在 2020/9/17 20:41, Jinyang He 写道:
Hi, Huacai,
On 09/16/2020 01:39 PM, Huacai Chen wrote:
Hi, Jinyang,
On Tue, Sep 15, 2020 at 10:17 PM Jinyang He
wrote:
On 09/16/2020 09:33 AM, Jiaxun Yang wrote:
于 2020年9月15日 GMT+08:00 下午9:07:43, Jinyang He
写到:
Add loongson_kexec_prepare
于 2020年9月15日 GMT+08:00 下午9:07:43, Jinyang He 写到:
>Add loongson_kexec_prepare(), loongson_kexec_shutdown() and
>loongson_kexec_crashdown() for passing the parameters of kexec_args.
>
>To start loongson64, CPU0 needs 3 parameters:
>fw_arg0: the number of cmd.
>fw_arg1: cmd structure which seems
在 2020/9/12 9:59, Youling Tang 写道:
Commit a94e4f24ec83 ("MIPS: init: Drop boot_mem_map") left
the BOOT_MEM_INIT_RAM unused, remove it.
Signed-off-by: Youling Tang
---
arch/mips/include/asm/bootinfo.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/mips/include/asm/bootinfo.h
在 2020/8/25 下午5:09, Thomas Bogendoerfer 写道:
Loonson2ef's mc146818rtc.h is the same as the generic one -> remove it.
Signed-off-by: Thomas Bogendoerfer
Acked-by: Jiaxun Yang
---
.../include/asm/mach-loongson2ef/mc146818rtc.h | 36 --
1 file changed,
This is causing lscpu segfault. So probably worthy to
include it as a part of mips-fixes.
Jiaxun Yang (2):
MIPS: cacheinfo: Add missing VCache
MIPS: Loongson64: Set cluster for cores
arch/mips/kernel/cacheinfo.c | 34 ++
arch/mips/loongson64/smp.c | 2
Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.
Signed-off-by: Jiaxun Yang
---
arch/mips/kernel/cacheinfo.c | 34 ++
1 file changed, 26 insertions(+), 8
When INTIMER is disabled by host, the GT compare interrupt
will be ignored.
Signed-off-by: Jiaxun Yang
---
arch/mips/kvm/vz.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index 9d03bd0a604a..1d2140f7461a 100644
--- a/arch/mips/kvm/vz.c
+++ b
Loongson64C and Loongson64G have extimer feature, which is sharing
Cause.TI with intimer (which is cevt-r4k).
To ensure the cevt-r4k's usability, we need to add a callback for
clock device to ensure intimer is enabled when cevt-r4k is enabled.
Signed-off-by: Jiaxun Yang
---
arch/mips/include
Some platforms may have shared Cause.TI, bailing out in IRQ handler
when clock event is not enabled can give another clock device a chance.
Signed-off-by: Jiaxun Yang
---
arch/mips/kernel/cevt-r4k.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel
Now we have hotplug aware reliable sync-r4k, we can simply use
that instead of our IPI based implementation.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/smp.h | 1 -
arch/mips/loongson64/smp.c | 32 ++--
2 files changed, 2 insertions(+), 31 deletions
There is no need to hijack initialization procudre to take care of
r4k timer we have CPUHP framework to deal with the CPU plug sequence.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/time.h | 28 +++-
arch/mips/kernel/cevt-r4k.c | 30
Now all platforms are sharing sync-r4k procdure, there is no need to let
platform to select it.
Signed-off-by: Jiaxun Yang
---
arch/mips/Kconfig | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 880680c0df31..7674f4379d39
d
at every plug event.
Here we reworked the whole procdure. Now the synchronise event on CPU0
is triggered by smp call function, and we won't touch the count on CPU0
at all.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/r4k-timer.h | 5 --
arch/mips/kernel/smp.c| 2 -
arch/m
Jiaxun Yang (7):
MIPS: sync-r4k: Rework to be many cores firendly
MIPS: time: Use CPUHUP to handle r4k timer
MIPS: Kconfig: Always select SYNC_R4K if both SMP and r4k timer is
enabled
MIPS: Loongson64: Remove custom count sync procudure
MIPS: cevt-r4k: Don't handle IRQ if clockevent
在 2020/8/11 下午10:37, Jiaxun Yang 写道:
在 2020/8/11 下午5:31, Xingxing Su 写道:
Commit c34b26b98caca48ec9ee9 ("KVM: MIPS: clean up redundant 'kvm_run'
parameters") remove the 'kvm_run' parameter in kvm_vz_gpsi_lwc2.
The following build error:
arch/mips/kvm/vz.c: I
在 2020/8/11 下午5:31, Xingxing Su 写道:
Commit c34b26b98caca48ec9ee9 ("KVM: MIPS: clean up redundant 'kvm_run'
parameters") remove the 'kvm_run' parameter in kvm_vz_gpsi_lwc2.
The following build error:
arch/mips/kvm/vz.c: In function ‘kvm_trap_vz_handle_gpsi’:
arch/mips/kvm/vz.c:1243:43:
kvm/emulate.c:1939:2: note: here
1939 | case lw_op:
Just fix it.
Signed-off-by: Jiaxun Yang
Reviewed-by: Huacai Chen
---
This is blocking KVM MIPS from build, so it needs to get into 5.9.
---
arch/mips/kvm/emulate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/m
在 2020/8/8 下午9:41, Thomas Bogendoerfer 写道:
On Sat, Aug 08, 2020 at 03:25:02PM +0800, Tiezhu Yang wrote:
Loongson processors have a writecombine issue that maybe failed to
write back framebuffer used with ATI Radeon or AMD GPU at times,
after commit 8a08e50cee66 ("drm: Permit video-buffers
Do not override ejtag feature to 0 as Loongson 3A1000+ do have ejtag.
For watch, as KVM emulated CPU doesn't have watch feature, we should
not enable it unconditionally.
Signed-off-by: Jiaxun Yang
---
This patch should go into mips-fixes tree as watch feature is blocking
KVM guest boot in some
在 2020/8/8 上午12:45, Paul Cercueil 写道:
Hi Zhou,
Le sam. 8 août 2020 à 0:23, Zhou Yanjie a
écrit :
Hi Paul,
I'm not too sure if remove "cpu-feature-overrides.h" will cause some
problems for X2000, because according to my current test on X2000, I
found that it is somewhat different from
在 2020/8/7 下午5:38, Álvaro Fernández Rojas 写道:
Current board declarations are a mess. Let's put some order and make them
follow the same structure.
Also remove board declarations tabs and double whitespace in the header.
Signed-off-by: Álvaro Fernández Rojas
---
在 2020/8/7 上午12:52, Thomas Bogendoerfer 写道:
On Thu, Aug 06, 2020 at 07:56:20PM +0800, Jiaxun Yang wrote:
Our current problem is Loongson's writecombine implementation seems buggy.
This is our platform issue rather than target hardware issue.
ok, so simply clear cpu_data[0].writecombine
在 2020/8/6 下午6:17, Thomas Bogendoerfer 写道:
On Thu, Aug 06, 2020 at 04:32:13PM +0800, Tiezhu Yang wrote:
On 08/06/2020 03:39 PM, Jiaxun Yang wrote:
在 2020/8/6 下午3:09, Tiezhu Yang 写道:
Loongson processors have a writecombine issue that maybe failed to
write back framebuffer used with ATI
在 2020/8/6 下午3:09, Tiezhu Yang 写道:
Loongson processors have a writecombine issue that maybe failed to
write back framebuffer used with ATI Radeon or AMD GPU at times,
after commit 8a08e50cee66 ("drm: Permit video-buffers writecombine
mapping for MIPS"), there exists some errors such as
在 2020/8/1 14:11, Jiaxun Yang 写道:
Requested by downstream distros, a Kconfig option for default
IEEE 754 conformance mode allows them to set their mode to
relaxed by default.
Signed-off-by: Jiaxun Yang
Reviewed-by: WANG Xuerui
Reviewed-by: Serge Semin
Reviewed-by: Huacai Chen
--
v2
在 2020/8/4 上午7:58, Joshua Kinard 写道:
On 8/3/2020 15:49, Mike Rapoport wrote:
Hi,
On Tue, Aug 04, 2020 at 01:39:14AM +0800, kernel test robot wrote:
Hi Mike,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head:
在 2020/8/3 上午5:46, Maciej W. Rozycki 写道:
On Fri, 31 Jul 2020, Serge Semin wrote:
Requested by downstream distros, a Kconfig option for default
IEEE754 conformance mode allows them to set their mode to
relaxed by default.
That's what should have been here in the first place. Thanks!
Requested by downstream distros, a Kconfig option for default
IEEE 754 conformance mode allows them to set their mode to
relaxed by default.
Signed-off-by: Jiaxun Yang
Reviewed-by: WANG Xuerui
Reviewed-by: Serge Semin
Reviewed-by: Huacai Chen
--
v2: Reword according to Xuerui's suggestion
在 2020/7/31 下午12:24, Florian Fainelli 写道:
Disable pref 30 by utilizing the standard quirk method and matching the
affected SoCs: 7344, 7346, 7425.
Signed-off-by: Florian Fainelli
---
arch/mips/bmips/setup.c | 17 +
1 file changed, 17 insertions(+)
diff --git
Requested by downstream distros, a Kconfig option for default
IEEE754 conformance mode allows them to set their mode to
relaxed by default.
Signed-off-by: Jiaxun Yang
---
arch/mips/Kconfig| 21 +
arch/mips/kernel/cpu-probe.c | 12 +++-
2 files changed, 32
Requested by downstream distros, a Kconfig option for default
IEEE754 conformance mode allows them to set their mode to
relaxed by default.
Signed-off-by: Jiaxun Yang
---
arch/mips/Kconfig| 21 +
arch/mips/kernel/cpu-probe.c | 12 +++-
2 files changed, 32
在 2020/7/30 上午9:40, Stephen Rothwell 写道:
Hi Jiaxun,
On Thu, 30 Jul 2020 09:04:40 +0800 Jiaxun Yang wrote:
Btw: Neither James nor Ralf is still active at Linux-MIPS.
Interesting. I have just them listed as my contacts for MIPS. Should
I change to just Thomes (Thomas Bogendoerfer
)?
Yes
在 2020/7/29 下午6:31, Stephen Rothwell 写道:
Hi all,
After merging the mips tree, today's linux-next build (powerpc
allnoconfig) produced this warning:
drivers/of/address.c:104:21: warning: 'of_bus_pci_get_flags' defined but not
used [-Wunused-function]
104 | static unsigned int
After 2f96593ecc37 ("of_address: Add bus type match for pci ranges parser"),
the last user of of_bus_pci_get_flags when CONFIG_PCI is disabled had gone.
This caused unused function warning when compiling without CONFIG_PCI.
Fix by guarding it with CONFIG_PCI.
Signed-off-by: Jiaxun Yang
在 2020/7/29 4:52, Thomas Bogendoerfer 写道:
On Tue, Jul 28, 2020 at 11:36:54PM +0800, Jiaxun Yang wrote:
Hi,
This series convert reservation of Loongson64 Logic PIO into DeviceTree based
method.
It can be used to replace Huacai's
"MIPS: Loongson64: Reserve legacy MMIO space acco
Although currently we're not enabling any ISA device in devicetree,
but this node is required to express the ranges of address reserved
for ISA.
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/boot/dts
It can be very big on LS7A PCH systems.
Signed-off-by: Jiaxun Yang
--
v3: Move IO_SPACE_LIMIT to spaces.h
---
arch/mips/include/asm/io.h | 2 --
arch/mips/include/asm/mach-generic/spaces.h| 4
arch/mips/include/asm/mach-loongson64/spaces.h | 3 +--
3 files changed
So the parser can be used to parse range property of ISA bus.
As they're all using PCI-like method of range property, there is no need
start a new parser.
Signed-off-by: Jiaxun Yang
Reviewed-by: Rob Herring
--
v2: Drop useless check, fix some na for bus_addr
add define
Previously, we're hardcoding reserved ISA I/O Space in, now
we're processing it I/O via DeviceTree directly.
The ranges property if ISA node is used to determine the size and address
of reserved I/O space.
Signed-off-by: Jiaxun Yang
--
v2: Use range_parser instead of pci_range_parser
v4: Fix
Ranges should express the actual physical address on bus.
Also enlarge the PCI I/O size to the actual hardware limit.
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/dts/loongson
s's review comments.
v4:
- Fix typo & grammar issue according to Xuerui's suggestion.
Jiaxun Yang (5):
of_address: Add bus type match for pci ranges parser
MIPS: Loongson64: Process ISA Node in DeviceTree
MIPS: Loongson64: Enlarge IO_SPACE_LIMIT
MIPS: Loongson64: DTS: Fix ISA and
Ranges should express the actual physical address on bus.
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
Although currently we're not enabling any ISA device in devicetree,
but this node is required to express the ranges of address reserved
for ISA.
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/boot/dts
It can be very big on LS7A PCH systems.
Signed-off-by: Jiaxun Yang
--
v3: Move IO_SPACE_LIMIT to spaces.h
---
arch/mips/include/asm/io.h | 2 --
arch/mips/include/asm/mach-generic/spaces.h| 4
arch/mips/include/asm/mach-loongson64/spaces.h | 3 +--
3 files changed
Previously, we're hardcoding resserved ISA I/O Space in code, now
we're processing reverved I/O via DeviceTree directly. Using the ranges
property to determine the size and address of reserved I/O space.
Signed-off-by: Jiaxun Yang
--
v2: Use range_parser instead of pci_range_parser
---
arch
s's review comments.
Jiaxun Yang (5):
of_address: Add bus type match for pci ranges parser
MIPS: Loongson64: Process ISA Node in DeviceTree
MIPS: Loongson64: Enlarge IO_SPACE_LIMIT
MIPS: Loongson64: DTS: Fix ISA range for RS780E PCH
MIPS: Loongson64: Add ISA node for LS7A PCH
arch/mip
So the parser can be used to parse range property of ISA bus.
As they're all using PCI-like method of range property, there is no need
start a new parser.
Signed-off-by: Jiaxun Yang
--
v2: Drop useless check, fix some na for bus_addr
add define of of_range_parser_init according
在 2020/7/21 下午10:17, Jiaxun Yang 写道:
It can be very big on LS7A PCH systems.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/io.h | 3 ++-
arch/mips/include/asm/mach-loongson64/spaces.h | 3 +--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch
Ranges should express the actual physical address on bus.
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
Previously, we're hardcoding resserved ISA I/O Space in code, now
we're processing reverved I/O via DeviceTree directly. Using the ranges
property to determine the size and address of reserved I/O space.
Signed-off-by: Jiaxun Yang
--
v2: Use range_parser instead of pci_range_parser
---
arch
It can be very big on LS7A PCH systems.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/io.h | 3 ++-
arch/mips/include/asm/mach-loongson64/spaces.h | 3 +--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include
Although currently we're not enabling any ISA device in devicetree,
but this node is required to express the ranges of address reserved
for ISA.
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/boot/dts
So the parser can be used to parse range property of ISA bus.
As they're all using PCI-like method of range property, there is no need
start a new parser.
Signed-off-by: Jiaxun Yang
--
v2: Drop useless check, fix some na for bus_addr
add define of of_range_parser_init according
Hi,
This series convert reservation of Loongson64 Logic PIO into DeviceTree based
method.
It can be used to replace Huacai's
"MIPS: Loongson64: Reserve legacy MMIO space according to bridge type".
Thanks.
v2:
- Address Rob and Huacai's review comments.
Jiaxun Yang (5):
of_addres
在 2020/7/20 下午6:45, Arnd Bergmann 写道:
On Mon, Jul 20, 2020 at 9:44 AM Jiaxun Yang wrote:
It can be very big on LS7A PCH systems.
Signed-off-by: Jiaxun Yang
---
* On MIPS I/O ports are memory mapped, so we access them using normal
diff --git a/arch/mips/include/asm/mach-loongson64
在 2020/7/20 下午7:44, Huacai Chen 写道:
Hi, Jiaxun,
On Mon, Jul 20, 2020 at 6:20 PM Jiaxun Yang wrote:
在 2020/7/20 下午6:01, Huacai Chen 写道:
Hi, Jiaxun,
On Mon, Jul 20, 2020 at 3:44 PM Jiaxun Yang wrote:
Previously, we're hardcoding resserved ISA I/O Space in code, now
we're processing
在 2020/7/20 下午6:01, Huacai Chen 写道:
Hi, Jiaxun,
On Mon, Jul 20, 2020 at 3:44 PM Jiaxun Yang wrote:
Previously, we're hardcoding resserved ISA I/O Space in code, now
we're processing reverved I/O via DeviceTree directly. Using the ranges
property to determine the size and address
Although currently we're not enabling any ISA device in devicetree,
but this node is required to express the ranges of address reserved
for ISA.
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/boot/dts
Hi,
This series convert reservation of Loongson64 Logic PIO into DeviceTree based
method.
It can be used to replace Huacai's
"MIPS: Loongson64: Reserve legacy MMIO space according to bridge type".
Thanks.
Jiaxun Yang (5):
of_address: Add bus type match for pci ranges par
So the parser can be used to parse range property of different bus
types, such as ISA bus.
As they're all using PCI-like method of range property, there is no need
start a new parser.
Signed-off-by: Jiaxun Yang
---
drivers/of/address.c | 15 +++
include/linux/of_address.h
It can be very big on LS7A PCH systems.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/io.h | 3 ++-
arch/mips/include/asm/mach-loongson64/spaces.h | 3 +--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include
Ranges should express the actual physical address on bus.
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
Previously, we're hardcoding resserved ISA I/O Space in code, now
we're processing reverved I/O via DeviceTree directly. Using the ranges
property to determine the size and address of reserved I/O space.
Signed-off-by: Jiaxun Yang
---
arch/mips/loongson64/init.c | 85
of these remaining redundant parameters.
Signed-off-by: Tianjia Zhang
Reviewed-by: Huacai Chen
Tested-by: Jiaxun Yang
Can confirm it works on Loongson-3A4000.
Thanks!
---
--
- Jiaxun
在 2020/7/13 16:52, Alexander A. Klimov 写道:
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
在 2020/7/12 18:01, kernel test robot 写道:
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 0aea6d5c5be33ce94c16f9ab2f64de1f481f424b
commit: ff487d41036035376e47972c7c522490b839ab37 MIPS: Truncate link address
into 32bit for 32bit kernel
date: 9 weeks
在 2020/7/11 9:35, Jiaxun Yang 写道:
在 2020/7/10 16:51, Zhi Li 写道:
Add gmac platform data to support LS7A bridge chip.
Co-developed-by: Hongbin Li
Signed-off-by: Hongbin Li
Signed-off-by: Zhi Li
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 22
++
1 file
在 2020/7/10 16:51, Zhi Li 写道:
Add gmac platform data to support LS7A bridge chip.
Co-developed-by: Hongbin Li
Signed-off-by: Hongbin Li
Signed-off-by: Zhi Li
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 22 ++
1 file changed, 22 insertions(+)
diff --git
by
community users, it's time to retire it if nobody steps in to maintain
it.
Signed-off-by: Jiaxun Yang
---
arch/mips/Kbuild.platforms| 1 -
arch/mips/Kconfig | 19 --
arch/mips/configs/mips_paravirt_defconfig | 98 --
arch/mips/include/asm/Kbuild
Retire some features that never worked in the real world.
Also I wonder if there are any actual user of TE KVM.
Will Huacai or Alexsander take care relevant code?
Thanks.
Jiaxun Yang (3):
MIPS: Retire kvm paravirt
MIPS: KVM: Limit Trap-and-Emulate to MIPS32R2 only
MIPS: KVM: Remove
This file was created long ago and information inside is
obviously outdated.
Signed-off-by: Jiaxun Yang
---
arch/mips/kvm/00README.txt | 31 ---
1 file changed, 31 deletions(-)
delete mode 100644 arch/mips/kvm/00README.txt
diff --git a/arch/mips/kvm/00README.txt b
After tons of fixes to get Trap-and-Emulate build on Loongson64,
I've got panic on host machine when trying to run a VM.
I found that it can never work on 64bit systems. Revewing the
code, it looks like R6 can't supportrd by TE as well.
Signed-off-by: Jiaxun Yang
---
arch/mips/Kconfig | 1
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: a23df9a4bd326fb4c7f160b72b0e0560b989ac29
Gitweb:
https://git.kernel.org/tip/a23df9a4bd326fb4c7f160b72b0e0560b989ac29
Author:Jiaxun Yang
AuthorDate:Sat, 30 May 2020 20:11:12 +08:00
Committer
On Fri, 5 Jun 2020 17:11:05 +0800
Bibo Mao wrote:
> On MIPS system which has rixi hardware bit, page access bit is not
> set in pgrot. For memory reading, there will be one page fault to
> allocate physical page; however valid bit is not set, there will
> be the second fast tlb-miss fault
On Wed, 3 Jun 2020 15:44:06 -0600
Jonathan Corbet wrote:
> Commit 632dcc2c75ef ("irqchip: Add Loongson PCH MSI controller")
> appears to suffer from a lack of copy-and-paste fixup, with the
> result that the KConfig description describes the wrong device.
> Avoid potential user confusion by
Jiaxun Yang (2):
irqchip: loongson-pci-msi: Fix a typo in Kconfig
irqchip: loongson-*: Fix COMPILE_TEST
drivers/irqchip/Kconfig| 2 +-
drivers/irqchip/irq-loongson-htpic.c | 4
drivers/irqchip/irq-loongson-htvec.c | 4
drivers/irqchip/irq-loongson-liointc.c
spurious_interrupt helper only exists on MIPS and x86,
so define a dummy function on other architectures to fix
COMPILE_TEST.
Reported-by: kbuild test robot
Signed-off-by: Jiaxun Yang
---
drivers/irqchip/irq-loongson-htpic.c | 4
drivers/irqchip/irq-loongson-htvec.c | 4
drivers
PCH MSI driver's tittle was wrong.
My stupid mistake.
Fixes: cca8fbff2585 ("irqchip: Add Loongson PCH MSI controller")
Signed-off-by: Jiaxun Yang
---
drivers/irqchip/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqch
The following commit has been merged into the irq/core branch of tip:
Commit-ID: da10a4b626657387845f32d37141fc7d48ebbdb3
Gitweb:
https://git.kernel.org/tip/da10a4b626657387845f32d37141fc7d48ebbdb3
Author:Jiaxun Yang
AuthorDate:Thu, 28 May 2020 23:27:54 +08:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 818e915fbac518e8c78e1877a0048d92d4965e5a
Gitweb:
https://git.kernel.org/tip/818e915fbac518e8c78e1877a0048d92d4965e5a
Author:Jiaxun Yang
AuthorDate:Thu, 28 May 2020 23:27:49 +08:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 6c2832c3c6edc38ab58bad29731b4951c0a90cf8
Gitweb:
https://git.kernel.org/tip/6c2832c3c6edc38ab58bad29731b4951c0a90cf8
Author:Jiaxun Yang
AuthorDate:Thu, 28 May 2020 23:27:50 +08:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: b6e4bc125fc517969f97d901b1845ebf47bbea26
Gitweb:
https://git.kernel.org/tip/b6e4bc125fc517969f97d901b1845ebf47bbea26
Author:Jiaxun Yang
AuthorDate:Thu, 28 May 2020 23:27:52 +08:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 632dcc2c75ef6de3272aa4ddd8f19da1f1ace323
Gitweb:
https://git.kernel.org/tip/632dcc2c75ef6de3272aa4ddd8f19da1f1ace323
Author:Jiaxun Yang
AuthorDate:Thu, 28 May 2020 23:27:53 +08:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: ef8c01eb64ca6719da449dab0aa9424e13c58bd0
Gitweb:
https://git.kernel.org/tip/ef8c01eb64ca6719da449dab0aa9424e13c58bd0
Author:Jiaxun Yang
AuthorDate:Thu, 28 May 2020 23:27:51 +08:00
Committer
compatible = "pci0014,7a24.0",
Just wonder if using such compatible string is allowed?
I've saw some some usages like mine in the tree, such as
arch/x86/platform/ce4100/falconfalls.dts, and
arch/mips/boot/dts/img/boston.dts.
If that's allowed, should we surpress these warnings in checkpatch
script?
Thanks.
--
Jiaxun Yang
于 2020年5月29日 GMT+08:00 下午12:13:36, Huacai Chen 写到:
>Hi, Jiaxun,
>
>On Fri, May 29, 2020 at 11:45 AM Jiaxun Yang wrote:
>>
>> With this series, LS7A and Loongson-3A4000 is finally supported
>> note that this series should depend on irqchip support[1], which
>
On Tue, 26 May 2020 10:53:15 +0100
Marc Zyngier wrote:
> On 2020-05-26 10:26, Jiaxun Yang wrote:
> > On Mon, 25 May 2020 11:12:26 +0100
> > Marc Zyngier wrote:
> >
> >> On Sat, 16 May 2020 09:29:02 +0100,
> >> Jiaxun Yang wrote:
> >> &g
Load correct devicetree according to PRID and PCH type.
Signed-off-by: Jiaxun Yang
---
arch/mips/loongson64/env.c | 56 +++---
1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index
DeviceTree for Loongson-3 Quad core + LS7A boards
and Loongson-3 Release 4 + LS7A boards.
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/Makefile | 5 +-
.../dts/loongson/loongson3-r4-package.dtsi| 74 +++
.../dts/loongson/loongson3_4core_ls7a.dts | 25
Document loongson3-8core-ls7a and loongson3-r4-ls7a, with
two boards LS7A PCH.
Signed-off-by: Jiaxun Yang
---
.../devicetree/bindings/mips/loongson/devices.yaml| 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml
b
With this series, LS7A and Loongson-3A4000 is finally supported
note that this series should depend on irqchip support[1], which
is likely to get merged soon.
Thanks.
[1]: https://lkml.org/lkml/2020/5/16/72
Jiaxun Yang (3):
dt-bindings: mips: Document two Loongson generic boards
MIPS
Add binding for Loongson PCH PIC Controller.
Signed-off-by: Jiaxun Yang
--
v2:
- Fix naming
- Mark loongson,pic-base-vec as required
v5:
- Add range check for loongson,pic-base-vec
---
.../loongson,pch-pic.yaml | 56 +++
1 file changed
Add binding for Loongson PCH MSI controller.
Signed-off-by: Jiaxun Yang
Reviewed-by: Rob Herring
--
v5: Add range check for msi-base-vec & msi-num-vecs
---
.../loongson,pch-msi.yaml | 62 +++
1 file changed, 62 insertions(+)
create mode 10
This controller appears on Loongson LS7A family of PCH to transform
interrupts from PCI MSI into HyperTransport vectorized interrrupts
and send them to procrssor's HT vector controller.
Signed-off-by: Jiaxun Yang
--
v2:
- Style clean-ups
- Add ack callback
- Use
This controller appears on Loongson-3 chips for receiving interrupt
vectors from PCH's PIC and PCH's PCIe MSI interrupts.
Signed-off-by: Jiaxun Yang
---
v2:
- Style cleanup
- Set ack callback and set correct edge_irq handler
v3:
- Correct bitops in ACK callback
v4
Add binding for Loongson-3 HyperTransport Interrupt Vector Controller.
Signed-off-by: Jiaxun Yang
--
v4: Drop ref, '|', add additionalProperties, fix example
---
.../interrupt-controller/loongson,htvec.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
This controller appears on Loongson LS7A family of PCH to transform
interrupts from devices into HyperTransport vectorized interrrupts
and send them to procrssor's HT vector controller.
Signed-off-by: Jiaxun Yang
---
v2:
- Style clean-ups
- Use IRQ_FASTEOI_HIERARCHY_HANDLERS
v5:
- Add some range checks in dt-schema
Jiaxun Yang (6):
irqchip: Add Loongson HyperTransport Vector support
dt-bindings: interrupt-controller: Add Loongson HTVEC
irqchip: Add Loongson PCH PIC controller
dt-bindings: interrupt-controller: Add Loongson PCH PIC
irqchip: Add Loongson
PCI_IOBASE is used to create VM maps for PCI I/O ports, it is
required by generic PCI drivers to make memory mapped I/O range
work.
To deal with legacy drivers that have fixed I/O ports range we
reserved 0x1 in PCI_IOBASE, should be enough for i8259 i8042
stuff.
Signed-off-by: Jiaxun Yang
On Wed, 27 May 2020 13:53:54 +0200
Thomas Bogendoerfer wrote:
> On Wed, May 27, 2020 at 02:34:33PM +0800, Jiaxun Yang wrote:
> > That's what already done by Arm64 and other architectures.
> > That would allow us put more things like PE headers safely into
> > the header
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