Walk the guest page tables via a loop when searching for a PTE,
instead of using unique variables for each level of the page tables.
This simplifies the code and makes it easier to support 5-level paging
in the future.
Signed-off-by: Jim Mattson
---
.../testing/selftests/kvm/lib/x86
Add a selftest that verifies KVM's ability to save and restore
nested state when the L1 guest is using 5-level paging and the L2
guest is using 4-level paging. Specifically, canonicality tests of
the VMCS12 host-state fields should accept 57-bit virtual addresses.
Signed-off-by: Jim Ma
Add a new VM mode, VM_MODE_PXXV57_4K, to support tests that require
5-level paging on x86. This mode sets up a 57-bit virtual address
space and sets CR4.LA57 in the guest.
Signed-off-by: Jim Mattson
---
.../testing/selftests/kvm/include/kvm_util.h | 1 +
tools/testing/selftests/kvm/lib
Walk the guest page tables via a loop when creating new mappings,
instead of using unique variables for each level of the page tables.
This simplifies the code and makes it easier to support 5-level paging
in the future.
Signed-off-by: Jim Mattson
---
.../testing/selftests/kvm/lib/x86
eater than 48 bits wide.
Add a regression test that reproduces the KVM_SET_NESTED_STATE failure
conditions. To do so, the first three patches add support for 5-level
paging in the selftest L1 VM.
Jim Mattson (4):
KVM: selftests: Use a loop to create guest page tables
KVM: selftests: Use a lo
: fix memory leak in kvm_io_bus_unregister_dev()")
> Cc: sta...@vger.kernel.org
> Reported-by: Hao Sun
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
;dev_count; i++)
> + for (i = 0; i < bus->dev_count; i++) {
> if (bus->range[i].dev == dev) {
> break;
> }
> + }
Per coding-style.rst, neither the for loop nor the if-block should have braces.
"Do not unnecessarily use braces where a single statement will do."
Stylistic nits aside,
Reviewed-by: Jim Mattson
> could lead to use-after-free since readers expect the devices on their
> reference of the bus to remain valid.
>
> Fixes: f65886606c2d ("KVM: fix memory leak in kvm_io_bus_unregister_dev()")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
On Mon, Apr 12, 2021 at 6:09 AM David Edmondson
wrote:
>
> Instruction emulation happens for a variety of reasons, yet on error
> we have no idea exactly what triggered it. Add a cause of emulation to
> the various originators and pass it upstream when emulation fails.
What is userspace going to
> >
> > Babu, Jim, I'd appreciate it if you ran this to confirm.
Tested-by: Jim Mattson
On Mon, Mar 22, 2021 at 7:37 PM wrote:
>
> From: Haiwei Li
>
> According to IA-32 SDM Vol.3D "A.1 BASIC VMX INFORMATION", two inspections
> are missing.
> * Bit 31 is always 0. Earlier versions of this manual specified that the
> VMCS revision identifier was a 32-bit field in bits 31:0 of this MS
On Thu, Mar 11, 2021 at 12:32 PM Borislav Petkov wrote:
>
> On Thu, Mar 11, 2021 at 09:07:55PM +0100, Borislav Petkov wrote:
> > On Wed, Mar 10, 2021 at 07:21:23PM -0600, Babu Moger wrote:
> > > # git bisect good
> > > 59094faf3f618b2d2b2a45acb916437d611cede6 is the first bad commit
> > > commit 5
On Wed, Mar 10, 2021 at 7:24 AM Andi Kleen wrote:
>
> The pebs_no_isolation optimization check is inverted. We want to disable
> PEBS isolation when the microcode is at least the revision in the table,
> not for older microcode. So remove the extra !.
The original code was correct because of the d
non-NULL.
>
> Fixes: abd562df94d1 ("x86/perf: Use static_call for x86_pmu.guest_get_msrs")
> Cc: Like Xu
> Cc: Paolo Bonzini
> Cc: Jim Mattson
> Reported-by: Dmitry Vyukov
> Reported-by: syzbot+cce9ef2dd25246f81...@syzkaller.appspotmail.com
> Suggested-by: Pe
1/20/21 3:45 PM, Babu Moger wrote:
> >>>
> >>>
> >>> On 1/20/21 3:14 PM, Jim Mattson wrote:
> >>>> On Tue, Jan 19, 2021 at 3:45 PM Babu Moger wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>
On Fri, Feb 19, 2021 at 6:46 AM David Edmondson
wrote:
>
> If the VM entry/exit controls for loading/saving MSR_EFER are either
> not available (an older processor or explicitly disabled) or not
> used (host and guest values are the same), reading GUEST_IA32_EFER
> from the VMCS returns an inaccur
On Tue, Feb 23, 2021 at 2:51 PM Sean Christopherson wrote:
>
> On Fri, Feb 19, 2021, David Edmondson wrote:
> > If the VM entry/exit controls for loading/saving MSR_EFER are either
> > not available (an older processor or explicitly disabled) or not
> > used (host and guest values are the same), r
On Thu, Feb 18, 2021 at 8:35 AM Sean Christopherson wrote:
>
> On Thu, Feb 18, 2021, Paolo Bonzini wrote:
> > On 18/02/21 13:56, David Edmondson wrote:
> > > On Thursday, 2021-02-18 at 12:54:52 +01, Paolo Bonzini wrote:
> > >
> > > > On 18/02/21 11:04, David Edmondson wrote:
> > > > > When dumping
if/when it showed up in the kernel on AMD hardware.
>
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
Babu Moger
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
o limiting the
> number of ASIDs consumed by the guest.
>
> Signed-off-by: Sean Christopherson
I always thought this was a bizarre one-off restriction.
Reviewed-by: Jim Mattson
The following commit has been merged into the perf/core branch of tip:
Commit-ID: b3c3361fe325074d4144c29d46daae4fc5a268d5
Gitweb:
https://git.kernel.org/tip/b3c3361fe325074d4144c29d46daae4fc5a268d5
Author:Jim Mattson
AuthorDate:Fri, 05 Feb 2021 11:13:24 -08:00
Committer
On a host that suffers from pebs_no_isolation, perf_guest_get_msrs()
adds an entry to cpuc->guest_switch_msrs for
MSR_IA32_PEBS_ENABLE. Kvm's atomic_switch_perf_msrs() is the only
caller of perf_guest_get_msrs(). If atomic_switch_perf_msrs() finds an
entry for MSR_IA32_PEBS_ENABLE in cpuc->guest_sw
isolation_ucodes[] table so that these parts benefit from Andi's
optimization in commit 9b545c04abd4f ("perf/x86/kvm: Avoid unnecessary
work in guest filtering").
Signed-off-by: Jim Mattson
Cc: Andi Kleen
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Arnaldo Carvalho de Melo
Cc: M
On Wed, Jan 20, 2021 at 1:16 PM Jim Mattson wrote:
>
> On Fri, Jan 15, 2021 at 11:35 AM Jim Mattson wrote:
> >
> > On Fri, Oct 23, 2020 at 10:43 AM Paolo Bonzini wrote:
> > >
> > > On 23/10/20 19:23, Jim Mattson wrote:
> > > >> The information
isolation_ucodes[] table so that these parts benefit from Andi's
optimization in commit 9b545c04abd4f ("perf/x86/kvm: Avoid unnecessary
work in guest filtering").
Signed-off-by: Jim Mattson
Cc: Andi Kleen
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Arnaldo Carvalho de Melo
Cc: M
On Fri, Jan 15, 2021 at 11:35 AM Jim Mattson wrote:
>
> On Fri, Oct 23, 2020 at 10:43 AM Paolo Bonzini wrote:
> >
> > On 23/10/20 19:23, Jim Mattson wrote:
> > >> The information that we need is _not_ that provided by the advanced
> > >> VM-exit info
On Tue, Jan 19, 2021 at 3:45 PM Babu Moger wrote:
>
>
>
> On 1/19/21 5:01 PM, Jim Mattson wrote:
> > On Mon, Sep 14, 2020 at 11:33 AM Babu Moger wrote:
> >
> >> Thanks Paolo. Tested Guest/nested guest/kvm units tests. Everything works
> >> as expected.
On Mon, Sep 14, 2020 at 11:33 AM Babu Moger wrote:
> Thanks Paolo. Tested Guest/nested guest/kvm units tests. Everything works
> as expected.
Debian 9 does not like this patch set. As a kvm guest, it panics on a
Milan CPU unless booted with 'nopcid'. Gmail mangles long lines, so
please see the a
On Thu, Sep 3, 2020 at 7:12 AM Mohammed Gamal wrote:
>
> This patch exposes allow_smaller_maxphyaddr to the user as a module parameter.
>
> Since smaller physical address spaces are only supported on VMX, the parameter
> is only exposed in the kvm_intel module.
> Modifications to VMX page fault an
On Fri, Oct 23, 2020 at 10:43 AM Paolo Bonzini wrote:
>
> On 23/10/20 19:23, Jim Mattson wrote:
> >> The information that we need is _not_ that provided by the advanced
> >> VM-exit information (or by a page walk). If a page is neither writable
> >> nor exe
On Wed, Apr 4, 2018 at 10:44 PM Paolo Bonzini wrote:
>
> On 04/04/2018 19:35, Stefan Fritsch wrote:
> > On Wednesday, 4 April 2018 19:24:20 CEST Paolo Bonzini wrote:
> >> On 04/04/2018 19:10, Konrad Rzeszutek Wilk wrote:
> >>> Should there be a corresponding test-case?
> >>
> >> Good point! Stefa
It looks like userspace can possibly induce this by providing guest
CPUID information with a "physical address width" of 64 in leaf
0x8008.
Perhaps cpuid_query_maxphyaddr() should just look at the low 5 bits of
CPUID.8008H:EAX? Better would be to return an error for
out-of-range values, bu
On Thu, Dec 10, 2020 at 1:26 PM Babu Moger wrote:
>
> Hi Jim,
>
> > -Original Message-----
> > From: Jim Mattson
> > Sent: Monday, December 7, 2020 5:06 PM
> > To: Moger, Babu
> > Cc: Paolo Bonzini ; Thomas Gleixner
> > ; Ingo Molnar ;
On Wed, Dec 9, 2020 at 2:39 PM Babu Moger wrote:
>
>
>
> On 12/7/20 5:22 PM, Jim Mattson wrote:
> > On Mon, Dec 7, 2020 at 2:38 PM Babu Moger wrote:
> >>
> >> Newer AMD processors have a feature to virtualize the use of the SPEC_CTRL
> >> MSR. This f
On Mon, Dec 7, 2020 at 3:47 AM stsp wrote:
>
> 07.12.2020 14:29, Paolo Bonzini пишет:
> > On 07/12/20 12:24, stsp wrote:
> >> It tries to enable VME among other things.
> >> qemu appears to disable VME by default,
> >> unless you do "-cpu host". So we have a situation where
> >> the host (which is
On Mon, Dec 7, 2020 at 2:38 PM Babu Moger wrote:
>
> Newer AMD processors have a feature to virtualize the use of the SPEC_CTRL
> MSR. This feature is identified via CPUID 0x800A_EDX[20]. When present,
> the SPEC_CTRL MSR is automatically virtualized and no longer requires
> hypervisor interve
On Mon, Dec 7, 2020 at 2:38 PM Babu Moger wrote:
>
> Newer AMD processors have a feature to virtualize the use of the
> SPEC_CTRL MSR. When supported, the SPEC_CTRL MSR is automatically
> virtualized and no longer requires hypervisor intervention.
>
> This feature is detected via CPUID function 0x
t; change; without this patch, instead, CR4 would be checked against the
> previous value for L2 on vmentry, and against the previous value for
> L1 on vmexit, and CPUID would not be updated.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Jim Mattson
On Mon, Nov 9, 2020 at 2:57 PM Luck, Tony wrote:
>
> > I thought Linux had long ago gone the route of turning rdmsr/wrmsr
> > into rdmsr_safe/wrmsr_safe, so that the guest would ignore the #GPs on
> > writes and return zero to the caller for #GPs on reads.
>
> Linux just switched that around for t
On Mon, Nov 9, 2020 at 2:09 PM Luck, Tony wrote:
>
> What does KVM do with model specific MSRs?
"Model specific model-specific registers?" :-)
KVM only implements a small subset of MSRs. By default, any access to
the rest raises #GP.
> Looks like you let the guest believe it was running on one
On Sun, Nov 1, 2020 at 10:14 PM Tao Xu wrote:
>
> There are some cases that malicious virtual machines can cause CPU stuck
> (event windows don't open up), e.g., infinite loop in microcode when
> nested #AC (CVE-2015-5307). No event window obviously means no events,
> e.g. NMIs, SMIs, and IRQs wil
On Fri, Oct 23, 2020 at 10:16 AM Paolo Bonzini wrote:
>
> On 23/10/20 18:59, Jim Mattson wrote:
> >> The problem is that page fault error code bits cannot be reconstructed
> >> from bits 0..2 of the EPT violation exit qualification, if bit 8 is
> >> clear in th
On Fri, Oct 23, 2020 at 2:07 AM Paolo Bonzini wrote:
>
> On 22/10/20 19:13, Jim Mattson wrote:
> > We don't actually use KVM_GET_SUPPORTED_CPUID at all today. If it's
> > commonly being misinterpreted as you say, perhaps we should add a
> > KVM_GET_TRUE_SUPPORT
On Fri, Oct 23, 2020 at 2:22 AM Paolo Bonzini wrote:
>
> On 23/10/20 05:14, Sean Christopherson wrote:
> +
> + /*
> +* Check that the GPA doesn't exceed physical memory limits, as
> that is
> +* a guest page fault. We have to emulate the instruction
On Thu, Oct 22, 2020 at 9:37 AM Paolo Bonzini wrote:
>
> On 22/10/20 18:35, Jim Mattson wrote:
> > On Thu, Oct 22, 2020 at 6:02 AM Paolo Bonzini wrote:
> >>
> >> On 22/10/20 03:34, Wanpeng Li wrote:
> >>> From: Wanpeng Li
> >>>
> > hardware and kvm in its default configuration.
> >
> > A well-behaved userspace should not set the bit if it is not supported.
> >
> > Suggested-by: Jim Mattson
> > Signed-off-by: Wanpeng Li
>
> It's common for userspace to copy all supported CPUID bits to
On Fri, Oct 9, 2020 at 9:17 AM Jim Mattson wrote:
>
> On Fri, Jul 10, 2020 at 8:48 AM Mohammed Gamal wrote:
> >
> > Check guest physical address against it's maximum physical memory. If
> > the guest's physical address exceeds the maximum (i.e. has reserved
On Fri, Jul 10, 2020 at 8:48 AM Mohammed Gamal wrote:
>
> Check guest physical address against it's maximum physical memory. If
> the guest's physical address exceeds the maximum (i.e. has reserved bits
> set), inject a guest page fault with PFERR_RSVD_MASK set.
>
> This has to be done both in the
On Wed, Aug 12, 2020 at 10:51 AM Sean Christopherson
wrote:
>
> On successful nested VM-Enter, check for pending interrupts and convert
> the highest priority interrupt to a pending posted interrupt if it
> matches L2's notification vector. If the vCPU receives a notification
> interrupt before n
On Thu, Sep 10, 2020 at 2:51 AM Wanpeng Li wrote:
>
> From: Wanpeng Li
>
> According to SDM 27.2.4, Event delivery causes an APIC-access VM exit.
> Don't report internal error and freeze guest when event delivery causes
> an APIC-access exit, it is handleable and the event will be re-injected
> d
on Lewis
> Signed-off-by: Alexander Graf
Reviewed-by: Jim Mattson
s that triggers PDPTR loads also being used to trigger MMU context
> resets.
>
> Fixes: 427890aff855 ("kvm: x86: Toggling CR4.SMAP does not load PDPTEs in PAE
> mode")
> Fixes: cb957adb4ea4 ("kvm: x86: Toggling CR4.PKE does not load PDPTEs in PAE
> mode")
>
On Thu, Sep 24, 2020 at 11:42 AM Tom Lendacky wrote:
>
> From: Tom Lendacky
>
> This series updates the INVD intercept support for both SVM and VMX to
> skip the instruction rather than emulating it, since emulation of this
> instruction is just a NOP.
Isn't INVD a serializing instruction, where
On Wed, Sep 23, 2020 at 9:51 AM Sean Christopherson
wrote:
>
> If PCID is not exposed to the guest, clear INVPCID in the guest's CPUID
> even if the VMCS INVPCID enable is not supported. This will allow
> consolidating the secondary execution control adjustment code without
> having to special ca
>
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
On Thu, Sep 3, 2020 at 1:02 PM Paolo Bonzini wrote:
>
> On 03/09/20 20:32, Jim Mattson wrote:
> >> [Checking writes to CR3] would be way too slow. Even the current
> >> trapping of present #PF can introduce some slowdown depending on the
> >> workload.
> &
On Thu, Sep 3, 2020 at 11:03 AM Paolo Bonzini wrote:
>
> On 03/09/20 19:57, Jim Mattson wrote:
> > On Thu, Sep 3, 2020 at 7:12 AM Mohammed Gamal wrote:
> >> This patch exposes allow_smaller_maxphyaddr to the user as a module
> >> parameter.
> >>
> &g
On Thu, Sep 3, 2020 at 7:12 AM Mohammed Gamal wrote:
>
> This patch exposes allow_smaller_maxphyaddr to the user as a module parameter.
>
> Since smaller physical address spaces are only supported on VMX, the parameter
> is only exposed in the kvm_intel module.
> Modifications to VMX page fault an
On Wed, Sep 2, 2020 at 11:16 AM Sean Christopherson
wrote:
>
> On Fri, Aug 28, 2020 at 01:39:39PM -0700, Jim Mattson wrote:
> > On Fri, Aug 28, 2020 at 1:54 AM Chenyi Qiang wrote:
> > >
> > > Update the fields (i.e. VM_{ENTRY_LOAD, EXIT_CLEAR}_BND
On Fri, Aug 28, 2020 at 7:51 PM Xiaoyao Li wrote:
>
> On 8/29/2020 9:49 AM, Chenyi Qiang wrote:
> >
> >
> > On 8/29/2020 1:43 AM, Jim Mattson wrote:
> >> On Fri, Aug 28, 2020 at 1:54 AM Chenyi Qiang
> >> wrote:
> >>>
> >>> KVM s
On Fri, Aug 28, 2020 at 1:54 AM Chenyi Qiang wrote:
>
> Update the fields (i.e. VM_{ENTRY_LOAD, EXIT_CLEAR}_BNDCFGS and
> VM_{ENTRY, EXIT}_LOAD_IA32_PERF_GLOBAL_CTRL) in
> nested MSR_IA32_VMX_TRUE_{ENTRY, EXIT}_CTLS according to guest CPUID
> when user space initializes the features MSRs. Regardle
by: Chenyi Qiang
> Reviewed-by: Xiaoyao Li
Reviewed-by: Jim Mattson
On Fri, Aug 28, 2020 at 1:54 AM Chenyi Qiang wrote:
>
> When setting the nested VMX MSRs, verify it with the values in
> vmcs_config.nested_vmx_msrs, which reflects the global capability of
> VMX controls MSRs.
>
> Signed-off-by: Chenyi Qiang
You seem to have entirely missed the point of this co
On Fri, Aug 28, 2020 at 1:54 AM Chenyi Qiang wrote:
>
> KVM supports the nested VM_{EXIT, ENTRY}_LOAD_IA32_PERF_GLOBAL_CTRL and
> VM_{ENTRY_LOAD, EXIT_CLEAR}_BNDCFGS, but they doesn't expose during
> the setup of nested VMX controls MSR.
>
Aren't these features added conditionally in
nested_vmx_e
On Mon, Jul 13, 2020 at 11:23 AM Jim Mattson wrote:
>
> On Mon, Jul 13, 2020 at 9:22 AM Vitaly Kuznetsov wrote:
> >
> > Before commit 850448f35aaf ("KVM: nVMX: Fix VMX preemption timer
> > migration") struct kvm_vmx_nested_state_hdr looked like:
>
On Wed, Aug 26, 2020 at 12:15 PM Babu Moger wrote:
>
> Handling of kvm_read/write_guest_virt*() errors can be moved to common
> code. The same code can be used by both VMX and SVM.
>
> Signed-off-by: Babu Moger
Reviewed-by: Jim Mattson
off-by: Babu Moger
> Reviewed-by: Jim Mattson
> ---
> @@ -835,7 +832,7 @@ static bool nested_exit_on_exception(struct vcpu_svm *svm)
> {
> unsigned int nr = svm->vcpu.arch.exception.nr;
>
> - return (svm->nested.ctl.intercept_exceptions & (1 <
On Wed, Aug 26, 2020 at 12:14 PM Babu Moger wrote:
>
> Modify intercept_dr to generic intercepts in vmcb_control_area. Use
> the generic vmcb_set_intercept, vmcb_clr_intercept and vmcb_is_intercept
> to set/clear/test the intercept_dr bits.
>
> Signed-off-by: Babu Moger
Reviewed-by: Jim Mattson
On Wed, Aug 26, 2020 at 12:14 PM Babu Moger wrote:
>
> Change intercept_cr to generic intercepts in vmcb_control_area.
> Use the new vmcb_set_intercept, vmcb_clr_intercept and vmcb_is_intercept
> where applicable.
>
> Signed-off-by: Babu Moger
Reviewed-by: Jim Mattson
: "respectively"
>
> Signed-off-by: Babu Moger
Reviewed-by: Jim Mattson
On Mon, Aug 24, 2020 at 11:57 AM Jim Mattson wrote:
>
> On Fri, Aug 21, 2020 at 8:40 PM Sean Christopherson
> wrote:
> >
> > On Thu, Aug 20, 2020 at 01:08:22PM -0700, Jim Mattson wrote:
> > > On Wed, Apr 1, 2020 at 1:13 AM Vitaly Kuznetsov
> > > wrote
On Fri, Aug 21, 2020 at 8:40 PM Sean Christopherson
wrote:
>
> On Thu, Aug 20, 2020 at 01:08:22PM -0700, Jim Mattson wrote:
> > On Wed, Apr 1, 2020 at 1:13 AM Vitaly Kuznetsov wrote:
> > > ---
> > > arch/x86/kvm/vmx/vmx.c | 12 +++-
> > > 1 fil
On Thu, Aug 20, 2020 at 6:34 AM Maxim Levitsky wrote:
>
> This will be used later to return an error when setting this msr fails.
>
> For VMX, it already has an error condition when EFER is
> not in the shared MSR list, so return an error in this case.
>
> Signed-off-by: Maxim Levitsky
> ---
> -
On Thu, Aug 20, 2020 at 6:34 AM Maxim Levitsky wrote:
>
> Replace svm_vcpu_init_msrpm with svm_vcpu_alloc_msrpm, that also allocates
> the msr bitmap and add svm_vcpu_free_msrpm to free it.
>
> This will be used later to move the nested msr permission bitmap allocation
> to nested.c
>
> No functio
- svm->nested.vmcb = 0;
> + svm->nested.vmcb12_gpa = 0;
Here, too, perhaps this could be changed from 0 to an illegal value in
a follow-up change.
Reviewed-by: Jim Mattson
On Thu, Aug 20, 2020 at 6:33 AM Maxim Levitsky wrote:
>
> The 'page' is to hold the vcpu's vmcb so name it as such to
> avoid confusion.
>
> Signed-off-by: Maxim Levitsky
Reviewed-by: Jim Mattson
On Wed, Apr 1, 2020 at 1:13 AM Vitaly Kuznetsov wrote:
>
> If KVM wasn't used at all before we crash the cleanup procedure fails with
> BUG: unable to handle page fault for address: ffc8
> #PF: supervisor read access in kernel mode
> #PF: error_code(0x) - not-present page
> PGD
On Thu, Aug 20, 2020 at 11:38 AM Jim Mattson wrote:
>
> On Thu, Aug 20, 2020 at 11:34 AM Tom Lendacky wrote:
> >
> > On 8/20/20 11:30 AM, Tom Lendacky wrote:
> > > On 8/20/20 11:17 AM, Tom Lendacky wrote:
> > >> On 8/20/20 10:55 AM, Andy Lutomirski wrote:
On Thu, Aug 20, 2020 at 11:34 AM Tom Lendacky wrote:
>
> On 8/20/20 11:30 AM, Tom Lendacky wrote:
> > On 8/20/20 11:17 AM, Tom Lendacky wrote:
> >> On 8/20/20 10:55 AM, Andy Lutomirski wrote:
> >>> On Thu, Aug 20, 2020 at 8:21 AM Tom Lendacky
> >>> wrote:
>
> On 8/20/20 10:10 AM, Sean C
On Wed, Aug 19, 2020 at 3:09 PM Jim Mattson wrote:
>
> On Wed, Aug 19, 2020 at 2:46 PM Graf (AWS), Alexander wrote:
>
> > Special MSRs like EFER also irritate me a bit. We can't really trap on them
> > - most code paths just know they're handled in kernel. Maybe I
On Mon, Aug 3, 2020 at 2:14 PM Alexander Graf wrote:
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -901,6 +901,13 @@ struct kvm_hv {
> struct kvm_hv_syndbg hv_syndbg;
> };
>
> +struct msr_bitmap_range {
> + u32 flags;
> + u32 nmsrs;
> +
On Wed, Aug 19, 2020 at 2:46 PM Graf (AWS), Alexander wrote:
> Special MSRs like EFER also irritate me a bit. We can't really trap on them -
> most code paths just know they're handled in kernel. Maybe I'll add some
> sanity checks as well...
Why can't we intercept EFER?
On Mon, Aug 3, 2020 at 2:14 PM Alexander Graf wrote:
>
> While tying to add support for the MSR_CORE_THREAD_COUNT MSR in KVM,
> I realized that we were still in a world where user space has no control
> over what happens with MSR emulation in KVM.
>
> That is bad for multiple reasons. In my case,
On Tue, Aug 18, 2020 at 12:28 AM Chenyi Qiang wrote:
>
>
>
> On 8/14/2020 1:31 AM, Jim Mattson wrote:
> > On Wed, Aug 12, 2020 at 10:42 PM Chenyi Qiang
> > wrote:
> >>
> >>
> >>
> >> On 8/13/2020 5:21 AM, Jim Mattson wrote:
>
On Fri, Aug 14, 2020 at 3:09 AM Chenyi Qiang wrote:
>
>
>
> On 8/14/2020 1:52 AM, Jim Mattson wrote:
> > On Wed, Aug 12, 2020 at 9:54 PM Chenyi Qiang wrote:
> >>
> >>
> >>
> >> On 8/11/2020 8:05 AM, Jim Mattson wrote:
> >
On Fri, Aug 7, 2020 at 1:47 AM Chenyi Qiang wrote:
>
> Existence of PKS is enumerated via CPUID.(EAX=7H,ECX=0):ECX[31]. It is
> enabled by setting CR4.PKS when long mode is active. PKS is only
> implemented when EPT is enabled and requires the support of VM_{ENTRY,
> EXIT}_LOAD_IA32_PKRS currently
On Wed, Aug 12, 2020 at 9:54 PM Chenyi Qiang wrote:
>
>
>
> On 8/11/2020 8:05 AM, Jim Mattson wrote:
> > On Fri, Aug 7, 2020 at 1:47 AM Chenyi Qiang wrote:
> >>
> >> PKS MSR passes through guest directly. Configure the MSR to match the
> >> L0/L1
On Wed, Aug 12, 2020 at 10:42 PM Chenyi Qiang wrote:
>
>
>
> On 8/13/2020 5:21 AM, Jim Mattson wrote:
> > On Fri, Aug 7, 2020 at 1:46 AM Chenyi Qiang wrote:
> >>
> >> Protection Keys for Supervisor Pages (PKS) uses IA32_PKRS MSR (PKRS) at
> >> index
On Fri, Aug 7, 2020 at 1:46 AM Chenyi Qiang wrote:
>
> Protection Keys for Supervisor Pages (PKS) uses IA32_PKRS MSR (PKRS) at
> index 0x6E1 to allow software to manage supervisor protection key
> rights. For performance consideration, PKRS intercept will be disabled
> so that the guest can access
On Wed, Aug 12, 2020 at 8:00 AM Sean Christopherson
wrote:
>
> On Mon, Aug 10, 2020 at 05:05:36PM -0700, Jim Mattson wrote:
> > On Fri, Aug 7, 2020 at 1:47 AM Chenyi Qiang wrote:
> > >
> > > PKS MSR passes through guest directly. Configure the MSR to match the
>
On Fri, Aug 7, 2020 at 1:47 AM Chenyi Qiang wrote:
>
> PKS MSR passes through guest directly. Configure the MSR to match the
> L0/L1 settings so that nested VM runs PKS properly.
>
> Signed-off-by: Chenyi Qiang
> ---
> arch/x86/kvm/vmx/nested.c | 32
> arch/x86/k
2_PKRS = 1, VM exit loads PKRS from the host-state
> area.
> If VM_ENTRY_LOAD_IA32_PKRS = 1, VM entry loads PKRS from the guest-state
> area.
>
> Signed-off-by: Chenyi Qiang
Reviewed-by: Jim Mattson
Manual Volume 2: System Programming,
> Pub. 24593 Rev. 3.34(or later)"
>
> The documentation can be obtained at the links below:
> Link: https://www.amd.com/system/files/TechDocs/24593.pdf
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
>
> Signed-off-by: Babu Moger
Reviewed-by: Jim Mattson
t; > "else if" case is a mess.
> >
> > Fixes: d42e3fae6faed ("kvm: x86: Read PDPTEs on CR0.CD and CR0.NW changes")
> > Cc: Jim Mattson
> > Cc: Oliver Upton
> > Cc: Peter Shier
> > Signed-off-by: Sean Christopherson
> > ---
> &
On Wed, Aug 5, 2020 at 5:18 PM Michael S. Tsirkin wrote:
>
> On Wed, Aug 05, 2020 at 10:05:40AM -0700, Jim Mattson wrote:
> > On Tue, Jul 28, 2020 at 7:38 AM Vitaly Kuznetsov
> > wrote:
> > >
> > > PCIe config space can (depending on the configuration) be qui
On Tue, Jul 28, 2020 at 7:38 AM Vitaly Kuznetsov wrote:
>
> PCIe config space can (depending on the configuration) be quite big but
> usually is sparsely populated. Guest may scan it by accessing individual
> device's page which, when device is missing, is supposed to have 'pci
> hole' semantics:
On Tue, Aug 4, 2020 at 11:41 AM Sean Christopherson
wrote:
> Ping. This really needs to be in the initial pull for 5.9, as is kvm/queue
> has a 100% fatality rate for me.
I agree completely, but I am curious what guest you have that toggles
CD/NW in 64-bit mode.
n bool rather than int?
> +{
> + if (!vcpu->kvm->arch.user_space_msr_enabled)
> + return 0;
> +
> + vcpu->run->exit_reason = KVM_EXIT_X86_WRMSR;
> + vcpu->run->msr.error = 0;
Same question about 'pad' as above.
> + vcpu->run->msr.index = index;
> + vcpu->run->msr.data = data;
> + vcpu->arch.pending_user_msr = true;
> + vcpu->arch.complete_userspace_io = complete_emulated_wrmsr;
> +
> + return 1;
> +}
> +
Reviewed-by: Jim Mattson
On Thu, Jul 30, 2020 at 4:53 PM Jim Mattson wrote:
>
> On Thu, Jul 30, 2020 at 4:08 PM Alexander Graf wrote:
> > Do you have a particular situation in mind where that would not be the
> > case and where we would still want to actually complete an MSR operation
> > after
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