On 9/25/2024 4:01 PM, Dmitry Baryshkov wrote:
> On Wed, Sep 25, 2024 at 03:21:37PM GMT, Jingyi Wang wrote:
>> Document the components used to boot the ADSP, CDSP and GPDSP on the
>> Qualcomm QCS8300 SoC. Use fallback to indicate the compatibility of the
>> remoteproc on the
Document the components used to boot the ADSP, CDSP and GPDSP on the
Qualcomm QCS8300 SoC. Use fallback to indicate the compatibility of the
remoteproc on the QCS8300 with that on the SA8775P.
Co-developed-by: Xin Liu
Signed-off-by: Xin Liu
Signed-off-by: Jingyi Wang
---
Changes in v3:
- add
On 9/16/2024 10:57 PM, Krzysztof Kozlowski wrote:
> On 11/09/2024 08:41, Jingyi Wang wrote:
>> + - items:
>> + - enum:
>> + - qcom,qcs8300-adsp-pas
>> + - const: qcom,sa8775p-adsp-pas
>> + - items:
>> + -
Document the components used to boot the ADSP, CDSP and GPDSP on the
Qualcomm QCS8300 SoC. Use fallback to indicate the compatibility of the
remoteproc on the QCS8300 with that on the SA8775P.
Co-developed-by: Xin Liu
Signed-off-by: Xin Liu
Signed-off-by: Jingyi Wang
---
Changes in v2
Hi Dmitry,
On 9/6/2024 11:18 AM, Dmitry Baryshkov wrote:
> On Thu, Sep 05, 2024 at 12:54:35PM GMT, Jingyi Wang wrote:
>>
>>
>> On 9/4/2024 5:39 PM, Krzysztof Kozlowski wrote:
>>> On 04/09/2024 10:33, Jingyi Wang wrote:
>>>> Enable clock control
On 9/5/2024 2:24 PM, Krzysztof Kozlowski wrote:
> On 05/09/2024 06:30, Jingyi Wang wrote:
>>>> diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
>>>> b/drivers/remoteproc/qcom_q6v5_pas.c
>>>> index ef82835e98a4..f92ccd4921b7 100644
>>>> --- a/dr
On 9/4/2024 5:41 PM, Krzysztof Kozlowski wrote:
> On 04/09/2024 10:33, Jingyi Wang wrote:
>> Add initial DTSI for QCS8300 SoC.
>>
>> This revision brings support for:
>> - CPUs with cpu idle
>> - interrupt-controller with PDC wakeup support
>> - gcc
&g
On 9/4/2024 5:39 PM, Krzysztof Kozlowski wrote:
> On 04/09/2024 10:33, Jingyi Wang wrote:
>> Enable clock controller, interrconnect and pinctrl for QCS8300.
>
> NXP QCS8300? What is QCS8300? Which products use it? That's a defconfig
> for entire kernel, not your Qualcom
On 9/4/2024 5:38 PM, Krzysztof Kozlowski wrote:
> On 04/09/2024 10:33, Jingyi Wang wrote:
>> Document the QCS8275/QCS8300 SoC and its reference board QCS8300 RIDE.
>> QCS8300 is an Industrial Safe SoC, while QCS8275 is the Industrial
>> Non-Safe version which can share
On 9/4/2024 5:36 PM, Krzysztof Kozlowski wrote:
> On 04/09/2024 10:33, Jingyi Wang wrote:
>> From: Xin Liu
>>
>> Add QMP PHY support for QCS8300 which is compatible with SA8775P.
>>
>> Signed-off-by: Xin Liu
>> Signed-off-by: Jingyi Wang
>> ---
&g
On 9/4/2024 5:36 PM, Krzysztof Kozlowski wrote:
> On 04/09/2024 10:33, Jingyi Wang wrote:
>> Add support for PIL loading on ADSP, CDSP and GPDSP on QCS8300
>> platform.
>>
>> Co-developed-by: Xin Liu
>> Signed-off-by: Xin Liu
>> Signed-off-by: Jin
Signed-off-by: Jingyi Wang
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 246 ++
2 files changed, 247 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile
b/arch/arm64/boot/dts/qcom/Makefile
index 197ab325c0b9
-by: Tingguo Cheng
[Raviteja: added interconnect nodes]
Co-developed-by: Raviteja Laggyshetty
Signed-off-by: Raviteja Laggyshetty
Signed-off-by: Jingyi Wang
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1282 +
1 file changed, 1282 insertions(+)
diff --git a/arch
Enable clock controller, interrconnect and pinctrl for QCS8300.
It needs to be built-in for UART to provide a console.
Signed-off-by: Jingyi Wang
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
Document the QCS8275/QCS8300 SoC and its reference board QCS8300 RIDE.
QCS8300 is an Industrial Safe SoC, while QCS8275 is the Industrial
Non-Safe version which can share the same SoC dtsi and board DTS.
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/arm/qcom.yaml | 8
From: Kyle Deng
Document the Always-On Subsystem side channel on the QCS8300 platform for
communication with client found on the SoC such as remoteprocs.
Signed-off-by: Kyle Deng
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 +
1 file
Document QFPROM compatible for QCS8300. It provides access functions for
QFPROM data to rest of the drivers via nvmem interface.
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
Document the qcom,qcs8300-tcsr compatible, tcsr will provide various
control and status functions for their peripherals.
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd
Document the Inter-Processor Communication Controller on the QCS8300
Platform, which will be used to route interrupts across various subsystems
found on the SoC.
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff
Document qcom,qcs8300-imem compatible. It has child node for debug
purpose.
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml
b/Documentation/devicetree
From: Zhenhua Huang
Document scm compatible for QCS8300 SoCs. It is an interface to
communicate to the secure firmware.
Signed-off-by: Zhenhua Huang
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a
From: Zhenhua Huang
QCS8300 SoC includes apps smmu that implements arm,mmu-500, which is used
to translate device-visible virtual addresses to physical addresses. Add
compatible for it.
Signed-off-by: Zhenhua Huang
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/iommu/arm
Document Power Domain Controller for QCS8300. PDC is included in QCS8300
SoC. This controller acts as an interrupt controller, enabling the
detection of interrupts when the GIC is non-operational.
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/interrupt-controller/qcom
From: Tingguo Cheng
Add support for the power-domains found on QCS8300 platform.
Co-developed-by: Shazad Hussain
Signed-off-by: Shazad Hussain
Signed-off-by: Tingguo Cheng
Signed-off-by: Jingyi Wang
---
drivers/pmdomain/qcom/rpmhpd.c | 24
1 file changed, 24
From: Shazad Hussain
Add compatible and constants for the power domains exposed by the RPMH
in the Qualcomm QCS8300 platform.
Signed-off-by: Shazad Hussain
Signed-off-by: Tingguo Cheng
Signed-off-by: Jingyi Wang
---
.../devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
include/dt
From: Xin Liu
Add QMP PHY support for QCS8300 which is compatible with SA8775P.
Signed-off-by: Xin Liu
Signed-off-by: Jingyi Wang
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
b/drivers/phy/qualcomm
From: Xin Liu
Document the Universal Flash Storage(UFS) Controller on the QCS8300
Platform.
Signed-off-by: Xin Liu
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs
From: Xin Liu
Document the QMP UFS PHY compatible for QCS8300 to support physical
layer functionality for USB found on the SoC.
Signed-off-by: Xin Liu
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++
1 file changed, 2 insertions
Add support for PIL loading on ADSP, CDSP and GPDSP on QCS8300
platform.
Co-developed-by: Xin Liu
Signed-off-by: Xin Liu
Signed-off-by: Jingyi Wang
---
drivers/remoteproc/qcom_q6v5_pas.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers
Document the components used to boot the ADSP, CDSP and GPDSP on the
QCS8300 SoC.
Co-developed-by: Xin Liu
Signed-off-by: Xin Liu
Signed-off-by: Jingyi Wang
---
Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a
-by: Jingyi Wang
---
patch series organized as:
- 1-2: remoteproc binding and driver
- 3-5: ufs binding and driver
- 6-7: rpmhpd binding and driver
- 8-15: bindings for other components found on the SoC
- 16-19: changes to support the device tree
dependencies:
tlmm:
https://lore.kernel.org/linux
On 8/28/2024 5:07 PM, Krzysztof Kozlowski wrote:
> On 28/08/2024 09:28, Jingyi Wang wrote:
>>
>>
>> On 8/28/2024 3:22 PM, Krzysztof Kozlowski wrote:
>>> On Wed, Aug 28, 2024 at 11:05:10AM +0800, Jingyi Wang wrote:
>>>> Document the components us
On 8/28/2024 3:22 PM, Krzysztof Kozlowski wrote:
> On Wed, Aug 28, 2024 at 11:05:10AM +0800, Jingyi Wang wrote:
>> Document the components used to boot the ADSP, CDSP and GPDSP on the
>> QCS8300 SoC.
>>
>> Co-developed-by: Xin Liu
>> Signed-off-by: Xin L
Add support for PIL loading on ADSP, CDSP and GPDSP on QCS8300
platform.
Co-developed-by: Xin Liu
Signed-off-by: Xin Liu
Signed-off-by: Jingyi Wang
---
drivers/remoteproc/qcom_q6v5_pas.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/drivers/remoteproc
Document the components used to boot the ADSP, CDSP and GPDSP on the
QCS8300 SoC.
Co-developed-by: Xin Liu
Signed-off-by: Xin Liu
Signed-off-by: Jingyi Wang
---
.../bindings/remoteproc/qcom,sa8775p-pas.yaml | 22 +++
1 file changed, 22 insertions(+)
diff --git a/Documentation
Add the bindings and driver changes for DSP support on the QCS8300
platform in order to enable the ADSP, CDSP and GPDSP remoteproc to
boot.
Signed-off-by: Jingyi Wang
---
Jingyi Wang (2):
dt-bindings: remoteproc: qcom,sa8775p-pas: Document QCS8300 remoteproc
remoteproc: qcom: pas: Add
On 3/29/2021 6:07 PM, Marc Zyngier wrote:
On Mon, 29 Mar 2021 09:52:10 +0100,
Jingyi Wang wrote:
Currently, arm use gic_ipi_send_mask() to inject single IPI, which
make the procedure a little complex. We use gic_ipi_send_single()
instead as some other archs.
Signed-off-by: Jingyi Wang
On 3/29/2021 5:55 PM, Marc Zyngier wrote:
On Mon, 29 Mar 2021 09:52:08 +0100,
Jingyi Wang wrote:
IRM, bit[40] in ICC_SGI1R, determines how the generated SGIs
are distributed to PEs. If the bit is set, interrupts are routed
to all PEs in the system excluding "self". We use
This series optimize arm IPI injection process by making use of
ICC_SGI1R IRM bit and implementing gic_ipi_send_single().
Jingyi Wang (3):
irqchip/gic-v3: Make use of ICC_SGI1R IRM bit
irqchip/gic-v3: Implement gic_ipi_send_single()
arm/arm64: Use gic_ipi_send_single() to inject single IPI
We implement gic_ipi_send_single() to make single ipi injection
easier.
Signed-off-by: Jingyi Wang
---
drivers/irqchip/irq-gic-v3.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 8ecc1b274ea8
t IPIs are sent.
Signed-off-by: Jingyi Wang
---
drivers/irqchip/irq-gic-v3.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index eb0ee356a629..8ecc1b274ea8 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/
Currently, arm use gic_ipi_send_mask() to inject single IPI, which
make the procedure a little complex. We use gic_ipi_send_single()
instead as some other archs.
Signed-off-by: Jingyi Wang
---
arch/arm/kernel/smp.c | 16 +---
arch/arm64/kernel/smp.c | 16 +---
2 files
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