Hi James,
On Tue, Oct 3, 2017 at 1:37 PM, James Morse wrote:
> Hi Jintack,
>
> On 03/10/17 04:11, Jintack Lim wrote:
>> This design overview will help to digest the subsequent patches that
>> implement AT instruction emulation.
>
>> diff --git a/arch/arm64/k
ff-by: Jintack Lim
---
arch/arm64/kvm/context.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c
index a7811e1..afd1702 100644
--- a/arch/arm64/kvm/context.c
+++ b/arch/arm64/kvm/context.c
@@ -18,6 +18,7 @@
#include
#include
#in
From: Christoffer Dall
Make mmu functions non-static so that we can reuse those functions
to support mmu for the nested VMs.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_mmu.h | 9
virt/kvm/arm/mmu.c | 94
-by: Jintack Lim
---
arch/arm/include/asm/kvm_asm.h| 7 +-
arch/arm/include/asm/kvm_host.h | 26 +---
arch/arm/kvm/hyp/switch.c | 5 +-
arch/arm/kvm/hyp/tlb.c| 18 ++---
arch/arm64/include/asm/kvm_asm.h | 7 +-
arch/arm64/include/asm/kvm_host.h | 10 ++-
arch
From: Christoffer Dall
Sometimes when we are invalidating the TLB for a certain S2 MMU
context, this context can also have EL2 context associated with it and
we have to invalidate this too.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
virt/kvm/arm/arm.c | 5 +
virt/kvm
pa is used for the former and ipa is used for the
latter.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
Notes:
v1-->v2:
- Added a common function to inject s2 faults.
- Align L1 IPA as well as L2 IPA in transparent_hugepage_adjust(). This will
come in handy when
From: Christoffer Dall
Move this little function to the header files for arm/arm64 so other
code can make use of it directly.
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_emulate.h | 8
arch/arm64/include/asm/kvm_emulate.h | 8
virt/kvm/arm/mmu.c
From: Christoffer Dall
Based on the pseudo-code in the ARM ARM, implement a stage 2 software
page table walker.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
Notes:
v1-->v2:
- Handled different endianness between the host and the guest hypervisor
- Decoupled
: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_mmu.h | 7 +++
arch/arm64/include/asm/kvm_mmu.h | 2 ++
arch/arm64/kvm/mmu-nested.c | 22 ++
virt/kvm/arm/mmu.c | 7 +++
4 files changed, 38 insertions(+)
diff --git a/arch/arm
shadow stage-2 table. This will be handled in a more
efficient way using the reverse mapping feature in a later version of
the patch series.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
Notes:
v1-->v2:
- Removed an unnecessary iteration for each vcpu
From: Jintack Lim
We are about to add a framework to handle system instruction traps. To
reuse existing helper functions, let's move them around.
No functional change.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 89 ---
1
This introduces a function prototype to determine if we need to forward
system instruction traps to the virtual EL2. The implementation of
forward_trap functions for each system instruction will be added in
later patches.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 8
Emulate AT S1E[01] instructions by issuing the same instructions in EL2. We
set the physical EL1 registers, NV and NV1 bits as described in the AT
instruction emulation overview.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_emulate.h | 11 +++
arch/arm64/kvm/sys_regs.c
s in the stage 2 page tables maintained by the guest
hypervisor. We then need to invalidate all EL1&0 regime stage 1 and 2
TLB entries of all VMIDs, which are assigned by the host hypervisor, for
this VM.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 29
registers and executing AT instructions. Note
that ctxt->hw_sys_regs is expected to have the proper processor context
before calling the handling function(__kvm_at_insn) implemented in this
patch.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_asm.h | 3 +
arch/arm64/kvm/hyp/Makef
Emulate TLBI VAE2* instruction executed in the virtual EL2. Based on the
same principle as TLBI ALLE2 instruction, we can simply emulate those
instructions by executing corresponding VAE1* instructions with the
virtual EL2's VMID assigned by the host hypervisor.
Signed-off-by: Jintac
tage 1 TLB entries via TLBI VMALL1IS instruction, but to
make it simeple, we reuse the existing function, __kvm_tlb_flush_vmid(),
which invalidates both of stage 1 and 2 TLB entries.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 35 +--
1 file changed
Based on the same principle as TLBI ALLE1(IS) and TLBI VMALLS12E1(IS)
emulation, we clear the mappings in the shadow stage-2 page tables and
invalidate TLB entries. We do it only for one mapping for the current
VMID from the guest hypervisor's view.
Signed-off-by: Jintack Lim
---
arch/arm6
Emulate AT S1E2 instructions by issuing the corresponding S1E1
instructions in EL2. We set the physical EL1 registers and the HCR_EL2
register as described in the AT instruction emulation overview.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 19 +--
1 file changed
ff-by: Jintack Lim
---
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/kvm/sys_regs.c| 99 ++--
2 files changed, 96 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 3993703..e160895 1
Forward system instruction traps to the virtual EL2 if a corresponding
bit in the virtual HCR_EL2 is set.
Signed-off-by: Jintack Lim
---
Notes:
v1-->v2:
This is a new commit. We can rework existing forward_nv_traps() and
forward_nv1_traps() defined in rfc-v2 cpu patches to re
Based on the same principle as TLBI ALLE1(IS) emulation, we clear the
mappings in the shadow stage-2 page tables and invalidate TLB entries.
But this time we do it only for the current VMID from the guest
hypervisor's perspective, not for all VMIDs.
Signed-off-by: Jintack Lim
---
arch/
This design overview will help to digest the subsequent patches that
implement AT instruction emulation.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 66 +++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch
r_el2, then execute the same instruction in EL2.
We don't set HCR_EL2.TTLB bit yet.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_asm.h | 1 +
arch/arm64/include/asm/kvm_mmu.h | 1 +
arch/arm64/include/asm/sysreg.h | 15
arch/arm64/kvm/hyp/tlb.c
List all system instructions to emulate. This patch only introduces the
definitions, emulation handlers will be added in subsequent patches.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/sysreg.h | 38 ++
arch/arm64/kvm/sys_regs.c | 26
Rework the system instruction emulation framework to handle potentially
all system instruction traps other than MSR/MRS instructions. Those
system instructions would be AT and TLBI instructions controlled by
HCR_EL2.NV, AT, and TTLB bits.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c
: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_mmu.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 601f431..7a1c581 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch
ges a set of shadow stage-2 page tables for each shadow
VMID. All this information is stored in kvm_nested_s2_mmu struct.
A host hypervisor manages a list of kvm_nested_s2_mmu objects per VM. On
a VM entry it searches an object in the list using a virtual VMID as a
key.
Signed-off-by: Jintac
more.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
Notes:
v1-->v2:
Fixed a bug that hw_vttbr was not initialized correctly in
kvm_arch_vcpu_init()
where vmid is not allocated yet. This prevented the guest from booting on
32bit
arm; hw_vttbr is set on each
From: Christoffer Dall
stage2_flush_xxx functions take a pointer to the kvm struct as the first
parameter but they are never used. Clean this up before modifying mmu
code for nested virtualization support.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
virt/kvm/arm/mmu.c | 15
_cache for nesting
Dave Martin (1):
arm64: KVM: Hide unsupported AArch64 CPU features from guests
Jintack Lim (18):
KVM: arm64: Expose limited memory management support to the virtual
EL2
KVM: arm/arm64: Manage mmus for nested VMs
KVM: arm64: Move system register helper functions a
.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 47 ++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 65f4c20..395b964 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch
From: Dave Martin
Currently, a guest kernel sees the true CPU feature registers
(ID_*_EL1) when it reads them using MRS instructions. This means
that the guest will observe features that are present in the
hardware but the host doesn't understand or doesn't provide support
for. A guest may legi
On Sun, Jul 30, 2017 at 4:00 PM, Christoffer Dall wrote:
> On Tue, Jul 18, 2017 at 11:58:46AM -0500, Jintack Lim wrote:
>> When HCR.NV bit is set, eret instructions trap to EL2 with EC code 0x1A.
>> Emulate eret instructions by setting pc and pstate.
>
> It may be worth
On Sun, Jul 30, 2017 at 3:59 PM, Christoffer Dall wrote:
> On Tue, Jul 18, 2017 at 11:58:34AM -0500, Jintack Lim wrote:
>> To support the virtual EL2 execution, we need to maintain the EL2
>> special registers such as SPSR_EL2, ELR_EL2 and SP_EL2 in vcpu context.
>>
>&
On Sun, Jul 30, 2017 at 3:59 PM, Christoffer Dall wrote:
> On Tue, Jul 18, 2017 at 11:58:30AM -0500, Jintack Lim wrote:
>> Nested virtualizaion is in use only if all three conditions are met:
>> - The architecture supports nested virtualization.
>> - The kernel param
On Sun, Jul 30, 2017 at 3:59 PM, Christoffer Dall wrote:
> On Tue, Jul 18, 2017 at 11:58:30AM -0500, Jintack Lim wrote:
>> Nested virtualizaion is in use only if all three conditions are met:
>> - The architecture supports nested virtualization.
>> - The kernel param
On Sun, Jul 30, 2017 at 3:59 PM, Christoffer Dall wrote:
> On Tue, Jul 18, 2017 at 11:58:28AM -0500, Jintack Lim wrote:
>> Add a new kernel parameter(kvm-arm.nested) to enable KVM/ARM nested
>> virtualization support. This kernel parameter on arm architecture is
>>
Hi Christoffer,
On Mon, Jul 31, 2017 at 8:59 AM, Christoffer Dall wrote:
> On Tue, Jul 18, 2017 at 11:59:04AM -0500, Jintack Lim wrote:
>> Forward CPACR_EL1 traps to the virtual EL2 if virtual CPTR_EL2 is
>> configured to trap CPACR_EL1 accesses from EL1.
>>
>> T
Hi Christoffer,
On Mon, Jul 31, 2017 at 9:00 AM, Christoffer Dall wrote:
> Hi Jintack,
>
> On Tue, Jul 18, 2017 at 11:58:26AM -0500, Jintack Lim wrote:
>> Nested virtualization is the ability to run a virtual machine inside another
>> virtual machine. In other words,
On Fri, Jul 28, 2017 at 4:13 PM, Bandan Das wrote:
> Jintack Lim writes:
> ...
>>>
>>> I'll share my experiment setup shortly.
>>
>> I summarized my experiment setup here.
>>
>> https://github.com/columbia/nesting-pub/wiki/Nested-virtualizatio
On Wed, Jul 19, 2017 at 4:49 AM, Christoffer Dall wrote:
> Hi Jintack,
>
> On Tue, Jul 18, 2017 at 10:23:05PM -0400, Jintack Lim wrote:
>> On Tue, Jul 18, 2017 at 12:58 PM, Jintack Lim wrote:
>> > Nested virtualization is the ability to run a virtual machine inside
&
On Tue, Jul 18, 2017 at 12:59 PM, Jintack Lim wrote:
> Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the
> virtual HCR_EL2.NV bit is set.
>
> This is for recursive nested virtualization.
>
> Signed-off-by: Jintack Lim
This should be linaro e-mail ad
On Tue, Jul 18, 2017 at 12:58 PM, Jintack Lim wrote:
> Nested virtualization is the ability to run a virtual machine inside another
> virtual machine. In other words, it’s about running a hypervisor (the guest
> hypervisor) on top of another hypervisor (the host hypervisor).
>
> Su
ster accesses in virtual EL2
Jintack Lim (31):
arm64: Add ARM64_HAS_NESTED_VIRT feature
KVM: arm/arm64: Enable nested virtualization via command-line
KVM: arm/arm64: Check if nested virtualization is in use
KVM: arm64: Add EL2 system registers to vcpu context
KVM: arm64: Add EL2 speci
completed. Just add this parameter first to
use it when implementing nested virtualization support.
Signed-off-by: Jintack Lim
---
Documentation/admin-guide/kernel-parameters.txt | 4
arch/arm/include/asm/kvm_host.h | 4
arch/arm64/include/asm/kvm_host.h
Add a new ARM64_HAS_NESTED_VIRT feature to indicate that the
CPU has the ARMv8.3 nested virtualization capability.
This will be used to support nested virtualization in KVM.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/sysreg.h | 1 +
arch
Nested virtualizaion is in use only if all three conditions are met:
- The architecture supports nested virtualization.
- The kernel parameter is set.
- The userspace uses nested virtualiztion feature.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_host.h | 11 +++
arch/arm64
patch doesn't set the NV bit yet. It will be set in a later patch
once nested virtualization support is completed.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.h | 30 +++-
arch/arm64/include/asm/sysreg.h | 37 +
arch/arm64/kvm/sys_r
From: Christoffer Dall
When running a nested hypervisor we occasionally have to figure out if
the mode we are switching into is the virtual EL2 mode or a regular
EL0/1 mode.
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_emulate.h | 6 ++
arch/arm64/include/asm/kvm_emulate
If the guest exception level is EL2, then set up the shadow context of
the virtual EL2 to hardware. Otherwise, set the regular EL0/EL1 context.
Note that the shadow context content will be prepared in subsequent
patches.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 74
d-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 4 ++
arch/arm64/include/asm/kvm_emulate.h | 4 ++
arch/arm64/kvm/Makefile | 2 +-
arch/arm64/kvm/context.c | 54
arch/arm64/kvm/hyp/sysreg-sr.c
With the nested virtualization support, a hypervisor running inside a VM
(i.e. a guest hypervisor) is now deprivilaged and runs in EL1 instead of
EL2. So, the host hypervisor manages the shadow context for the virtual
EL2 execution.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm
From: Christoffer Dall
Some bits of the TCR weren't defined and since we're about to use these
in KVM, add these defines.
Signed-off-by: Christoffer Dall
---
arch/arm64/include/asm/pgtable-hwdef.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h
a special care for MPIDR_EL1. Read of
this register returns the value of VMPIDR_EL2, so when a VM has the
virtual EL2, the value of MPIDR_EL1 should come from the virtual
VMPIDR_EL2.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 81
From: Christoffer Dall
When running in virtual EL2 mode, we actually run the hardware in EL1
and therefore have to use the EL1 registers to ensure correct operation.
By setting the HCR.TVM and HCR.TVRM we ensure that the virtual EL2 mode
doesn't shoot itself in the foot when setting up what it b
Support inject synchronous exceptions to the virtual EL2 as
described in ARM ARM AArch64.TakeException().
This can be easily extended to support to inject asynchronous exceptions
to the virtual EL2, but it will be added in a later patch when appropriate.
Signed-off-by: Jintack Lim
---
arch/arm
These macros and enums can be reused to inject exceptions
for nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_emulate.h | 12
arch/arm64/kvm/inject_fault.c| 12
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a
.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/sysreg.h | 2 ++
arch/arm64/kvm/sys_regs.c | 29 -
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 98c32ef..6373d3d 100644
n.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/handle_exit.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index d19e253..6cf6b93 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch
virtual _EL2 registers.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/esr.h | 1 +
arch/arm64/kvm/handle_exit.c | 16
arch/arm64/kvm/trace.h | 21 +
3 files changed, 38 insertions(+)
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include
EL2 and above are trapped to EL2. In these cases,
ESR_EL2.EC will be set to 0x18.
Change the existing handler to handle those system instructions as well
as MRS/MSR instructions. Emulation of each system instructions will be
done in separate patches.
Signed-off-by: Jintack Lim
---
arch/arm64
Now that the psci call is done by the smc instruction when nested
virtualization is enabled, it is clear that all hvc instruction from the
VM (including from the virtual EL2) are supposed to handled in the
virtual EL2.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/handle_exit.c | 6 ++
1
For the same reason we trap virtual memory register accesses in virtual
EL2, we trap CPACR_EL1 access too; We allow the virtual EL2 mode to
access EL1 system register state instead of the virtual EL2 one.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/hyp/switch.c | 10 +++---
arch/arm64/kvm
Forward exceptions due to WFI or WFE instructions to the virtual EL2 if
they are not coming from the virtual EL2 and virtual HCR_EL2.TWX is set.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/handle_exit.c | 13 -
arch/arm64/kvm/nested.c
These macros will be used to support the virtual EL2 with VHE.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_emulate.h | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_emulate.h
b/arch/arm64/include/asm/kvm_emulate.h
index
ARMv8.1 added more EL2 registers: TTBR1_EL2, CONTEXTIDR_EL2, and three
EL2 virtual timer registers. Add the first two registers to vcpu context
and set their handlers. The timer registers and their handlers will be
added in a separate patch.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm
to EL2.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 67 +++-
1 file changed, 66 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c
index 39bd92d..9947bc8 100644
--- a/arch/arm64/kvm/context.c
ccess virtual CPTR_EL2. The downside of using v8.0 format
is to convert the format when copying states between CPTR_EL2 and
CPACR_EL1 to support the virtual EL2 with VHE. The decision is subject
to change depending on the future discussion.
Signed-off-by: Jintack Lim
---
arch/arm64/includ
Now that the virtual EL2 can access EL2 register states via EL1
registers, we need to consider it when selecting the register to
emulate.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 46 --
1 file changed, 44 insertions(+), 2 deletions
trap since it's one of the EL12 registers controlled by HCR_EL2.NV
bit. Therefore, add a handler for it and don't treat it as a
non-trap-registers when preparing a shadow context.
Move EL12 system register macros to a common place to reuse them.
Signed-off-by: Jintack Lim
---
ar
Forward the EL1 virtual memory register traps to the virtual EL2 if they
are not coming from the virtual EL2 and the virtual HCR_EL2.TVM or TRVM
bit is set.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 24
1
-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 4fd7090..3559cf7 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -149,6 +149,9 @@ static
since those registers already have EL2 register states.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/hyp/switch.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index d513da9..fffd0c7 100644
Forward CPACR_EL1 traps to the virtual EL2 if virtual CPTR_EL2 is
configured to trap CPACR_EL1 accesses from EL1.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kvm
Forward traps due to HCR_EL2.NV bit to the virtual EL2 if they are not
coming from the virtual EL2 and the virtual HCR_EL2.NV bit is set.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_arm.h| 1 +
arch/arm64/include/asm/kvm_coproc.h
Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the
virtual HCR_EL2.NV bit is set.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/kvm/sys_regs.c| 18 ++
2 files changed
irtual EL2
without trapping to the host hypervisor. So, when returning from the VHE
host mode, set the vcpu mode depending on the physical exception level.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 36 ++--
1 file changed, 22 insertions(+), 14 deletion
Forward traps due to FP/ASIMD register accesses to the virtual EL2 if
virtual CPTR_EL2.TFP is set. Note that if TFP bit is set, then even
accesses to FP/ASIMD register from EL2 as well as NS EL0/1 will trap to
EL2. So, we don't check the VM's exception level.
Signed-off-by: Jintack Lim
From: Christoffer Dall
We were not allowing userspace to set a more privileged mode for the VCPU
than EL1, but now that we support nesting with a virtual EL2 mode, do
allow this!
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/guest.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/ar
locally in the shadow array, with no benefit to
software actually running in virtual EL1 at all.
To fix this, simply synchronize the shadow and real EL1 state for these
registers on entry/exit to/from virtual EL2 state.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm
To support the virtual EL2 execution, we need to maintain the EL2
special registers such as SPSR_EL2, ELR_EL2 and SP_EL2 in vcpu context.
Note that SP_EL2 is not accessible in EL2, so we don't need a trap
handler for this register.
Signed-off-by: Jintack Lim
---
arch/arm64/includ
From: Christoffer Dall
Set the initial exception level of the guest to EL2 if nested
virtualization feature is enabled.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/uapi/asm/kvm.h | 1 +
arch/arm64/kvm/reset.c
Thanks Christoffer and Marc,
On Mon, Jul 3, 2017 at 5:54 AM, Christoffer Dall wrote:
> On Mon, Jul 03, 2017 at 10:32:45AM +0100, Marc Zyngier wrote:
>> On 03/07/17 10:03, Christoffer Dall wrote:
>> > On Mon, Jun 26, 2017 at 10:33:23AM -0400, Jintack Lim wrote:
&g
On Mon, Jul 3, 2017 at 5:08 AM, Christoffer Dall wrote:
> On Mon, Jun 26, 2017 at 11:21:25AM -0400, Jintack Lim wrote:
>> On Wed, Feb 22, 2017 at 6:47 AM, Christoffer Dall wrote:
>> > On Mon, Jan 09, 2017 at 01:24:17AM -0500, Jintack Lim wrote:
>> >> Forward except
On Wed, Feb 22, 2017 at 6:47 AM, Christoffer Dall wrote:
> On Mon, Jan 09, 2017 at 01:24:17AM -0500, Jintack Lim wrote:
>> Forward exceptions due to hvc instruction to the guest hypervisor.
>>
>> Signed-off-by: Jintack Lim
>> ---
>> arch/arm64/include/asm/kvm_n
Hi Christoffer,
On Wed, Feb 22, 2017 at 6:10 AM, Christoffer Dall wrote:
> On Mon, Jan 09, 2017 at 01:24:02AM -0500, Jintack Lim wrote:
>> With the nested virtualization support, the context of the guest
>> includes EL2 register states. The host manages a set of virtual EL2
&g
Hi Bandan,
On Tue, Jun 6, 2017 at 4:16 PM, Bandan Das wrote:
> Jintack Lim writes:
>
>> From: Christoffer Dall
>>
>> When running in virtual EL2 we use the shadow EL1 systerm register array
>> for the save/restore process, so that hardware and especially the memor
On Tue, Jun 6, 2017 at 6:07 PM, Bandan Das wrote:
> Hi Jintack,
>
> Jintack Lim writes:
>
>> Hi Bandan,
>>
>> On Tue, Jun 6, 2017 at 4:21 PM, Bandan Das wrote:
>>> Jintack Lim writes:
>>>
>>>> Emulate taking an exception to the gues
Hi Bandan,
On Tue, Jun 6, 2017 at 4:21 PM, Bandan Das wrote:
> Jintack Lim writes:
>
>> Emulate taking an exception to the guest hypervisor running in the
>> virtual EL2 as described in ARM ARM AArch64.TakeException().
>
> ARM newbie here, I keep thinking of ARM ARM as
017 at 01:23:56AM -0500, Jintack Lim wrote:
>> Nested virtualization is the ability to run a virtual machine inside another
>> virtual machine. In other words, it’s about running a hypervisor (the guest
>> hypervisor) on top of another hypervisor (the host hypervisor).
>>
>
On Fri, Feb 3, 2017 at 11:14 AM, Marc Zyngier wrote:
> On 03/02/17 15:19, Jintack Lim wrote:
>> The ARM architecture defines the EL1 physical timer and the virtual timer,
>> and it is reasonable for an OS to expect to be able to access both.
>> However, the current KVM im
Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
Now VMs are able to use the EL1 physical timer.
Signed-off-by: Jintack Lim
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/sys_regs.c| 37 ++---
include/kvm/arm_arch_timer.h | 2
Now that we maintain the EL1 physical timer register states of VMs,
update the physical timer interrupt level along with the virtual one.
Signed-off-by: Jintack Lim
Acked-by: Christoffer Dall
---
virt/kvm/arm/arch_timer.c | 4
1 file changed, 4 insertions(+)
diff --git a/virt/kvm/arm
Now that we have a separate structure for timer context, make functions
generic so that they can work with any timer context, not just the
virtual timer context. This does not change the virtual timer
functionality.
Signed-off-by: Jintack Lim
Acked-by: Marc Zyngier
Acked-by: Christoffer Dall
make sense.
Signed-off-by: Jintack Lim
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_host.h | 3 ---
arch/arm/kvm/arm.c| 1 -
arch/arm64/include/asm/kvm_host.h | 3 ---
include/kvm/arm_arch_timer.h | 9 +++--
virt/kvm/arm/arch_timer.c | 38
Initialize the emulated EL1 physical timer with the default irq number.
Signed-off-by: Jintack Lim
Reviewed-by: Christoffer Dall
---
arch/arm/kvm/reset.c | 9 -
arch/arm64/kvm/reset.c | 9 -
include/kvm/arm_arch_timer.h | 3 ++-
virt/kvm/arm/arch_timer.c| 9
Abstract virtual timer context into a separate structure and change all
callers referring to timer registers, irq state and so on. No change in
functionality.
This is about to become very handy when adding the EL1 physical timer.
Signed-off-by: Jintack Lim
Acked-by: Christoffer Dall
Acked-by
When scheduling a background timer, consider both of the virtual and
physical timer and pick the earliest expiration time.
Signed-off-by: Jintack Lim
Reviewed-by: Christoffer Dall
---
arch/arm/kvm/arm.c| 3 ++-
virt/kvm/arm/arch_timer.c | 53
KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle
those traps. This results in terminating VMs. Instead, set a handler for
the EL1 phys timer access, and inject an undefined exception as an
intermediate step.
Signed-off-by: Jintack Lim
Reviewed-by: Christoffer
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