Re: [PATCH] implement flush_cache_vmap for RISC-V

On Wednesday, April 14, 2021 7:03:13 AM UTC you wrote: > Hi, > > Le 4/12/21 à 3:08 AM, Jisheng Zhang a écrit : > > Hi Jiuyang, > > > > On Mon, 12 Apr 2021 00:05:30 + Jiuyang Liu wrote: > >> This patch implements flush_cache_vmap for RISC-V, since it m

Re: [PATCH] implement flush_cache_vmap and flush_cache_vunmap for RISC-V

VMA won't be added to related codes, which might introduce a bug > > in some out-of-order micro-architecture implementations. > > > > Signed-off-by: Jiuyang Liu > > --- > > > > arch/riscv/include/asm/cacheflush.h | 8 > > 1 file changed, 8 ins

[PATCH] implement flush_cache_vmap for RISC-V

This patch implements flush_cache_vmap for RISC-V, since it modifies PTE. Without this patch, SFENCE.VMA won't be added to related codes, which might introduce a bug in the out-of-order micro-architecture implementations. Signed-off-by: Jiuyang Liu Reviewed-by: Alexandre Ghiti Review

[PATCH] implement flush_cache_vmap and flush_cache_vunmap for RISC-V

This patch implements flush_cache_vmap and flush_cache_vunmap for RISC-V, since these functions might modify PTE. Without this patch, SFENCE.VMA won't be added to related codes, which might introduce a bug in some out-of-order micro-architecture implementations. Signed-off-by: Jiuyan

Re: [PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV

fix for my stack by adding flush in the flush_cache_vmap. Does this approach sound reasonable? Regards, Jiuyang On Tue, 16 Mar 2021 at 09:17 PM Palmer Dabbelt wrote: > We're trying to avoid this sort of thing, instead relying on the generic > kernel > functionality to batch

Re: [PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV

In general, this patch didn't handle the G bit in PTE, kernel trap it to sbi_remote_sfence_vma. do you think I should use flush_tlb_all? Jiuyang arch/arm/mm/mmu.c void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval) {

[PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV

program asid. 2. implement local_flush_tlb_asid to flush tlb with asid. Signed-off-by: Jiuyang Liu --- arch/riscv/include/asm/pgtable.h | 27 +++ arch/riscv/include/asm/tlbflush.h | 12 2 files changed, 39 insertions(+) diff --git a/arch/riscv/include/asm

[PATCH 2/2] Bug Fix for last patch

Sorry for the noise, Andrew gave me feedbacks, and pointed two bugs in last patch. 1. asid should be thread safe, which is not the intent. 2. asid extracting logic was wrong. This patch fixes these bugs. Signed-off-by: Jiuyang Liu --- arch/riscv/include/asm/tlbflush.h | 8 ++-- 1 file

[PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV

From: Jiuyang Liu This patch inserts SFENCE.VMA after modifying PTE based on RISC-V specification. arch/riscv/include/asm/pgtable.h: 1. implement pte_user, pte_global and pte_leaf to check correspond attribute of a pte_t. 2. insert SFENCE.VMA in set_pte_at based on RISC-V Volume 2, Privileged