Allow a io-pgtable implementation to skip TLB operations by checking for
NULL pointers in the helper functions. It will be up to to the owner
of the io-pgtable instance to make sure that they independently handle
the TLB correctly.
Signed-off-by: Jordan Crouse
---
include/linux/io-pgtable.h
Add a special implementation for the SMMU attached to most Adreno GPU
target triggered from the qcom,adreno-gpu-smmu compatible string. When
selected the driver will attempt to enable split pagetables.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 3 +++
drivers/iommu/arm
Construct the io-pgtable config before calling the implementation specific
init_context function and pass it so the implementation specific function
can get a chance to change it before the io-pgtable is created.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 3 ++-
drivers
.
Reviewed-by: Rob Herring
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index d7ceb4c34423
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm
Add a link to the pointer to the struct device that is attached to a
domain. This makes it easy to get the pointer if it is needed in the
implementation specific code.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 6 --
drivers/iommu/arm-smmu.h | 1 +
2 files changed, 5
/
Jordan Crouse (7):
iommu/arm-smmu: Pass io-pgtable config to implementation specific
function
iommu/arm-smmu: Add support for split pagetables
dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU
iommu/arm-smmu: Add a pointer to the attached device to smmu_domain
iommu/arm-smmu
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom
Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
by the io-pgtable configuration.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 21 -
drivers/iommu/arm-smmu.h | 25 +++--
2 files changed, 35 insertions(+), 11
On Mon, Jun 08, 2020 at 04:13:08PM +0100, Will Deacon wrote:
> On Thu, Jun 04, 2020 at 02:39:04PM -0600, Jordan Crouse wrote:
> > When CONFIG_OF=n of_match_device() gets pre-processed out of existence
> > leaving qcom-smmu_client_of_match unused. Mark it as possibly unused to
> &
space initialization")
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c| 2 +-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
On Wed, Jun 17, 2020 at 07:39:08PM -0700, Rob Clark wrote:
> On Wed, Jun 17, 2020 at 1:53 PM Eric Anholt wrote:
> >
> > Previously the address space went from 16M to ~0u, but with the
> > refactor one of the 'f's was dropped, limiting us to 256MB.
> > Additionally, the new interface takes a start
On Thu, Jun 11, 2020 at 08:22:29PM -0700, Rob Clark wrote:
> On Thu, Jun 11, 2020 at 3:29 PM Jordan Crouse wrote:
> >
> > Add support for using per-instance pagetables if all the dependencies are
> > available.
> >
> > Signed-off-by: Jordan Crouse
> >
could hang the GPU if one of the terminated
transactions is a CP read.
This depends on the arm-smmu adreno SMMU implementation [1].
[1] https://patchwork.kernel.org/patch/11600943/
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-qcom.c | 13 +
drivers/iommu/arm-smmu.c
://patchwork.kernel.org/patch/11600949/
Jordan Crouse (6):
iommu/arm-smmu: Add auxiliary domain support for arm-smmuv2
iommu/io-pgtable: Allow a pgtable implementation to skip TLB
operations
iommu/arm-smmu: Add a domain attribute to pass the pagetable config
drm/msm: Add support to create a local
-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_gpummu.c | 2 +-
drivers/gpu/drm/msm/msm_iommu.c | 180 ++-
drivers/gpu/drm/msm/msm_mmu.h| 16 ++-
3 files changed, 195 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm
The Adreno GPU has the capacity to manage its own pagetables and switch
them dynamically from the hardware. Add a domain attribute for arm-smmu-v2
to get the default pagetable configuration so that the GPU driver can match
the format for its own pagetables.
Signed-off-by: Jordan Crouse
addresses in the pagetable.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 216 ---
drivers/iommu/arm-smmu.h | 1 +
2 files changed, 201 insertions(+), 16 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 743d75b9ff3f
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 69 ++-
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
2 files changed, 69 insertions(+), 1 deletion(-)
diff
Add support for allocating an address space instance. Targets that support
per-instance pagetables should implement their own function to allocate a
new instance. The default will return the existing generic address space.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 15
Allow a io-pgtable implementation to skip TLB operations by checking for
NULL pointers in the helper functions. It will be up to to the owner
of the io-pgtable instance to make sure that they independently handle
the TLB correctly.
Signed-off-by: Jordan Crouse
---
include/linux/io-pgtable.h
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm
Construct the io-pgtable config before calling the implementation specific
init_context function and pass it so the implementation specific function
can get a chance to change it before the io-pgtable is created.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 3 ++-
drivers
the hardware would be less confusing when debugging a hang.
v8: Pass the attached device in the smmu_domain to the implementation
specific functions
[1] https://lists.linuxfoundation.org/pipermail/iommu/2020-May/044537.html
[2] https://patchwork.kernel.org/patch/11482591/
Jordan Crouse (7):
iommu/arm
Add a link to the pointer to the struct device that is attached to a
domain. This makes it easy to get the pointer if it is needed in the
implementation specific code.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 1 +
drivers/iommu/arm-smmu.h | 1 +
2 files changed, 2 insertions
.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index d7ceb4c34423..e52a1b146c97 100644
Add a special implementation for the SMMU attached to most Adreno GPU
target triggered from the qcom,adreno-gpu-smmu compatible string. When
selected the driver will attempt to enable split pagetables.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 3 +++
drivers/iommu/arm
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom
Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
by the io-pgtable configuration.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 21 -
drivers/iommu/arm-smmu.h | 25 +++--
2 files changed, 35 insertions(+), 11
bootloader") [1] that identifies streams that are already configured
and marked them as pinned. This patch extends that to not re-write pinned
stream mappings for ARM_SMMU_DOMAIN_BYPASS domains.
[1]
https://lore.kernel.org/r/20191226221709.3844244-4-bjorn.anders...@linaro.org
Signed-o
On Thu, Jun 04, 2020 at 03:38:28PM -0700, Rob Clark wrote:
> On Thu, Jun 4, 2020 at 3:02 PM Jordan Crouse wrote:
> >
> > On Thu, Jun 04, 2020 at 02:27:21PM -0700, Rob Clark wrote:
> > > On Thu, Jun 4, 2020 at 1:57 PM Jordan Crouse
> > > wrote:
> > > >
On Thu, Jun 04, 2020 at 02:27:21PM -0700, Rob Clark wrote:
> On Thu, Jun 4, 2020 at 1:57 PM Jordan Crouse wrote:
> >
> > Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
> > split pagetables.
> >
> > Signed-off-by: Jordan Crouse
> >
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm
Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
by the io-pgtable configuration.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 21 -
drivers/iommu/arm-smmu.h | 25 +++--
2 files changed, 35 insertions(+), 11
would be less confusing when debugging a hang.
[1] https://lists.linuxfoundation.org/pipermail/iommu/2020-May/044537.html
[2] https://patchwork.kernel.org/patch/11482591/
Jordan Crouse (6):
iommu/arm-smmu: Pass io-pgtable config to implementation specific
function
iommu/arm-smmu: Add
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom
Add a special implementation for the SMMU attached to most Adreno GPU
target triggered from the qcom,adreno-gpu-smmu compatible string. When
selected the driver will attempt to enable split pagetables.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 5 -
drivers/iommu/arm
Construct the io-pgtable config before calling the implementation specific
init_context function and pass it so the implementation specific function
can get a chance to change it before the io-pgtable is created.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 3 ++-
drivers
.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index d7ceb4c34423..e52a1b146c97 100644
by: kbuild test robot
Acked-by: Will Deacon
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-qcom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c
index cf01d0215a39..be4318044f96 100644
--- a/drivers/iomm
by: kbuild test robot
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-qcom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c
index cf01d0215a39..063b4388b0ff 100644
--- a/drivers/iommu/arm-smmu-qcom.c
+++
On Wed, May 27, 2020 at 08:38:47AM -0700, Rob Clark wrote:
> On Wed, May 27, 2020 at 1:47 AM Sharat Masetty
> wrote:
> >
> > + more folks
> >
> > On 5/18/2020 9:55 PM, Rob Clark wrote:
> > > On Mon, May 18, 2020 at 7:23 AM Jordan Crouse
> > >
sp_ncmode = FIELD_PREP(REG_A6XX_TPL1_NC_MODE_HBB, 3);
sp_ncmode |= FIELD_PREP(REG_A6XX_TPL1_NC_MODE_UAVFLAGPRD_INV, 2);
uchemode = FIELD_PREP(REG_A6XX_UCHE_MODE_CNTL_HBB, 2);
}
I'm not sure if that is any clearer or not. Perhaps this is a problem for the
next person to add a new target. Rega
a -fix if it didn't.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gp
On Mon, May 18, 2020 at 11:07:33PM -0400, Jonathan Marek wrote:
> This fixes changing the frequency in sysfs while suspended, for example
> when doing something like this:
>
> cat devfreq/3d0.gpu/max_freq > devfreq/3d0.gpu/min_freq
A patch landed to fix this [1] but it crossed paths in
://patchwork.kernel.org/patch/11355255/
[2] https://patchwork.kernel.org/patch/11355259/
Jordan Crouse (3):
drm/msm: Attach the IOMMU device during initialization
drm/msm: Refactor address space initialization
drm/msm: Update the MMU helper function APIs
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
aggressive cleanups that follow.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu
Instead of using a bare unsigned type for the length value for map/unmap
functions pass in a size_t to more correctly match up with the underlying
APIs.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_gpummu.c | 4 ++--
drivers/gpu/drm/msm/msm_iommu.c | 4 ++--
drivers/gpu/drm/msm
On Wed, May 20, 2020 at 01:57:01PM +0100, Will Deacon wrote:
> On Mon, May 18, 2020 at 08:50:27AM -0700, Rob Clark wrote:
> > On Mon, May 18, 2020 at 8:18 AM Will Deacon wrote:
> > > On Wed, Mar 18, 2020 at 04:43:07PM -0700, Rob Clark wrote:
> > > > We do in fact need live domain switching, that
On Mon, May 18, 2020 at 03:59:59PM +0100, Will Deacon wrote:
> On Thu, Apr 09, 2020 at 05:33:47PM -0600, Jordan Crouse wrote:
> > Add support to enable TTBR1 if the domain requests it via the
> > DOMAIN_ATTR_SPLIT_TABLES attribute. If enabled by the hardware
> > and pa
On Thu, Apr 23, 2020 at 05:09:21PM -0400, Jonathan Marek wrote:
> Adreno 640 and 650 GPUs need some registers set differently.
As before, make sure you send the XML updates up so the database stays current.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> dri
t; RSCC_TCS2_DRV0_STATUS
> RSCC_TCS3_DRV0_STATUS
>
> Based on the values in msm-4.14 and msm-4.19 kernels.
>
> v3: replaced adreno_is_a650 around ->rscc with checks for "rscc" resource
This is one of the most frustrating bits about the different GMU flavors. There
is simply no
don't forget to do that
so we don't accidentally lose the registers if we do a refresh.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 138 +++---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 10 +
On Thu, Apr 23, 2020 at 05:09:13PM -0400, Jonathan Marek wrote:
> This function allows pinning iova to a specific page range (for a6xx GMU).
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/msm_drv.h | 6 +-
> drivers/gpu/dr
On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
> This patches replaces the previously used static DDR vote and uses
> dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
> GPU frequency.
>
> Signed-off-by: Sharat Masetty
> ---
>
On Fri, May 08, 2020 at 08:40:40AM -0700, Rob Clark wrote:
> On Fri, May 8, 2020 at 8:32 AM Rob Clark wrote:
> >
> > On Thu, May 7, 2020 at 5:54 AM Will Deacon wrote:
> > >
> > > On Thu, May 07, 2020 at 11:55:54AM +0100, Robin Murphy wrote:
> > > > On 2020-05-07 11:14 am, Sai Prakash Ranjan
wed-by: Eric Anholt
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 ++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/
GPU driver.
Call pm_runtime_get_if_in_use() in the gpu_busy() and gpu_set_freq()
callbacks to skip the hardware access if it isn't active.
v2: Use pm_runtime_get_if_in_use() per Eric Anholt
Cc: sta...@vger.kernel.org
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
GPU driver.
Check the power state in the gpu_busy() and gpu_set_freq() callbacks for
a5xx and a6xx to make sure that the hardware is active before trying to
access it.
Cc: sta...@vger.kernel.org
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4
drivers/gpu/drm/
On Thu, Apr 30, 2020 at 09:29:47AM +0530, Sharat Masetty wrote:
> This patch adds a new compatible string for sc7180 and also an
> additional clock listing needed to power the TBUs and the TCU.
>
> Signed-off-by: Sharat Masetty
> ---
> v2: Addressed review comments from Doug
>
>
receives a list of bogus pointers instead.
>
> Zero-initialize the "id" field and attempt to populate with strings from
> the clock-names property to resolve both these issues.
This looks great to me. Thanks for fixing that so quickly.
Reviewed-by: Jordan Crouse
> Fix
On Wed, Aug 14, 2019 at 05:00:49PM +0530, Sibi Sankar wrote:
> On 2019-08-14 06:13, Saravana Kannan wrote:
> >On Thu, Aug 8, 2019 at 10:37 AM Sibi Sankar wrote:
> >>
> >>Hey Saravana,
> >>
> >>Thanks for the review!
> >>
> >>On 8/8/19 2:51 AM, Saravana Kannan wrote:
> >>> On Wed, Aug 7, 2019 at
Remove the default for CONFIG_DRM_MSM and let the user select the driver
manually as one does.
Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure
it doesn't get missed when we need it for a6xx targets.
v2: Move from default 'm' to no default
Signed-off-by: Jordan Crouse
Now that CONFIG_DRM_MSM is no longer default 'y' add it as a module to all
ARCH_QCOM enabled defconfigs to restore the previous expected build
behavior.
Signed-off-by: Jordan Crouse
---
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/configs/qcom_defconfig | 1 +
arch/arm64/configs
On Sun, Jun 30, 2019 at 06:14:41AM -0700, Rob Clark wrote:
> From: Rob Clark
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_gp
zable gap in coverage since there
seem to be more of these guys in the world than 8996.
Reviewed-by: Jordan Crouse
> ---
>
> v3:
> -Adjusted MERCIU for A540 for best performance.
>
> drivers/gpu/drm/msm/adreno/a5xx.xml.h | 28
> drivers/gpu/drm/m
On Fri, May 31, 2019 at 07:12:28PM -0700, Saravana Kannan wrote:
> I'll have to Nack this series because it's making a couple of wrong
> assumptions
> about bandwidth voting.
>
> Firstly, it's mixing up OPP to bandwidth mapping (Eg: CPU freq to CPU<->DDR
> bandwidth mapping) with the bandwidth
On Tue, May 21, 2019 at 07:18:32PM +0100, Robin Murphy wrote:
> On 21/05/2019 17:13, Jordan Crouse wrote:
> >Add support for a split pagetable (TTBR0/TTBR1) scheme for arm-smmu-v2.
> >If split pagetables are enabled, create a pagetable for TTBR1 and set
> >up the sign exte
On Tue, May 14, 2019 at 09:09:55PM -0700, Rob Clark wrote:
> On Mon, May 13, 2019 at 3:48 PM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Thu, May 9, 2019 at 11:44 AM Rob Clark wrote:
> >
> > > From: Douglas Anderson
> > >
> > > Let's fixup the reserved memory to re-add the things we deleted in
I somewhat accidently injected an error in the DPU KMS init that caused it to
fail and a handful of NULL deferences and errors ended up popping out. Here are
some fixes in the interest of robustness.
Jordan Crouse (3):
drm/msm/dpu: Fix error recovery after failing to enable clocks
drm/msm/dpu
, in the case of the GMU).
Instead of calling the pm_suspend function directly, use
pm_runtime_force_suspend() which should check the correct state of
runtime and call the functions on our behalf or skip them if they are
not needed.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno
In the failure path for dpu_kms_init() it is possible to get to the MMU
destroy function with uninitialized MMU structs. Check for NULl and skip
if needed.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions
to prepare/enable. Skip the current failed clock during
the unwind to to avoid the extra log spew.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
b/drivers
An error while initializing the msm driver ends up calling
drm_atomic_helper_shutdown() without first initializing the funcs
in mode_config. While I'm not 100% sure this isn't a ordering
problem in msm adding a check to drm_mode_alloc seems like
a nice and safe solution.
Signed-off-by: Jordan
These are a few support changes in advance of per-instance pagetables. These
can be added to msm-next immediately since they don't require anything external
support and they are mostly benign on their own without the more aggressive
changes coming up later.
Jordan Crouse (3):
drm/msm/adreno
When we move to 64 bit addressing for a5xx and a6xx targets we will start
seeing pagefaults at larger addresses so format them appropriately in the
log message for easier debugging.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1
Describe the zap-shader node that defines a reserved memory region
to store the zap shader.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt
b
a5xx and a6xx both share (mostly) the same code to load the zap shader and
bring the GPU out of secure mode. Move the formerly 5xx specific code to
adreno to make it available for a6xx too.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 111
On Thu, Apr 04, 2019 at 10:02:07AM +0800, YueHaibing wrote:
> On 2019/4/3 23:36, Jordan Crouse wrote:
> > On Wed, Apr 03, 2019 at 02:48:11PM +0800, Yue Haibing wrote:
> >> From: YueHaibing
> >>
> >> When building CONFIG_DEBUG_FS is not set
> >> gcc wa
Describe the zap-shader node that defines a reserved memory region
to store the zap shader.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt
b
Targets that support per-instance pagetable switching will have to keep
track of which pagetable belongs to each instance to be able to recover
for preemption.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 120 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 19 +
drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 70 +
3 files changed, 192 insertions(+), 17 deletions(-)
diff
Add support to create a GPU target specific address space for
a context. For those targets that support per-instance
pagetables they will return a new address space set up for
the instance if possible otherwise just use the global
device pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu
Add support for per-instance pagetables for a6xx targets. Add support
to handle split pagetables and create a new instance if the needed
IOMMU support exists and insert the necessary PM4 commands to trigger
a pagetable switch at the beginning of a user command.
Signed-off-by: Jordan Crouse
in some of the target files but I think
it pays for itself in improved code flow and flexibility.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 37 --
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 50 ++
drivers/gpu/drm/msm
generating 32 bit addresses so switch over now to prepare
for using addresses above 4G for targets that support them.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++
2 files changed, 28 insertions
Add an attribute to return the base address of the pagetable. This is used
by auxiliary domains from arm-smmu to return the address of the pagetable
to the leaf driver so that it can set the appropriate pagetable through
it's own means.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h
, I want to make sure that this fits with the
current thinking about how aux domains should look and feel.
[1] https://patchwork.freedesktop.org/series/43447/
[2] https://patchwork.kernel.org/patch/10825061/
Jordan Crouse (15):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Add split
Add a helper function to create a GEM address space attached to
an iommu auxiliary domain for a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.h | 4 +++
drivers/gpu/drm/msm/msm_gem_vma.c | 53 +++
2 files changed
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
iova addresses in the pagetable. The driver/hardware can be used
to switch the pagetable according to its own specific implementation.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 135 ++-
1 file changed, 111 insertions(+), 24 deletions
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path. This clears the way
to change ctx->aspace to a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
drivers/gpu/d
When we move to 64 bit addressing for a5xx and a6xx targets we will start
seeing pagefaults at larger addresses so format them appropriately in the
log message for easier debugging.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1
Add support for a split pagetable (TTBR0/TTBR1) scheme for
arm-smmu-v2. If split pagetables are enabled, create a
pagetable for TTBR1 and set up the sign extension bit so
that all IOVAs with that bit set are mapped and translated
from the TTBR1 pagetable.
Signed-off-by: Jordan Crouse
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index e90da6b..3f2250b 100644
--- a/include
configuration to be NULL just in case the caller
accidentally calls for a flush with the wrong device.
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable.h | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
The allocation for the clock bulk data does a classic sizeof(pointer)
instead of sizeof(struct) so the array ends up incorrectly sized
for the clock data.
Cc: sta...@vger.kernel.org
Fixes: 8e54eea ("drm/msm: Add a helper function to parse clock names")
Signed-off-by: Jordan Crouse
---
and egg problem.
Luckily this is easily fixed by removing the pm_runtime calls from the
functions and letting the device link to the IOMMU device handle the magic.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 13 +
1 file changed, 1 insertion(+), 12 deletions
and fixed by Dan Carpenter.
[1] https://patchwork.freedesktop.org/series/56656/
Fixes: f05c83e77460 ("drm/msm: add uapi to get/set debug name")
Reported-by: Dan Carpenter
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 5 -
1 file changed, 4 insertions(+),
201 - 300 of 511 matches
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