This change makes sure that Broadcom NAND driver moves to interrupt
polling on the first brcmnand_write() call.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd
Added support to read/write oob during EDU transfers.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 59 +---
1 file changed, 52 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand
rs/mtd/nand/raw/brcmnand/brcmnand.c:1951: warning: Function parameter
> or member 'end' not described in 'brcmnand_fill_dma_desc'
> drivers/mtd/nand/raw/brcmnand/brcmnand.c:1951: warning: Function parameter
> or member 'next_desc' not described in
Looks good to me.
Signed-off-by: Kamal Dasu
On Thu, Aug 27, 2020 at 3:30 PM Scott Branden
wrote:
>
> Patch series looks good.
>
> Acked-by: Scott Branden
>
> On 2020-08-27 11:18 a.m., Florian Fainelli wrote:
> > Hi all,
> >
> > This patch series fixes in
Mark,
This block is used on multiple Broadcom SoCs and would like to get
comments from all who deal with iProc and have touched this file as
well.
Please copy :
Florian Fainelli
Rayagonda Kokatanur
and
bcm-kernel-feedback-l...@broadcom.com (maintainer:BROADCOM SPI DRIVER)
Kamal
On Mon, Jun 15,
Check and set master panic write flag so that low level drivers
can use it to take required action to ensure oops data gets written
to assigned mtdoops device partition.
Fixes: 9f897bfdd89f ("mtd: Add flag to indicate panic_write")
Signed-off-by: Kamal Dasu
---
drivers/mtd/mtdcore.c |
On Mon, Jun 15, 2020 at 3:19 AM Miquel Raynal wrote:
>
> Hi Kamal,
>
> Kamal Dasu wrote on Fri, 12 Jun 2020 12:34:22
> -0400:
>
> > On Fri, Jun 12, 2020 at 3:07 AM Miquel Raynal
> > wrote:
> > >
> > > Hi Kamal,
> > >
> &g
Alvaro,
On Sat, Jun 13, 2020 at 5:01 AM Álvaro Fernández Rojas
wrote:
>
> Hi Kamal,
>
> > El 12 jun 2020, a las 20:47, Kamal Dasu escribió:
> >
> > On Fri, Jun 5, 2020 at 1:07 PM Álvaro Fernández Rojas
> > wrote:
> >>
> >> MTD_OPS_AUTO_OOB
Can you please accept this if there are no objections.
Kamal
> On May 4, 2020, at 7:54 PM, Kamal Dasu wrote:
>
> Check and set master panic write flag so that low level drivers
> can use it to take required action to ensure oops data gets written
> to assigned mtdoops d
mnand: Add support for flash-edu for dma
transfers")
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 26
1 file changed, 26 insertions(+)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 0c
edu_err in brcmnand_read()
Kamal Dasu (2):
mtd: rawnand: brcmnand: Don't default to edu transfer
mtd: rawnand: brcmnand: ECC error handling on EDU transfers
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 31 ++--
1 file changed, 29 insertions(+), 2 deletions(-)
--
2.17.1
When flash-dma is absent do not default to using flash-edu.
Make sure flash-edu is enabled before setting EDU transfer
function.
Fixes: a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma
transfers")
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/
On Fri, Jun 5, 2020 at 1:07 PM Álvaro Fernández Rojas wrote:
>
> MTD_OPS_AUTO_OOB is writting OOB with ECC enabled, which changes all ECC bytes
> from an erased page to 0x00 when JFFS2 cleanmarkers are added with mtd-utils.
> | BBI | JFFS2 | ECC | JFFS2 | Spare |
> 0800
On Fri, Jun 12, 2020 at 3:07 AM Miquel Raynal wrote:
>
> Hi Kamal,
>
> Kamal Dasu wrote on Thu, 11 Jun 2020 12:04:29
> -0400:
>
> > On Thu, Jun 11, 2020 at 3:27 AM Miquel Raynal
> > wrote:
> > >
> > > Hi Kamal,
> > >
> &g
On Thu, Jun 11, 2020 at 3:27 AM Miquel Raynal wrote:
>
> Hi Kamal,
>
> Kamal Dasu wrote on Thu, 11 Jun 2020 01:44:54
> -0400:
>
> > Implemented ECC correctable and uncorrectable error handling for EDU
>
> Implement?
>
> > reads. If ECC correctable bi
On Thu, Jun 11, 2020 at 3:16 AM Miquel Raynal wrote:
>
> Hi Kamal,
>
> Kamal Dasu wrote on Thu, 11 Jun 2020 01:44:53
> -0400:
>
> > When flash-dma is absent do not default to using flash-edu.
> > Make sure flash-edu is enabled before setting EDU transfer
> > f
holds true for ECC correctable errors beyond set threshold.
Fixes: a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma
transfers")
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 26
1 file changed, 26 insertion
When flash-dma is absent do not default to using flash-edu.
Make sure flash-edu is enabled before setting EDU transfer
function.
Fixes: a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma
transfers")
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/
Check and set master panic write flag so that low level drivers
can use it to take required action to ensure oops data gets written
to assigned mtdoops device partition.
Signed-off-by: Kamal Dasu
---
drivers/mtd/mtdcore.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
On Sat, May 2, 2020 at 2:08 PM Miquel Raynal wrote:
>
> Hi Kamal,
>
> Miquel Raynal wrote on Thu, 9 Jan 2020
> 18:28:07 +0100:
>
> > Hi Kamal,
> >
> > Kamal Dasu wrote on Thu, 9 Jan 2020 10:25:59
> > -0500:
> >
> > > Miquel,
> >
This change fixes crash observed on PM resume. This bug
was introduced in the change made for flash-edu support.
Fixes: a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma
transfers")
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 3 +
Check mtd panic write flag and set the mtd partition panic
write flag so that low level drivers can use it to take
required action to ensure oops data gets written to assigned
mtd partition.
Fixes: 9f897bfdd8 ("mtd: Add flag to indicate panic_write")
Signed-off-by: Kamal Dasu
---
d
, 2019 at 3:39 PM Richard Weinberger wrote:
>
> - Ursprüngliche Mail -
> > Von: "Kamal Dasu"
> > This has been observed on MIPS4K and MIPS5K architectures. There is a
> > check on the controller driver to use pio in such cases.
>
> I fear your ker
On Mon, Sep 30, 2019 at 12:25 PM Boris Brezillon
wrote:
>
> On Mon, 30 Sep 2019 12:01:28 -0400
> Kamal Dasu wrote:
>
> > Does anyone have any comments on this patch ?.
> >
> > Kamal
> >
> > On Fri, Sep 6, 2019 at 3:49 PM Kamal Dasu wrote:
> > >
Does anyone have any comments on this patch ?.
Kamal
On Fri, Sep 6, 2019 at 3:49 PM Kamal Dasu wrote:
>
> For controller drivers that use DMA and set NAND_USE_BOUNCE_BUFFER
> option use data buffers that are not vmalloced, aligned and have
> valid virtual address to be able to do D
vmalloced data buffer for
DMA transfers.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/nand_base.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 91f046d4d452..46f6965a896a 100644
This change adds support for flash dma v0.0.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
The spi-nor controller defaults to BSPI mode. So its being put to its
default mode.
Kamal
On Tue, Aug 6, 2019 at 8:16 AM Mark Brown wrote:
>
> On Tue, Aug 06, 2019 at 03:44:34PM +0530, Rayagonda Kokatanur wrote:
> > Switch back to BSPI mode after MSPI operations (write and erase)
> > are comple
From: Claire Lin
In brcmstb_nand_verify_erased_page(), fix ecc chunk pointer calculation
while correcting erased page bitflip.
Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Claire Lin
Reviewed-by: Ray Jui
Signed-off-by: Kamal Dasu
---
d
If mtd_oops is in progress, switch to polling during NAND command
completion instead of relying on DMA/interrupts so that the mtd_oops
buffer can be completely written in the assigned NAND partition.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 48
Added a flag to indicate a panic_write so that low level drivers can
use it to take required action where applicable, to ensure oops data
gets written to assigned mtd device.
Signed-off-by: Kamal Dasu
---
drivers/mtd/mtdcore.c | 3 +++
include/linux/mtd/mtd.h | 6 ++
2 files changed, 9
Richard,
You have any other review comments/concerns with this patch, if not
can you please sign off on it.
Thanks
Kamal
On Fri, May 17, 2019 at 7:56 AM Kamal Dasu wrote:
>
> On Fri, May 17, 2019 at 4:12 AM Richard Weinberger
> wrote:
> >
> > On Thu, May 16, 2019 at 6:42
Refactored NAND ECC and CMD address configuration code to use helper
functions.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 100 +++
1 file changed, 62 insertions(+), 38 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
This change adds support for brcm NAND v7.3 controller. This controller
uses a newer version of flash_dma engine and change mostly implements
these differences.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 102 ---
1 file changed, 80
Added brcm,brcmnand-v7.3 as possible compatible string to support
brcmnand controller v7.3.
Signed-off-by: Kamal Dasu
---
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
b
On Mon, Jun 3, 2019 at 10:18 AM Boris Brezillon
wrote:
>
> On Mon, 3 Jun 2019 10:11:20 -0400
> Kamal Dasu wrote:
>
> > Boris,
> >
> > On Sat, Jun 1, 2019 at 3:57 AM Boris Brezillon
> > wrote:
> > >
> > > On Thu, 30 May 2019 17:20:35 -0400
Boris,
On Sat, Jun 1, 2019 at 3:57 AM Boris Brezillon
wrote:
>
> On Thu, 30 May 2019 17:20:35 -0400
> Kamal Dasu wrote:
>
> > Refactored NAND ECC and CMD address configuration code to use inline
> > functions.
>
> I'd expect the compiler to be smar
This change adds support for brcm NAND v7.3 controller. This controller
uses a newer version of flash_dma engine and change mostly implements
these differences.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 102 ---
1 file changed, 80
Refactored NAND ECC and CMD address configuration code to use inline
functions.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 100 +++
1 file changed, 62 insertions(+), 38 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
Added brcm,brcmnand-v7.3 as possible compatible string to support
brcmnand controller v7.3.
Signed-off-by: Kamal Dasu
---
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
b
nand-controller.yaml replaced nand.txt however the references to it were
not updated. This change updates these references wherever it appears in
bindings documentation.
Fixes: 212e49693592 ("dt-bindings: mtd: Add YAML schemas for the generic NAND
options")
Signed-off-by:
ues.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index ce0b8ff..1bdd490 100644
--- a/drivers/mtd/nand/raw/brcmn
nand-ecc-strength and nand-ecc-step-size can be made optional as
brcmnand driver can support using raw NAND layer detected values.
Signed-off-by: Kamal Dasu
---
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a
nand-ecc-strength and nand-ecc-step-size can be made optional as
brcmnand driver can support using raw NAND layer detected values.
Signed-off-by: Kamal Dasu
---
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
ues.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index ce0b8ff..a4d2057 100644
--- a/drivers/mtd/nand/raw/brcmn
On Mon, May 20, 2019 at 1:34 PM Miquel Raynal wrote:
>
> Hi Kamal,
>
> Kamal Dasu wrote on Mon, 20 May 2019 13:31:52
> -0400:
>
> > Will make the changes and send a V2 patch.
> >
> > On Mon, May 20, 2019 at 8:44 AM Miquel Raynal
> > wrote:
> > &g
Will make the changes and send a V2 patch.
On Mon, May 20, 2019 at 8:44 AM Miquel Raynal wrote:
>
> Hi Kamal,
>
> Kamal Dasu wrote on Fri, 17 May 2019 14:29:55
> -0400:
>
> > This change supports nand-ecc-step-size and nan
ues.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index ce0b8ff..e967b30 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++
nand-ecc-strength and nand-ecc-step-size can be made optional as
brcmanand driver can support using the nand_base driver detected
values.
Signed-off-by: Kamal Dasu
---
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
On Fri, May 17, 2019 at 4:12 AM Richard Weinberger
wrote:
>
> On Thu, May 16, 2019 at 6:42 PM Kamal Dasu wrote:
> >
> > If mtd_oops is in progress, switch to polling during NAND command
> > completion instead of relying on DMA/interrupts so that the mtd_oops
> > bu
If mtd_oops is in progress, switch to polling during NAND command
completion instead of relying on DMA/interrupts so that the mtd_oops
buffer can be completely written in the assigned NAND partition.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 48
Added a flag to indicate a panic_write so that low level drivers can
use it to take required action where applicable, to ensure oops data
gets written to assigned mtd device.
Signed-off-by: Kamal Dasu
---
drivers/mtd/mtdcore.c | 3 +++
include/linux/mtd/mtd.h | 6 ++
2 files changed, 9
Please ignore v2 patch 1/2 and 2/2. The commit ordering is not right.
v3 patch on the way
Kamal
On Thu, May 16, 2019 at 12:01 PM Kamal Dasu wrote:
>
> If mtd_oops is in progress switch to polling for nand command completion
> interrupts and use PIO mode wihtout DMA so that the mtd_oo
If mtd_oops is in progress switch to polling for nand command completion
interrupts and use PIO mode wihtout DMA so that the mtd_oops buffer can
be completely written in the assinged nand partition.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 1 -
1 file changed, 1
Added a flag to indicate a panic_write so that low level drivers can
use it to take required action where applicable, to ensure oops data
gets written to assigned mtd device.
Signed-off-by: Kamal Dasu
---
drivers/mtd/mtdcore.c| 3 ++
drivers/mtd/nand/raw/brcmnand/brcmnand.c
On Mon, May 6, 2019 at 12:01 PM Richard Weinberger
wrote:
>
> On Wed, May 1, 2019 at 7:52 PM Kamal Dasu wrote:
> >
> > If mtd_oops is in progress switch to polling for nand command completion
> > interrupts and use PIO mode wihtout DMA so that the mtd_oops buffer can
>
IRQs are wired to cpu0.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 55 ++--
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 482c6f0
On Thu, May 2, 2019 at 4:25 AM Miquel Raynal wrote:
>
> Hi Kamal,
>
> Kamal Dasu wrote on Wed, 1 May 2019 13:46:15
> -0400:
>
> > If mtd_oops is in progress switch to polling for nand command completion
>
> s/nand/NAND/
Will change this.
>
> > interrup
The oobregion->offset for large page nand parts was wrong, change
fixes this error in calculation.
Fixes: ef5eeea6e911 ("mtd: nand: brcm: switch to mtd_ooblayout_ops")
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 2 +-
1 file changed, 1 insertion(+
On Wed, May 1, 2019 at 2:35 PM Florian Fainelli wrote:
>
> On 4/26/19 12:22 PM, Kamal Dasu wrote:
> > The oobregion->offset for large page nand parts was wrong, change
> > fixes this error in calculation.
>
> Should this have a Fixes tag so this can be backported
and the panic is not on cpu0.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 55 ++--
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index
The oobregion->offset for large page nand parts was wrong, change
fixes this error in calculation.
Signed-off-by: Kamal Dasu
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/
.
> Following this convention solves the issue.
>
> Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
> Signed-off-by: Justin Chen
Signed-off-by: Kamal Dasu
> ---
> drivers/spi/spi-bcm-qspi.c | 8
> 1 file changed, 4 insertions(+), 4 deletions
On Mon, Dec 10, 2018 at 4:03 PM Wolfram Sang
wrote:
>
> Rejecting transfers should be handled by the core.
>
> Signed-off-by: Wolfram Sang
Reviewed-by: Kamal Dasu
> ---
> drivers/i2c/busses/i2c-brcmstb.c | 13 ++---
> 1 file changed, 2 insertions(+), 11 deletion
: bcm-qspi: Add Broadcom MSPI driver")
Signed-off-by: Kamal Dasu
---
drivers/spi/spi-bcm-qspi.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 1596d35..2946989 100644
--- a/drivers/s
When using the spi-nor master controller always verify the chip select
bit in the cs register. Also do not use CDRAM PCS bit in BSPI mode.
Additionally make sure to enable/disable BSPI_MAST_N_BOOT_CTRL while using
BSPI mode.
V2 changes:
- Added "Fixes:" tag to 1/2 and 2/2 patches
Kam
Always confirm the BSPI_MAST_N_BOOT_CTRL bit when enabling
or disabling BSPI transfers.
Fixes: 4e3b2d236fe00 ("spi: bcm-qspi: Add BSPI spi-nor flash controller driver")
Signed-off-by: Kamal Dasu
---
drivers/spi/spi-bcm-qspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Added fix for probing of spi-nor device non-zero chip selects. Set
MSPI_CDRAM_PCS (peripheral chip select) with spi master for MSPI
controller and not for MSPI/BSPI spi-nor master controller. Ensure
setting of cs bit in chip select register on chip select change.
Signed-off-by: Kamal Dasu
.
*** BLURB HERE ***
Kamal Dasu (2):
spi: bcm-qspi: Avoid setting MSPI_CDRAM_PCS for spi-nor master
spi: bcm-qspi: Always change BSPI_MAST_N_BOOT_CTRL state
drivers/spi/spi-bcm-qspi.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions(-)
--
2.7.4
Always confirm the BSPI_MAST_N_BOOT_CTRL bit when enabling
or disabling BSPI transfers.
Signed-off-by: Kamal Dasu
---
drivers/spi/spi-bcm-qspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 2946989..6573152
Implemented and populated spi-nor mtd PM handlers for resume ops.
spi-nor resume op re-initializes spi-nor flash to its probed
state by calling the newly implemented spi_nor_init() function.
Signed-off-by: Kamal Dasu
---
drivers/mtd/spi-nor/spi-nor.c | 14 ++
1 file changed, 14
his is needed S2/S3 PM
on platfroms that turn off power to the spi-nor flash on pm suspend.
Kamal Dasu (2):
mtd: spi-nor: add spi_nor_init() function
mtd: spi-nor: Add spi-nor mtd resume handler
drivers/mtd/spi-nor/spi-nor.c | 68 +++
include/linux/mtd/
not supporting the 4-byte address
instruction set.
spi_nor_scan() now ends by calling spi_nor_init() once the probe phase has
completed. Further patches could also use spi_nor_init() to implement the
mtd->_resume() handler for the spi-nor framework.
Signed-off-by: Kamal Dasu
---
drivers/mtd/s
not supporting the 4-byte address
instruction set.
spi_nor_scan() now ends by calling spi_nor_init() once the probe phase has
completed. Further patches could also use spi_nor_init() to implement the
mtd->_resume() handler for the spi-nor framework.
Signed-off-by: Kamal Dasu
---
drivers/mtd/s
Implemented and populated spi-nor mtd PM handlers for resume ops.
spi-nor resume op re-initializes spi-nor flash to its probed
state by calling the newly implemented spi_nor_init() function.
Signed-off-by: Kamal Dasu
---
drivers/mtd/spi-nor/spi-nor.c | 13 +
1 file changed, 13
using the mtd
handlers for resume in the spi-nor driver. spi-nor mtd pm resume() calls
newly implemented spi_nor_init() function that sets up the spi-nor flash
to its pre-suspend/power-on probed state. This is needed S2/S3 PM
on platfroms that turn off power to the spi-nor flash on pm suspend.
Kamal
move the need to include
file by removing all use of SPINOR_OP_READ* macros.
Fixes: 4e3b2d236fe0 ("spi: bcm-qspi: Add BSPI spi-nor flash controller driver")
Link: https://patchwork.kernel.org/patch/9624585/
Signed-off-by: Kamal Dasu
---
drivers/
On Wed, Jul 26, 2017 at 3:03 AM, Arnd Bergmann wrote:
> On Tue, Jul 25, 2017 at 11:39 PM, Kamal Dasu wrote:
>> Arnd, Cyrille,
>>
>> I am working on fixing spi-bcm-qspi.c as per Cyrill's suggestion as
>> mentioned here : https://patchwork.kernel.org/patch/962
Arnd, Cyrille,
I am working on fixing spi-bcm-qspi.c as per Cyrill's suggestion as
mentioned here : https://patchwork.kernel.org/patch/9624585/.
And remove the use of SPINOR_OP_READ* and there by remove need to
include spi-nor.h.
Thanks
Kamal
On Fri, Jul 21, 2017 at 6:00 PM, Arnd Bergmann wrot
ew this patch?
>
>>
>> This patch was originally implemented by Prafulla Kota
>> and fully tested on iProc based NS2 SVK
>>
>> Signed-off-by: Prafulla Kota
>> Signed-off-by: Ray Jui
Acked-by: Kamal Dasu
>> ---
>> drivers/mtd/nand/brcmnand/
>
> Brian, Kamal, can you review this patch?
>
>>
>> This patch was originally implemented by Prafulla Kota
>> and fully tested on iProc based NS2 SVK
>>
>> Signed-off-by: Prafulla Kota
>> Signed-off-by: Ray Jui
Reviewed-by: Kamal Dasu
>> ---
ttern of the completion is:
>
> brcmstb_send_i2c_cmd()
> reinit_completion()
> ...
> /* initiate transfer by setting iic_enable */
> ...
> brcmstb_i2c_wait_for_completion()
>
> Signed-off-by: Daniel Wagner
Reviewed-by: Kamal Dasu
> ---
> drivers/i2c
; There is no good reason to kill the system when this condition occur
>> because we could have systems which listed the NAND controller as
>> available (e.g: from Device Tree), but the NAND chip could be
>> malfunctioning and not responding.
>>
>> Signed-off-by: Flori
This patch looks good to me.
Acked-by: Kamal Dasu
Thanks
Kamal
On Thu, Jun 2, 2016 at 1:13 PM, Boris Brezillon
wrote:
> On Tue, 31 May 2016 10:23:02 -0700
> Florian Fainelli wrote:
>
>> The 7.2 controller differs in a few area compared to its predecssor (7.1):
>>
>&
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