On Wed, Nov 11, 2020 at 04:14:36AM +0300, Dmitry Osipenko wrote:
> The latency allowness is calculated based on buffering capabilities of
> memory clients. Add FIFO sizes to the Tegra30 memory clients.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra30.c | 66
On Wed, Nov 11, 2020 at 04:14:33AM +0300, Dmitry Osipenko wrote:
> Factor out clk initialization and make it resource-managed. This makes
> easier to follow code and will help to make further changes cleaner.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra20-emc.c | 70
On Wed, Nov 11, 2020 at 04:14:32AM +0300, Dmitry Osipenko wrote:
> The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use
> dev_pm_opp_set_clkname() instead.
>
> Suggested-by: Viresh Kumar
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra20-emc.c | 30
On Wed, Nov 11, 2020 at 04:14:31AM +0300, Dmitry Osipenko wrote:
> Correct typo in a stub of devm_tegra_memory_controller_get() to fix a
> non-ARM kernel compile-testing.
>
> Reported-by: Stephen Rothwell
> Signed-off-by: Dmitry Osipenko
> ---
> include/soc/tegra/mc.h | 2 +-
Thanks, applied.
On Tue, Nov 10, 2020 at 08:32:26PM +0100, Sylwester Nawrocki wrote:
> The PLL status polling loops in the set_rate callbacks of some PLLs
> have no timeout detection and may become endless loops when something
> goes wrong with the PLL.
>
> For some PLLs there is already the ktime API based
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On Thu, Nov 12, 2020 at 03:36:35PM +0100, Sylwester Nawrocki wrote:
> On 11/10/20 20:37, Krzysztof Kozlowski wrote:
> > The Exynos clock output driver can be built as module (it does not have
> > to be part of core init process) for better customization. Adding a
> > KCon
On Thu, 12 Nov 2020 at 12:51, Łukasz Stelmach wrote:
>
> This is a driver for AX88796C Ethernet Adapter connected in SPI mode as
> found on ARTIK5 evaluation board. The driver has been ported from a
> v3.10.9 vendor kernel for ARTIK5 board.
>
> Changes in v6:
> - fixed typos in Kconfig
> -
djust its bank number.
>
> Each a bank is a iova_region which is a independent iommu-domain.
> the iova range for each iommu-domain can't cross 4G.
>
> Signed-off-by: Yong Wu
> Acked-by: Krzysztof Kozlowski # memory part
> ---
> drivers/iommu/mtk_iommu.c | 12 +++
e/soc/mediatek/smi.h | 2 --
> 4 files changed, 2 insertions(+), 9 deletions(-)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On Wed, Nov 11, 2020 at 08:38:19PM +0800, Yong Wu wrote:
> This patch adds decriptions for mt8192 IOMMU and SMI.
>
> mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> table format. The M4U-SMI HW diagram is as below:
>
> EMI
>
ndings/memory/mtk-smi-larb-port.h | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
e in its special
> range.
>
> This is a preparing patch for multi-domain support.
>
> Signed-off-by: Yong Wu
> ---
> include/dt-bindings/memory/mtk-smi-larb-port.h | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
ings/memory/mtk-smi-larb-port.h | 15 +++
> 6 files changed, 20 insertions(+), 5 deletions(-)
> create mode 100644 include/dt-bindings/memory/mtk-smi-larb-port.h
>
> diff --git a/include/dt-bindings/memory/mt2712-larb-port.h
> b/include/dt-bindings/memory/mt2712-larb-p
On Wed, 11 Nov 2020 at 10:32, Serge Semin
wrote:
>
> On Wed, Nov 11, 2020 at 10:16:28AM +0100, Krzysztof Kozlowski wrote:
> > On Wed, Nov 11, 2020 at 12:08:45PM +0300, Serge Semin wrote:
> > > DWC USB3 DT node is supposed to be compliant with the Generic xHCI
&g
On Wed, Nov 11, 2020 at 12:17:37PM +0300, Dmitry Osipenko wrote:
> 11.11.2020 12:04, Krzysztof Kozlowski пишет:
> >> -obj-$(CONFIG_TEGRA124_EMC)+= clk-tegra124-emc.o
> >> +obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-emc.o
> >> +obj-$(CONF
On Wed, Nov 11, 2020 at 12:08:45PM +0300, Serge Semin wrote:
> DWC USB3 DT node is supposed to be compliant with the Generic xHCI
> Controller schema, but with additional vendor-specific properties, the
> controller-specific reference clocks and PHYs. So let's convert the
> currently available
On Wed, Nov 11, 2020 at 04:14:41AM +0300, Dmitry Osipenko wrote:
> Add modularization support to the Tegra124 EMC driver, which now can be
> compiled as a loadable kernel module.
>
> Note that EMC clock must be registered at clk-init time, otherwise PLLM
> will be disabled as unused clock at boot
On Wed, Nov 11, 2020 at 09:51:15AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Nov 11, 2020 at 04:14:40AM +0300, Dmitry Osipenko wrote:
> > Factor out clk initialization and make it resource-managed. This makes
> > easier to follow code and will help to make further
On Wed, Nov 11, 2020 at 04:14:40AM +0300, Dmitry Osipenko wrote:
> Factor out clk initialization and make it resource-managed. This makes
> easier to follow code and will help to make further changes cleaner.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra30-emc.c | 70
The Exynos clock output driver can be built as module (it does not have
to be part of core init process) for better customization. Adding a
KConfig entry allows also compile testing for build coverage.
Signed-off-by: Krzysztof Kozlowski
---
drivers/clk/samsung/Kconfig | 10
On Thu, Sep 03, 2020 at 09:53:25PM +0200, Krzysztof Kozlowski wrote:
> Cover the dt-bindings of mailbox drivers by mailbox maintainers entry.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Changes since v1:
> 1. New patch
Jassi,
Any comments on this patch?
Best regards,
Krzysztof
There are four flavors of TechNexion PICO-IMX6 boards. They have their
own DTSes, even though in Dwarf, Nymph and Pi are exactly the same.
They also have their own bindings so adjust the compatibles to match the
bindings.
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. None
Document and adjust the compatibles for i.MX7S based boards.
The Toradex boards use multiple compatibles.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Rob Herring
---
Changes since v1:
1. Rebase,
2. Add Rob's review.
---
Documentation/devicetree/bindings/arm/fsl.yaml | 12 +---
1
On Thu, Nov 05, 2020 at 07:45:01PM +0100, Krzysztof Kozlowski wrote:
> Use hyphens instead of underscores in the Exynos3250 node names which is
> expected by naming convention, multiple dtschema files and pointed out
> by dtc W=2 builds. Use also generic "ppmu" node name for PP
On Wed, Nov 04, 2020 at 11:36:56AM +0100, Sylwester Nawrocki wrote:
> From: Artur Świgoń
>
> This patch adds an 'interconnects' property to Exynos4412 DTS in order to
> declare the interconnect path used by the mixer. Please note that the
> 'interconnect-names' property is not needed when there
On Wed, Nov 04, 2020 at 11:36:55AM +0100, Sylwester Nawrocki wrote:
> This patch adds the following properties for Exynos4412 interconnect
> bus nodes:
> - interconnects: to declare connections between nodes in order to
>guarantee PM QoS requirements between nodes,
> - #interconnect-cells:
On Tue, Nov 10, 2020 at 09:33:11AM +0800, Yu Kuai wrote:
> The reference to device obtained with of_find_device_by_node() should
> be dropped. Thus add jump target to fix the exception handling for this
> function implementation.
>
> Fixes: 73a7f0a90641("memory: tegra: Add EMC (external memory
On Tue, 10 Nov 2020 at 07:00, Frank Lee wrote:
>
> It seems that sending too many e-mails at one time will cause some
> emails to fail to be sent out. I will try again.
Hi,
Instead please reduce the address list to relevant people, as pointed
out by scripts/get_maintainer.pl. Don't Cc
On Mon, Nov 09, 2020 at 09:28:47PM +0800, Yu Kuai wrote:
> The reference to device obtained with of_find_device_by_node() should
> be dropped. Thus add jump target to fix the exception handling for this
> function implementation.
You still need to correct the typo devcie->device in subject, as in
On Mon, 9 Nov 2020 at 02:01, Dmitry Osipenko wrote:
>
> 09.11.2020 02:23, Stephen Rothwell пишет:
> > Hi all,
> >
> > After merging the drivers-memory tree, today's linux-next build (x86_64
> > allmodconfig) failed like this:
> >
> > In file included from drivers/devfreq/tegra20-devfreq.c:18:
> >
On Sun, 8 Nov 2020 at 20:13, Nathan Chancellor wrote:
>
> Hi Krzysztof,
>
> On Sun, Nov 08, 2020 at 10:31:10AM +0100, Krzysztof Kozlowski wrote:
> > On Sun, 8 Nov 2020 at 03:23, Nathan Chancellor
> > wrote:
> >
> > Hi,
> >
> > Thanks for the
On Sat, Nov 07, 2020 at 02:39:26PM +0100, Paweł Chmiel wrote:
> It's not possible to reboot or poweroff Exynos7420 using PSCI. Instead
> we need to use syscon reboot/poweroff drivers, like it's done for other
> Exynos SoCs. This was confirmed by checking vendor source and testing it
> on Samsung
On Sat, Nov 07, 2020 at 02:39:25PM +0100, Paweł Chmiel wrote:
> Exynos7 uses the same syscon reboot and poweroff nodes as other Exynos
> SoCs, so instead of duplicating code we can just include common dtsi
> file, which already contains definitions of them. After this change,
> poweroff node will
< IMX8MN_GPU_PLL_OUT>,
> + < IMX8MN_SYS_PLL1_800M>,
> + < IMX8MN_SYS_PLL1_800M>;
> + assigned-clock-rates = <0>, <0>, <8>,
> <4>, <12>,
> + <4>, <4>;
It would be nice to align indentation here to <0> above.
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
; Signed-off-by: Adam Ford
> ---
> V2: No change
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
+++
> 1 file changed, 36 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
to hang on next CMU access.
>
> Signed-off-by: Paweł Chmiel
> ---
> Changes from v1:
> - Instead of marking clock as critical, enable it manually in driver.
> ---
> drivers/clk/samsung/clk-exynos7.c | 5 +
> 1 file changed, 5 insertions(+)
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
is small change and should go with small
and accurate description. Blowing the description does not help.
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
ll be added to support HDMI.
>
> Signed-off-by: Adam Ford
> Reviewed-by: Krzysztof Kozlowski
> ---
> V3: Correct name
I don't think you corrected the name. It's still there.
Best regards,
Krzysztof
On Sat, Nov 07, 2020 at 06:33:31AM -0600, Adam Ford wrote:
> Add beacon,imx8mn-beacon-kit to list of compatible options.
>
> Signed-off-by: Adam Ford
> ---
> V3: Correct Typo and move to Nano section
> V2: New to series
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On Fri, Nov 06, 2020 at 09:12:45PM +0100, Krzysztof Kozlowski wrote:
> On Thu, Nov 05, 2020 at 08:55:08PM +0100, Pavel Machek wrote:
> > Hi!
> >
> > > > > The Power Management Unit (PMU) is a separate device which has little
> > > > > common with clock
On Thu, Nov 05, 2020 at 08:55:08PM +0100, Pavel Machek wrote:
> Hi!
>
> > > > The Power Management Unit (PMU) is a separate device which has little
> > > > common with clock controller. Moving it to one level up (from clock
> > > > controller child to SoC) allows to remove fake simple-bus
On Fri, Nov 06, 2020 at 10:35:35AM +, Alice Guo wrote:
>
>
> > -Original Message-
> > From: Krzysztof Kozlowski
> > Sent: 2020年11月5日 17:06
> > To: Alice Guo
> > Cc: robh...@kernel.org; shawn...@kernel.org; s.ha...@pengutronix.de;
>
; create mode 100644 Documentation/devicetree/bindings/net/asix,ax88796c.yaml
>
I assume bindings will go with the driver to the net. I applied only
ARM-specific bits.
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On Tue, Nov 03, 2020 at 04:15:36PM +0100, Łukasz Stelmach wrote:
> Enable ax88796c driver for the ethernet chip on Exynos3250-based
> ARTIK5 boards.
>
> Signed-off-by: Łukasz Stelmach
> ---
> arch/arm/configs/exynos_defconfig | 2 ++
> arch/arm/configs/multi_v7_defconfig | 2 ++
Thanks,
On Tue, Nov 03, 2020 at 04:15:35PM +0100, Łukasz Stelmach wrote:
> Add node for ax88796c ethernet chip.
>
> Signed-off-by: Łukasz Stelmach
> ---
> arch/arm/boot/dts/exynos3250-artik5-eval.dts | 29
> 1 file changed, 29 insertions(+)
Thanks, applied.
Best regards,
ll be added to support HDMI.
>
> Signed-off-by: Adam Ford
> ---
> Based on:
> https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=374643
>
> V2: Fix issues noted from Krzysztof Kozlowski.
> Set Bluetooth UART speed
> Add supply and reset gp
On Fri, Nov 06, 2020 at 06:12:35AM -0600, Adam Ford wrote:
> Add beacon,imx8mn-beacon-kit to list of compatible options.
>
> Signed-off-by: Adam Ford
> ---
> V2: New to series
>
> Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Wed, Nov 04, 2020 at 07:49:12PM +0300, Dmitry Osipenko wrote:
> Add devfreq support to the Tegra20 EMC driver. Memory utilization
> statistics will be periodically polled from the memory controller and
> appropriate minimum clock rate will be selected by the devfreq governor.
>
>
On Wed, Nov 04, 2020 at 07:49:11PM +0300, Dmitry Osipenko wrote:
> Now Internal and External Memory Controllers are memory interconnection
> providers. This allows us to use interconnect API for tuning of memory
> configuration. EMC driver now supports OPPs and DVFS.
>
> Signed-off-by: Dmitry
On Wed, Nov 04, 2020 at 07:49:10PM +0300, Dmitry Osipenko wrote:
> EMC driver will become mandatory after turning it into interconnect
> provider because interconnect users, like display controller driver, will
> fail to probe using newer device-trees that have interconnect properties.
> Thus make
On Wed, Nov 04, 2020 at 07:49:09PM +0300, Dmitry Osipenko wrote:
> Add modularization support to the Tegra20 EMC driver, which now can be
> compiled as a loadable kernel module.
>
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/Kconfig | 2 +-
>
On Wed, Nov 04, 2020 at 07:49:08PM +0300, Dmitry Osipenko wrote:
> Add common SoC-agnostic ICC framework which turns Tegra Memory Controller
> into a memory interconnection provider. This allows us to use interconnect
> API for tuning of memory configurations.
>
> Tested-by: Peter Geis
>
On Wed, Nov 04, 2020 at 07:49:07PM +0300, Dmitry Osipenko wrote:
> Add missing PTC memory client latency allowness entry to the Tegra MC
> drivers.
>
> This prevents erroneous clearing of MC_INTSTATUS 0x0 register during
> of the LA programming in tegra_mc_setup_latency_allowance() due to the
>
On Wed, Nov 04, 2020 at 07:49:06PM +0300, Dmitry Osipenko wrote:
> The platform_get_irq() prints error message telling that interrupt is
> missing, hence there is no need to duplicated that message in the drivers.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/mc.c | 4
On Wed, Nov 04, 2020 at 07:49:05PM +0300, Dmitry Osipenko wrote:
> Use devm_platform_ioremap_resource() helper which makes code a bit
> cleaner.
>
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra124-emc.c | 4 +---
>
On Wed, Nov 04, 2020 at 07:49:04PM +0300, Dmitry Osipenko wrote:
> Multiple Tegra drivers need to retrieve Memory Controller and there is
> duplication of the retrieval code among the drivers.
>
> Add new devm_tegra_memory_controller_get() helper to remove the code's
> duplication and to fix
On Wed, Nov 04, 2020 at 07:48:55PM +0300, Dmitry Osipenko wrote:
> Each memory client has unique hardware ID, add these IDs.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Dmitry Osipenko
> ---
> include/dt-bindings/memory/tegra124-mc.h | 68
> 1 file changed, 68
On Wed, Nov 04, 2020 at 07:48:54PM +0300, Dmitry Osipenko wrote:
> Each memory client has unique hardware ID, add these IDs.
>
> Acked-by: Rob Herring
> Signed-off-by: Dmitry Osipenko
> ---
> include/dt-bindings/memory/tegra30-mc.h | 67 +
> 1 file changed, 67
On Wed, Nov 04, 2020 at 07:48:53PM +0300, Dmitry Osipenko wrote:
> Each memory client has unique hardware ID, add these IDs.
>
> Acked-by: Rob Herring
> Signed-off-by: Dmitry Osipenko
> ---
> include/dt-bindings/memory/tegra20-mc.h | 53 +
> 1 file changed, 53
On Wed, Nov 04, 2020 at 07:48:50PM +0300, Dmitry Osipenko wrote:
> Document new OPP table and voltage regulator properties which are needed
> for supporting dynamic voltage-frequency scaling of the memory controller.
> Some boards may have a fixed core voltage regulator, hence it's optional
>
On Wed, Nov 04, 2020 at 07:48:52PM +0300, Dmitry Osipenko wrote:
> Most of Host1x devices have at least one memory client. These clients
> are directly connected to the memory controller. The new interconnect
> properties represent the memory client's connection to the memory
> controller.
>
>
On Wed, Nov 04, 2020 at 07:48:51PM +0300, Dmitry Osipenko wrote:
> Document EMC DFS OPP table and interconnect paths that will be used
> for scaling of system's memory bandwidth based on memory utilization
> statistics. Previously ACTMON was supposed to drive EMC clock rate
> directly, but now it
On Wed, Nov 04, 2020 at 07:48:49PM +0300, Dmitry Osipenko wrote:
> External memory controller is interconnected with memory controller and
> with external memory. Document new interconnect property which turns
> External Memory Controller into interconnect provider.
>
> Reviewed-by: Rob Herring
On Wed, Nov 04, 2020 at 07:48:48PM +0300, Dmitry Osipenko wrote:
> Memory controller is interconnected with memory clients and with the
> External Memory Controller. Document new interconnect property which
> turns memory controller into interconnect provider.
>
> Signed-off-by: Dmitry Osipenko
On Wed, Nov 04, 2020 at 07:48:47PM +0300, Dmitry Osipenko wrote:
> Document new OPP table and voltage regulator properties which are needed
> for supporting dynamic voltage-frequency scaling of the memory controller.
> Some boards may have a fixed core voltage regulator, hence it's optional
>
On Wed, Nov 04, 2020 at 07:48:46PM +0300, Dmitry Osipenko wrote:
> External memory controller is interconnected with memory controller and
> with external memory. Document new interconnect property which turns
> External Memory Controller into interconnect provider.
>
> Acked-by: Rob Herring
>
On Wed, Nov 04, 2020 at 07:48:44PM +0300, Dmitry Osipenko wrote:
> The SoC core voltage can't be changed without taking into account the
> clock rate of External Memory Controller. Document OPP table that will
> be used for dynamic voltage frequency scaling, taking into account EMC
> voltage
On Wed, Nov 04, 2020 at 07:48:45PM +0300, Dmitry Osipenko wrote:
> Memory controller is interconnected with memory clients and with the
> External Memory Controller. Document new interconnect property which
> turns memory controller into interconnect provider.
>
> Acked-by: Rob Herring
>
On Wed, Nov 04, 2020 at 07:48:43PM +0300, Dmitry Osipenko wrote:
> External Memory Controller is interconnected with memory controller and
> with external memory. Document new interconnect property which turns EMC
> into interconnect provider.
>
> Acked-by: Rob Herring
> Signed-off-by: Dmitry
On Wed, Nov 04, 2020 at 07:48:42PM +0300, Dmitry Osipenko wrote:
> Memory controller is interconnected with memory clients and with the
> External Memory Controller. Document new interconnect property which
> turns memory controller into interconnect provider.
>
> Acked-by: Rob Herring
>
On Wed, Nov 04, 2020 at 07:48:41PM +0300, Dmitry Osipenko wrote:
> Tegra20 External Memory Controller talks to DRAM chips and it needs to be
> reprogrammed when memory frequency changes. Tegra Memory Controller sits
> behind EMC and these controllers are tightly coupled. This patch adds the
> new
On Wed, Nov 04, 2020 at 07:48:40PM +0300, Dmitry Osipenko wrote:
> There is superfluous zero in the registers base address and registers
> size should be twice bigger.
>
> Acked-by: Rob Herring
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
>
On Wed, Nov 04, 2020 at 07:48:39PM +0300, Dmitry Osipenko wrote:
> Drivers that use tegra_sku_info and have COMPILE_TEST are failing to be
> build due to the missing stub for tegra_sku_info, thus add the missing
> stub.
>
> Signed-off-by: Dmitry Osipenko
> ---
> include/soc/tegra/fuse.h | 4
On Wed, Nov 04, 2020 at 07:48:38PM +0300, Dmitry Osipenko wrote:
> The tegra_read_ram_code() is used by EMC drivers and we're going to make
> these driver modular, hence this function needs to be exported.
>
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
>
On Wed, Nov 04, 2020 at 07:48:37PM +0300, Dmitry Osipenko wrote:
> We're going to modularize Tegra EMC drivers and some of the EMC-clock
> driver symbols need to be exported, let's export them.
>
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
>
On Thu, Nov 05, 2020 at 12:18:23PM +0100, Anders Roxell wrote:
> While trying to do 'make dtbs_install' the following error shows up
>
> make[3]: *** No rule to make target
>
> '/srv/src/kernel/next/out/obj-arm64-next-20201105/dtbsinstall/freescale/imx8mm-kontron-n801x-s.dts',
> needed by
On Tue, Nov 03, 2020 at 07:44:12PM +0100, Łukasz Stelmach wrote:
> Add Ethernet interface description for Odroid X/X2.
>
> Add an alias to enable bootloaders to find the Ethernet
> interface and assign a MAC address.
>
> Signed-off-by: Łukasz Stelmach
> ---
>
On Tue, Nov 03, 2020 at 07:44:11PM +0100, Łukasz Stelmach wrote:
> Add Ethernet interface description for Odroid U3.
>
> Add an alias to enable bootloaders to find the Ethernet
> interface and assign a MAC address.
>
> Signed-off-by: Łukasz Stelmach
> ---
>
On Tue, Nov 03, 2020 at 07:44:10PM +0100, Łukasz Stelmach wrote:
> Add Ethernet interface description for Odroid XU.
>
> Add an alias to enable bootloaders to find the Ethernet
> interface and assign a MAC address.
>
> Signed-off-by: Łukasz Stelmach
> ---
>
On Tue, Nov 03, 2020 at 07:44:09PM +0100, Łukasz Stelmach wrote:
> Add Ethernet interface description for Odroid XU3 Lite.
>
> Add an alias to enable bootloaders to find the Ethernet
> interface and assign a MAC address.
>
> Signed-off-by: Łukasz Stelmach
> ---
>
On Tue, Nov 03, 2020 at 07:44:07PM +0100, Łukasz Stelmach wrote:
> Assign appropriate compatible properties.
>
> Signed-off-by: Łukasz Stelmach
This and #2 will have to wait till I figure out what happened my
previous pull request. I'll keep it in my queue.
Best regards,
Krzysztof
On Sun, Oct 04, 2020 at 03:38:18PM +0200, Krzysztof Kozlowski wrote:
> Hi,
>
> On top of previous pull request.
>
> Best regards,
> Krzysztof
Dear Arnd and Olof,
I got a notification from Patchwork that this was merged but I cannot
find it in your for-next or fixes.
Shall
On Thu, Oct 29, 2020 at 02:40:17PM +0100, Marek Szyprowski wrote:
> From: Jaehoon Chung
>
> Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the
> WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC).
>
> Signed-off-by: Jaehoon Chung
> [mszyprow: rewrote
On Tue, Nov 03, 2020 at 01:42:00PM +0800, Yong Wu wrote:
> Add mt8192 smi support.
>
> Signed-off-by: Yong Wu
> ---
> drivers/memory/mtk-smi.c | 19 +++
Thanks, applied.
Best regards,
Krzysztof
On Tue, Nov 03, 2020 at 01:41:59PM +0800, Yong Wu wrote:
> Add mt8192 smi support in the bindings.
>
> Signed-off-by: Yong Wu
> Reviewed-by: Rob Herring
> ---
> .../bindings/memory-controllers/mediatek,smi-common.yaml | 4 +++-
> .../bindings/memory-controllers/mediatek,smi-larb.yaml
On Tue, Nov 03, 2020 at 01:41:58PM +0800, Yong Wu wrote:
> Convert MediaTek SMI to DT schema.
>
> Signed-off-by: Yong Wu
> ---
> .../mediatek,smi-common.txt | 50 ---
> .../mediatek,smi-common.yaml | 140 ++
>
Document the compatible for SolidRun LX2160A based boards.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/arm/fsl.yaml | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml
b/Documentation/devicetree/bindings/arm
Document the compatible for LS1012A FRWY board.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml
b/Documentation/devicetree/bindings/arm/fsl.yaml
index
Use a generic name for the max77693 motor driver in Exynos4412 Midas
boards to align with Devicetree specification naming convention.
Signed-off-by: Krzysztof Kozlowski
---
arch/arm/boot/dts/exynos4412-midas.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot
Use hyphens instead of underscores in the Exynos4210 and Exynos4412 node
names which is expected by naming convention, multiple dtschema files
and pointed out by dtc W=2 builds. Use also generic "ppmu" node name
for PPMU nodes to match Devicetree specification.
Signed-off-by: Krzysztof
Use hyphens instead of underscores in the MFC reserved memory node names
which is expected by naming convention, multiple dtschema files and
pointed out by dtc W=2 builds.
Signed-off-by: Krzysztof Kozlowski
---
arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi | 4 ++--
1 file changed, 2
Use hyphens instead of underscores in the Exynos5433 node names which is
expected by naming convention, multiple dtschema files and pointed out
by dtc W=2 builds.
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi| 10 +-
arch/arm64/boot/dts
Use hyphens instead of underscores in the Exynos5250 and Exynos542x node
names which is expected by naming convention, multiple dtschema files
and pointed out by dtc W=2 builds.
Signed-off-by: Krzysztof Kozlowski
---
arch/arm/boot/dts/exynos5250.dtsi | 2 +-
arch/arm/boot/dts
Use hyphens instead of underscores in the Exynos3250 node names which is
expected by naming convention, multiple dtschema files and pointed out
by dtc W=2 builds. Use also generic "ppmu" node name for PPMU nodes to
match Devicetree specification.
Signed-off-by: Krzysztof Kozlowski
---
On Thu, 5 Nov 2020 at 12:46, Pavel Machek wrote:
>
> Hi!
>
> > The Power Management Unit (PMU) is a separate device which has little
> > common with clock controller. Moving it to one level up (from clock
> > controller child to SoC) allows to remove fake simple-bus compatible and
> > dtbs_check
On Thu, 5 Nov 2020 at 13:19, Alice Guo wrote:
>
>
>
> > -Original Message-
> > From: Krzysztof Kozlowski
> > Sent: 2020年11月5日 16:26
> > To: Alice Guo
> > Cc: robh...@kernel.org; shawn...@kernel.org; s.ha...@pengutronix.de;
> > dl-linux-im
On Thu, Nov 05, 2020 at 03:26:29PM +0800, Alice Guo wrote:
> Directly reading ocotp register depends on that bootloader enables ocotp
> clk, which is not always effective, so change to use nvmem API. Using
> nvmem API requires to support driver defer probe and thus change
> soc-imx8m.c to use
On Thu, Nov 05, 2020 at 03:26:26PM +0800, Alice Guo wrote:
> Add DT Binding doc for the Unique ID of i.MX 8M series.
>
> Signed-off-by: Alice Guo
> ---
> .../devicetree/bindings/arm/fsl.yaml | 33 +++
> 1 file changed, 33 insertions(+)
>
> diff --git
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