The binding spec wasn't clear that the order of the phandles in the
usb-phy array has meaning. Clarify this point in the binding that
it should be .
Signed-off-by: Kumar Gala
---
Documentation/devicetree/bindings/usb/dwc3.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
On Aug 9, 2013, at 10:47 AM, Laxman Dewangan wrote:
> Renaming the charging property names to have more meaningful:
>
> Renaming property "ti,back-battery-charge-enable" to
> "ti,backup-battery-chargeable"
> to tells OS that attahced battery is chargeable and OS can do charging.
>
> Renaming
On Aug 9, 2013, at 10:47 AM, Laxman Dewangan wrote:
Renaming the charging property names to have more meaningful:
Renaming property ti,back-battery-charge-enable to
ti,backup-battery-chargeable
to tells OS that attahced battery is chargeable and OS can do charging.
Renaming property
The binding spec wasn't clear that the order of the phandles in the
usb-phy array has meaning. Clarify this point in the binding that
it should be USB2-HS-PHY, USB3-SS-PHY.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
Documentation/devicetree/bindings/usb/dwc3.txt | 4 +++-
1 file changed
of above patch
as per discussion on above patch.
.../devicetree/bindings/rtc/rtc-palmas.txt | 21 +++
drivers/rtc/rtc-palmas.c | 14 ++--
2 files changed, 19 insertions(+), 16 deletions(-)
Acked-by: Kumar Gala ga...@codeaurora.org
- k
On Aug 9, 2013, at 11:28 AM, Mark Rutland wrote:
On Fri, Aug 09, 2013 at 04:40:32PM +0100, Kumar Gala wrote:
The binding spec wasn't clear that the order of the phandles in the
usb-phy array has meaning. Clarify this point in the binding that
it should be USB2-HS-PHY, USB3-SS-PHY.
Signed
I'm tossing my hat into the ring of maintainers/reviewers for device tree
bindings based on history of dealing with DT on embedded PPC and starting
work on ARM SoCs.
Signed-off-by: Kumar Gala
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Stephen Warren
Cc: Ian Campbell
Cc: Rob Herring
Cc: Grant
I'm tossing my hat into the ring of maintainers/reviewers for device tree
bindings based on history of dealing with DT on embedded PPC and starting
work on ARM SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Stephen
On Aug 7, 2013, at 10:52 AM, Mark Langsdorf wrote:
> The Calxeda sata_highbank driver has been adding its descriptions to the
> ahci driver. Separate them properly.
>
> Signed-off-by: Mark Langsdorf
> Acked-by: Rob Herring
> ---
> Changes from v2
> Fixed some indenting.
> Changes from
On Aug 7, 2013, at 10:52 AM, Mark Langsdorf wrote:
The Calxeda sata_highbank driver has been adding its descriptions to the
ahci driver. Separate them properly.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Acked-by: Rob Herring rob.herr...@calxeda.com
---
Changes from v2
On Aug 6, 2013, at 1:28 PM, Rohit Vaswani wrote:
> On 8/6/2013 8:47 AM, Kumar Gala wrote:
>> On Aug 5, 2013, at 6:02 PM, Rohit Vaswani wrote:
>>
>>> This patch adds basic board support for MSM8974 Dragonboard
>>> which belongs to the Snapdragon 800 family.
On Aug 5, 2013, at 6:02 PM, Rohit Vaswani wrote:
> This patch adds basic board support for MSM8974 Dragonboard
> which belongs to the Snapdragon 800 family.
> For now, just support a basic machine with device tree.
I think the board is APQ8074 and not MSM8974.
>
> Signed-off-by: Rohit Vaswani
On Aug 5, 2013, at 6:02 PM, Rohit Vaswani wrote:
This patch adds basic board support for MSM8974 Dragonboard
which belongs to the Snapdragon 800 family.
For now, just support a basic machine with device tree.
I think the board is APQ8074 and not MSM8974.
Signed-off-by: Rohit Vaswani
On Aug 6, 2013, at 1:28 PM, Rohit Vaswani wrote:
On 8/6/2013 8:47 AM, Kumar Gala wrote:
On Aug 5, 2013, at 6:02 PM, Rohit Vaswani wrote:
This patch adds basic board support for MSM8974 Dragonboard
which belongs to the Snapdragon 800 family.
For now, just support a basic machine
On Aug 1, 2013, at 9:15 PM, Rohit Vaswani wrote:
> Add the cpus bindings and the Kraitv2 release sequence
> to make SMP work for 2 cores on MSM8974.
>
> Signed-off-by: Rohit Vaswani
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> arch/arm/boot/dts/msm8974.dts |
On Aug 1, 2013, at 9:15 PM, Rohit Vaswani wrote:
> Add the cpus bindings and the Krait release sequence
> to make SMP work for MSM8960
>
> Signed-off-by: Rohit Vaswani
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 2 +
> Documentation/devicetree/bindings/arm/msm/kpss.txt | 16
On Aug 1, 2013, at 9:15 PM, Rohit Vaswani wrote:
Add the cpus bindings and the Krait release sequence
to make SMP work for MSM8960
Signed-off-by: Rohit Vaswani rvasw...@codeaurora.org
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 +
On Aug 1, 2013, at 9:15 PM, Rohit Vaswani wrote:
Add the cpus bindings and the Kraitv2 release sequence
to make SMP work for 2 cores on MSM8974.
Signed-off-by: Rohit Vaswani rvasw...@codeaurora.org
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm/boot/dts/msm8974.dts
On Jul 29, 2013, at 4:54 PM, Kumar Gala wrote:
>
> On Jul 29, 2013, at 4:40 PM, Stephen Boyd wrote:
>
>> On 07/29, Kumar Gala wrote:
>>>> diff --git a/Documentation/devicetree/bindings/arm/msm/tcsr-mutex.txt
>>>> b/Documentation/devicetree/bindings/ar
On Jul 29, 2013, at 4:54 PM, Kumar Gala wrote:
On Jul 29, 2013, at 4:40 PM, Stephen Boyd wrote:
On 07/29, Kumar Gala wrote:
diff --git a/Documentation/devicetree/bindings/arm/msm/tcsr-mutex.txt
b/Documentation/devicetree/bindings/arm/msm/tcsr-mutex.txt
new file mode 100644
index
Add driver for Qualcomm MSM Hardware Mutex block that exists on newer MSM
SoC (MSM8974, etc).
CC: Jeffrey Hugo
CC: Eric Holmberg
Signed-off-by: Kumar Gala
---
v2:
* Fixed init of stride
* Dealt with a number of comments from Stephen Boyd:
- use of instead of
- declaring
On Jul 29, 2013, at 4:40 PM, Stephen Boyd wrote:
> On 07/29, Kumar Gala wrote:
>>> diff --git a/Documentation/devicetree/bindings/arm/msm/tcsr-mutex.txt
>>> b/Documentation/devicetree/bindings/arm/msm/tcsr-mutex.txt
>>> new file mode 100644
>>> index 0
On Jul 29, 2013, at 3:11 PM, Kumar Gala wrote:
> Add driver for Qualcomm MSM Hardware Mutex block that exists on newer MSM
> SoC (MSM8974, etc).
>
> CC: Jeffrey Hugo
> CC: Eric Holmberg
> Signed-off-by: Kumar Gala
> ---
[ had old device tree mailing list ]
> .../dev
Add driver for Qualcomm MSM Hardware Mutex block that exists on newer MSM
SoC (MSM8974, etc).
CC: Jeffrey Hugo
CC: Eric Holmberg
Signed-off-by: Kumar Gala
---
.../devicetree/bindings/arm/msm/tcsr-mutex.txt | 20 +++
drivers/hwspinlock/Kconfig | 11 ++
drivers
Add driver for Qualcomm MSM Hardware Mutex block that exists on newer MSM
SoC (MSM8974, etc).
CC: Jeffrey Hugo jh...@codeaurora.org
CC: Eric Holmberg eholm...@codeaurora.org
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
.../devicetree/bindings/arm/msm/tcsr-mutex.txt | 20 +++
drivers
On Jul 29, 2013, at 3:11 PM, Kumar Gala wrote:
Add driver for Qualcomm MSM Hardware Mutex block that exists on newer MSM
SoC (MSM8974, etc).
CC: Jeffrey Hugo jh...@codeaurora.org
CC: Eric Holmberg eholm...@codeaurora.org
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
[ had old
On Jul 29, 2013, at 4:40 PM, Stephen Boyd wrote:
On 07/29, Kumar Gala wrote:
diff --git a/Documentation/devicetree/bindings/arm/msm/tcsr-mutex.txt
b/Documentation/devicetree/bindings/arm/msm/tcsr-mutex.txt
new file mode 100644
index 000..ddd6889
--- /dev/null
+++ b/Documentation
Add driver for Qualcomm MSM Hardware Mutex block that exists on newer MSM
SoC (MSM8974, etc).
CC: Jeffrey Hugo jh...@codeaurora.org
CC: Eric Holmberg eholm...@codeaurora.org
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Fixed init of stride
* Dealt with a number of comments from
On Jun 28, 2013, at 6:25 PM, Rohit Vaswani wrote:
> pen_release is no longer required as the synchronization
> is now managed by generic arm code.
> This is done as suggested in https://lkml.org/lkml/2013/6/4/184
>
> Signed-off-by: Rohit Vaswani
> ---
> arch/arm/mach-msm/headsmp.S | 41
On Jun 28, 2013, at 6:25 PM, Rohit Vaswani wrote:
pen_release is no longer required as the synchronization
is now managed by generic arm code.
This is done as suggested in https://lkml.org/lkml/2013/6/4/184
Signed-off-by: Rohit Vaswani rvasw...@codeaurora.org
---
On Jul 5, 2013, at 1:27 AM,
wrote:
> From: Hongbo Zhang
>
> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch add
> the device tree nodes for them.
>
> Signed-off-by: Hongbo Zhang
> ---
> arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 90
On Jul 5, 2013, at 1:27 AM,
wrote:
> From: Hongbo Zhang
>
> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch add
> the device tree nodes for them.
>
> Signed-off-by: Hongbo Zhang
> ---
> arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 90
On Jul 5, 2013, at 1:27 AM, hongbo.zh...@freescale.com
hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
On Jul 5, 2013, at 1:27 AM, hongbo.zh...@freescale.com
hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
hen a device is attached to a domain.
>
> Signed-off-by: Varun Sethi
> ---
> - no change in v11.
> - no change in v10.
> - Added CONFIG_IOMMU_API in v9.
> arch/powerpc/include/asm/device.h |6 ++
> 1 files changed, 6 insertions(+), 0 deletions(-)
Acked-by: Kumar Gala
- k
--
On Apr 10, 2013, at 10:45 PM, Vakul Garg wrote:
> The crypto node now contains a new property 'fsl,sec-era'.
> This is required so that applications can retrieve era info without
> having to be able to read SEC's register space.
>
> Signed-off-by: Vakul Garg
> ---
> Changelog:
>
> v2:
On Apr 10, 2013, at 10:43 PM, Vakul Garg wrote:
> Removing qoriq-sec4.1-0.dtsi as it is not used by any soc anymore.
>
> Signed-off-by: Vakul Garg
> ---
> arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi | 109 -
> 1 files changed, 0 insertions(+), 109 deletions(-)
>
On Apr 10, 2013, at 10:43 PM, Vakul Garg wrote:
Removing qoriq-sec4.1-0.dtsi as it is not used by any soc anymore.
Signed-off-by: Vakul Garg va...@freescale.com
---
arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi | 109 -
1 files changed, 0 insertions(+), 109
On Apr 10, 2013, at 10:45 PM, Vakul Garg wrote:
The crypto node now contains a new property 'fsl,sec-era'.
This is required so that applications can retrieve era info without
having to be able to read SEC's register space.
Signed-off-by: Vakul Garg va...@freescale.com
---
Changelog:
to a domain.
Signed-off-by: Varun Sethi varun.se...@freescale.com
---
- no change in v11.
- no change in v10.
- Added CONFIG_IOMMU_API in v9.
arch/powerpc/include/asm/device.h |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
Acked-by: Kumar Gala ga...@kernel.crashing.org
- k
On Apr 8, 2013, at 2:35 PM, Paul Bolle wrote:
> The last users of Kconfig symbol MPC10X_OPENPIC were removed in v2.6.27.
> Its Kconfig entry can be removed now.
>
> Signed-off-by: Paul Bolle
> ---
> Untested.
>
> arch/powerpc/platforms/embedded6xx/Kconfig | 5 -
> 1 file changed, 5
On Apr 8, 2013, at 2:35 PM, Paul Bolle wrote:
The last users of Kconfig symbol MPC10X_OPENPIC were removed in v2.6.27.
Its Kconfig entry can be removed now.
Signed-off-by: Paul Bolle pebo...@tiscali.nl
---
Untested.
arch/powerpc/platforms/embedded6xx/Kconfig | 5 -
1 file changed,
On Mar 18, 2013, at 6:19 PM, Ben Collins wrote:
> Somehow the driver snuck in with these still in it.
>
> Signed-off-by: Ben Collins
> ---
> arch/powerpc/platforms/85xx/sgy_cts1000.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
applied to next
- k
--
To unsubscribe from this
On Mar 18, 2013, at 6:19 PM, Ben Collins wrote:
Somehow the driver snuck in with these still in it.
Signed-off-by: Ben Collins be...@servergy.com
---
arch/powerpc/platforms/85xx/sgy_cts1000.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
applied to next
- k
--
To
On Mar 18, 2013, at 8:47 AM, Sergey Gerasimov wrote:
> Signed-off-by: Sergey Gerasimov
> ---
> arch/powerpc/boot/dts/ib8315.dts | 490 +++
> arch/powerpc/configs/83xx/ib8315_defconfig | 2121
> arch/powerpc/platforms/83xx/Kconfig|7 +
>
On Mar 18, 2013, at 9:59 AM, Kumar Gala wrote:
>
> On Mar 17, 2013, at 10:48 AM, Sethi Varun-B16395 wrote:
>
>>>>
>>>> + guts_node = of_find_compatible_node(NULL, NULL,
>>>> + "fsl,qoriq-device-config-1.0"
On Mar 17, 2013, at 10:48 AM, Sethi Varun-B16395 wrote:
>>>
>>> + guts_node = of_find_compatible_node(NULL, NULL,
>>> + "fsl,qoriq-device-config-1.0");
>>
>> This doesn't work for T4 or B4 device trees.
>>
> [Sethi Varun-B16395]hmm I need to use the dcfg space for
On Mar 18, 2013, at 8:50 AM, Sergey Gerasimov wrote:
> Signed-off-by: Sergey Gerasimov
> ---
> arch/powerpc/sysdev/fsl_pci.c | 71 +--
> 1 file changed, 34 insertions(+), 37 deletions(-)
>
Can you repost with subject and commit log fixed? It appears
On Mar 18, 2013, at 8:50 AM, Sergey Gerasimov wrote:
Signed-off-by: Sergey Gerasimov sergey.gerasi...@astrosoft-development.com
---
arch/powerpc/sysdev/fsl_pci.c | 71 +--
1 file changed, 34 insertions(+), 37 deletions(-)
Can you repost with subject
On Mar 17, 2013, at 10:48 AM, Sethi Varun-B16395 wrote:
+ guts_node = of_find_compatible_node(NULL, NULL,
+ fsl,qoriq-device-config-1.0);
This doesn't work for T4 or B4 device trees.
[Sethi Varun-B16395]hmm I need to use the dcfg space for this.
Let's see with
On Mar 18, 2013, at 9:59 AM, Kumar Gala wrote:
On Mar 17, 2013, at 10:48 AM, Sethi Varun-B16395 wrote:
+ guts_node = of_find_compatible_node(NULL, NULL,
+ fsl,qoriq-device-config-1.0);
This doesn't work for T4 or B4 device trees.
[Sethi Varun-B16395]hmm I
On Mar 18, 2013, at 8:47 AM, Sergey Gerasimov wrote:
Signed-off-by: Sergey Gerasimov sergey.gerasi...@astrosoft-development.com
---
arch/powerpc/boot/dts/ib8315.dts | 490 +++
arch/powerpc/configs/83xx/ib8315_defconfig | 2121
On Mar 14, 2013, at 10:14 AM, Paul Bolle wrote:
> The last user of Kconfig symbol 8260_PCI9 got removed in release v3.2.
> Remove this symbol too.
>
> Signed-off-by: Paul Bolle
> ---
> 0) Untested.
>
> 1) This probably is a second order effect of my commit
>
On Mar 12, 2013, at 4:49 PM, Paul Bolle wrote:
> The Kconfig entry for QE_USB contains
> default y if USB_GADGET_FSL_QE
>
> But USB_GADGET_FSL_QE got removed in commit
> 193ab2a6070039e7ee2b9b9bebea754a7c52fd1b ("usb: gadget: allow multiple
> gadgets to be built"). This default will
On Mar 12, 2013, at 4:49 PM, Paul Bolle wrote:
The Kconfig entry for QE_USB contains
default y if USB_GADGET_FSL_QE
But USB_GADGET_FSL_QE got removed in commit
193ab2a6070039e7ee2b9b9bebea754a7c52fd1b (usb: gadget: allow multiple
gadgets to be built). This default will therefor
On Mar 14, 2013, at 10:14 AM, Paul Bolle wrote:
The last user of Kconfig symbol 8260_PCI9 got removed in release v3.2.
Remove this symbol too.
Signed-off-by: Paul Bolle pebo...@tiscali.nl
---
0) Untested.
1) This probably is a second order effect of my commit
On Mar 14, 2013, at 3:20 PM, Kumar Gala wrote:
>
> On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote:
>
>> +/*
>> + * Table of SVRs and the corresponding PORT_ID values.
>> + *
>> + * All future CoreNet-enabled SOCs will have this erratum fixed, so this
On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote:
> +/*
> + * Table of SVRs and the corresponding PORT_ID values.
> + *
> + * All future CoreNet-enabled SOCs will have this erratum fixed, so this
> table
> + * should never need to be updated. SVRs are guaranteed to be unique, so
> + * there is
On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote:
+/*
+ * Table of SVRs and the corresponding PORT_ID values.
+ *
+ * All future CoreNet-enabled SOCs will have this erratum fixed, so this
table
+ * should never need to be updated. SVRs are guaranteed to be unique, so
+ * there is no worry
On Mar 14, 2013, at 3:20 PM, Kumar Gala wrote:
On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote:
+/*
+ * Table of SVRs and the corresponding PORT_ID values.
+ *
+ * All future CoreNet-enabled SOCs will have this erratum fixed, so this
table
+ * should never need to be updated. SVRs
On Jan 14, 2013, at 5:57 PM, Eric Blake wrote:
> On 01/13/2013 01:05 PM, Thomas Backlund wrote:
>> Thomas Backlund skrev 13.1.2013 20:38:
>>> patch both inline and attached as thunderbird tends to mess up ...
>>
>>> -
>>>
>>> if_bridge.h uses struct in6_addr ip6; but does not include the
On Jan 14, 2013, at 5:57 PM, Eric Blake wrote:
On 01/13/2013 01:05 PM, Thomas Backlund wrote:
Thomas Backlund skrev 13.1.2013 20:38:
patch both inline and attached as thunderbird tends to mess up ...
-
if_bridge.h uses struct in6_addr ip6; but does not include the in6.h
header.
On Feb 27, 2013, at 6:04 AM, Sethi Varun-B16395 wrote:
> Hi Kumar,Ben,
> I am implementing the Freescale PAMU (IOMMU) driver using the Linux IOMMU
> API. In this particular patch, I have added a new field to dev_archdata
> structure to store the dma domain information.
> This field is updated
On Feb 27, 2013, at 5:33 AM, Joerg Roedel wrote:
> On Mon, Feb 18, 2013 at 06:22:16PM +0530, Varun Sethi wrote:
>> Macros for checking FSL PCI controller version.
>>
>> Signed-off-by: Varun Sethi
>> ---
>> arch/powerpc/include/asm/pci-bridge.h |4
>> 1 files changed, 4 insertions(+), 0
On Feb 27, 2013, at 4:56 AM, Sethi Varun-B16395 wrote:
> This patch is present in the "next branch" of linux ppc tree maintained by
> Kumar Gala.
> Following is the commit id:
> 52c5affc545053d37c0b05224bbf70f5336caa20
>
> I am not sure if this would be part of 3
On Feb 27, 2013, at 4:56 AM, Sethi Varun-B16395 wrote:
This patch is present in the next branch of linux ppc tree maintained by
Kumar Gala.
Following is the commit id:
52c5affc545053d37c0b05224bbf70f5336caa20
I am not sure if this would be part of 3.9-rc1.
Regards
varun
This is now
On Feb 27, 2013, at 5:33 AM, Joerg Roedel wrote:
On Mon, Feb 18, 2013 at 06:22:16PM +0530, Varun Sethi wrote:
Macros for checking FSL PCI controller version.
Signed-off-by: Varun Sethi varun.se...@freescale.com
---
arch/powerpc/include/asm/pci-bridge.h |4
1 files changed, 4
On Feb 27, 2013, at 6:04 AM, Sethi Varun-B16395 wrote:
Hi Kumar,Ben,
I am implementing the Freescale PAMU (IOMMU) driver using the Linux IOMMU
API. In this particular patch, I have added a new field to dev_archdata
structure to store the dma domain information.
This field is updated
On Jan 21, 2013, at 7:02 AM, Julia Lawall wrote:
> From: Julia Lawall
>
> Delete successive tests to the same location. The code tested the result
> of a previous call, that itself was already tested. It is changed to test
> the result of the most recent call.
>
> A simplified version of
On Jan 21, 2013, at 7:02 AM, Julia Lawall wrote:
From: Julia Lawall julia.law...@lip6.fr
Delete successive tests to the same location. The code tested the result
of a previous call, that itself was already tested. It is changed to test
the result of the most recent call.
A simplified
On Dec 3, 2012, at 7:36 AM, Wei Yongjun wrote:
> From: Wei Yongjun
>
> Use for_each_compatible_node() macro instead of open coding it.
>
> Signed-off-by: Wei Yongjun
> ---
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
applied to next
On Dec 3, 2012, at 7:36 AM, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
Use for_each_compatible_node() macro instead of open coding it.
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 4 +---
1 file changed,
On Jan 4, 2013, at 12:06 PM, Cody P Schafer wrote:
> The only persistent change made by this loop is calling
> memblock_set_node() once for each memblock, which is not useful (and has
> no effect) as memblock_set_node() is not called with any
> memblock-specific parameters.
>
> Subsistute a
On Jan 4, 2013, at 12:06 PM, Cody P Schafer wrote:
The only persistent change made by this loop is calling
memblock_set_node() once for each memblock, which is not useful (and has
no effect) as memblock_set_node() is not called with any
memblock-specific parameters.
Subsistute a single
On Dec 20, 2012, at 3:08 AM, Tiejun Chen wrote:
> gdb always need to generate a single step properly to invoke
> a kgdb state. But with lazy interrupt, book3e can't always
> trigger a debug exception with a single step since the current
> is blocked for handling those pending exception, then we
On Dec 20, 2012, at 3:08 AM, Tiejun Chen wrote:
gdb always need to generate a single step properly to invoke
a kgdb state. But with lazy interrupt, book3e can't always
trigger a debug exception with a single step since the current
is blocked for handling those pending exception, then we miss
On Nov 25, 2012, at 11:33 PM, Sethi Varun-B16395 wrote:
> Hi Kumar,
> Can you please apply this patch.
>
> Regards
> Varun
Was waiting on the others to apply this all together. (ie getting an Ack from
Joerg, and follow comments from Timur to be resolved)
- k
>
>> -Original
On Nov 25, 2012, at 11:33 PM, Sethi Varun-B16395 wrote:
Hi Kumar,
Can you please apply this patch.
Regards
Varun
Was waiting on the others to apply this all together. (ie getting an Ack from
Joerg, and follow comments from Timur to be resolved)
- k
-Original Message-
From:
On Nov 21, 2012, at 3:01 AM,
wrote:
> From: Xuelin Shi
>
> The RaidEngine is a new Freescale hardware that used for parity
> computation offloading in RAID5/6.
>
> This patch adds the device node in device tree and related binding
> documentation.
>
> Signed-off-by: Harninder Rai
>
On Nov 20, 2012, at 7:54 AM, Varun Sethi wrote:
> PAMU bypass enable register added to the ccsr_guts structure.
>
> Signed-off-by: Timur Tabi
> Signed-off-by: Varun Sethi
> ---
> arch/powerpc/include/asm/fsl_guts.h |4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
applied to
On May 17, 2012, at 2:10 PM, Timur Tabi wrote:
> The MSR[GS] bit indicates whether the kernel is running in processor guest
> state mode, but such a check is unnecessary. The driver already checks
> for the /hypervisor node and the fsl,hv-version property, so it already
> knows that it's
On May 17, 2012, at 2:10 PM, Timur Tabi wrote:
The MSR[GS] bit indicates whether the kernel is running in processor guest
state mode, but such a check is unnecessary. The driver already checks
for the /hypervisor node and the fsl,hv-version property, so it already
knows that it's running
On Nov 20, 2012, at 7:54 AM, Varun Sethi wrote:
PAMU bypass enable register added to the ccsr_guts structure.
Signed-off-by: Timur Tabi ti...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h |4 +++-
1 files changed, 3
On Nov 21, 2012, at 3:01 AM, b29...@freescale.com b29...@freescale.com
wrote:
From: Xuelin Shi b29...@freescale.com
The RaidEngine is a new Freescale hardware that used for parity
computation offloading in RAID5/6.
This patch adds the device node in device tree and related binding
On Oct 4, 2012, at 6:56 AM, wrote:
> From: Varun Sethi
>
> Following is a brief description of the PAMU hardware:
> PAMU determines what action to take and whether to authorize the action on
> the basis
> of the memory address, a Logical IO Device Number (LIODN), and PAACT table
>
On Oct 4, 2012, at 6:56 AM, wrote:
> From: Varun Sethi
>
> Added the following domain attributes required by FSL PAMU driver:
> 1. Subwindows field added to the iommu domain geometry attribute.
> 2. Added new iommu stash attribute, which allows setting of the
> LIODN specific stash id
On Oct 4, 2012, at 6:56 AM, b16...@freescale.com b16...@freescale.com wrote:
From: Varun Sethi varun.se...@freescale.com
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
2. Added new iommu stash attribute,
On Oct 4, 2012, at 6:56 AM, b16...@freescale.com b16...@freescale.com wrote:
From: Varun Sethi varun.se...@freescale.com
Following is a brief description of the PAMU hardware:
PAMU determines what action to take and whether to authorize the action on
the basis
of the memory address, a
On Sep 20, 2012, at 4:46 AM, Sethi Varun-B16395 wrote:
>
>
>> -Original Message-
>> From: Wood Scott-B07421
>> Sent: Thursday, September 20, 2012 5:42 AM
>> To: Kumar Gala
>> Cc: Sethi Varun-B16395; joerg.roe...@amd.com; iommu@list
On Sep 20, 2012, at 4:46 AM, Sethi Varun-B16395 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, September 20, 2012 5:42 AM
To: Kumar Gala
Cc: Sethi Varun-B16395; joerg.roe...@amd.com; iommu@lists.linux-
foundation.org; linuxppc-...@lists.ozlabs.org; linux
On Jul 20, 2012, at 7:47 AM, Zhao Chenhui wrote:
> During suspend, all interrupts including IPI will be disabled. In this case,
> the suspend process will hang in SMP. To prevent this, pass the flag
> IRQF_NO_SUSPEND when requesting IPI irq.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li
On Sep 19, 2012, at 8:17 AM,
wrote:
> From: Varun Sethi
>
> Add a new field in the device (powerpc) archdata structure for storing iommu
> domain
> information pointer. This pointer is stored when the device is attached to a
> particular
> domain.
>
> Signed-off-by: Varun Sethi
> ---
>
On Sep 19, 2012, at 8:17 AM,
wrote:
> From: Varun Sethi
>
> Added the following domain attributes required by FSL PAMU driver:
> 1. Subwindows field added to the iommu domain geometry attribute.
> 2. Added new iommu stash attribute, which allows setting of the
> LIODN specific stash id
On Sep 19, 2012, at 8:17 AM,
wrote:
> From: Varun Sethi
>
> This patchset provides the Freescale PAMU (Peripheral Access Management Unit)
> driver
> and the corresponding IOMMU API implementation. PAMU is the IOMMU present on
> Freescale
> QorIQ platforms. PAMU can authorize memory
On Sep 19, 2012, at 8:17 AM, b16...@freescale.com b16...@freescale.com
wrote:
From: Varun Sethi varun.se...@freescale.com
This patchset provides the Freescale PAMU (Peripheral Access Management Unit)
driver
and the corresponding IOMMU API implementation. PAMU is the IOMMU present on
On Sep 19, 2012, at 8:17 AM, b16...@freescale.com b16...@freescale.com
wrote:
From: Varun Sethi varun.se...@freescale.com
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
2. Added new iommu stash
On Sep 19, 2012, at 8:17 AM, b16...@freescale.com b16...@freescale.com
wrote:
From: Varun Sethi varun.se...@freescale.com
Add a new field in the device (powerpc) archdata structure for storing iommu
domain
information pointer. This pointer is stored when the device is attached to a
On Jul 20, 2012, at 7:47 AM, Zhao Chenhui wrote:
During suspend, all interrupts including IPI will be disabled. In this case,
the suspend process will hang in SMP. To prevent this, pass the flag
IRQF_NO_SUSPEND when requesting IPI irq.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
On Aug 10, 2012, at 7:40 AM, Kumar Gala wrote:
>
> On Aug 2, 2012, at 5:04 AM, Zhao Chenhui wrote:
>
>> On Sat, Jul 28, 2012 at 08:20:31AM +1000, Benjamin Herrenschmidt wrote:
>>> On Fri, 2012-07-27 at 16:58 -0500, Kumar Gala wrote:
>>>> On Jul 20,
On Aug 10, 2012, at 7:40 AM, Kumar Gala wrote:
On Aug 2, 2012, at 5:04 AM, Zhao Chenhui wrote:
On Sat, Jul 28, 2012 at 08:20:31AM +1000, Benjamin Herrenschmidt wrote:
On Fri, 2012-07-27 at 16:58 -0500, Kumar Gala wrote:
On Jul 20, 2012, at 7:47 AM, Zhao Chenhui wrote:
During suspend
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