: Ashok Raj
Reviewed-by: Tony Luck
Reviewed-by: Ilpo Järvinen
Reviewed-by: Steven Rostedt (Google)
Signed-off-by: Jithu Joseph
Signed-off-by: Kuppuswamy Sathyanarayanan
---
include/trace/events/intel_ifs.h | 27
drivers/platform/x86/intel/ifs/runtest.c | 1
: Kuppuswamy Sathyanarayanan
---
Changes since v3:
* None
Changes since v2:
* Removed unnecessary parenthesis for 2 * HZ.
* Changed "Non valid" to Non-valid.
* Use simplified confition for sbaf_bundle_completed().
drivers/platform/x86/intel/ifs/ifs.h | 30 +++
drivers/platform
: Jithu Joseph
Co-developed-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Kuppuswamy Sathyanarayanan
---
Changes since v3:
* Added missing error return in validate_ifs_metadata().
arch/x86/include/asm/msr-index.h | 2 ++
drivers/platform/x86/intel/ifs/ifs.h | 37
This is a preliminary patch in preparation for the addition of SBAF
support.
Reviewed-by: Ashok Raj
Reviewed-by: Tony Luck
Reviewed-by: Ilpo Järvinen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
drivers/platform/x86/intel/ifs/ifs.h | 25 +
drivers/platform/x86/intel/ifs/c
support
trace: platform/x86/intel/ifs: Add SBAF trace support
Kuppuswamy Sathyanarayanan (1):
platform/x86/intel/ifs: Refactor MSR usage in IFS test code
arch/x86/include/asm/msr-index.h | 2 +
drivers/platform/x86/intel/ifs/ifs.h | 92 -
include/trace/events/intel_ifs.h
Rearrange the ifs_status trace struct members to eliminate a 4-byte
alignment hole. It reduces memory overhead.
Suggested-by: Steven Rostedt (Google)
Reviewed-by: Jithu Joseph
Reviewed-by: Ashok Raj
Signed-off-by: Kuppuswamy Sathyanarayanan
---
include/trace/events/intel_ifs.h | 2 +-
1
: Ashok Raj
Reviewed-by: Tony Luck
Reviewed-by: Ilpo Järvinen
Reviewed-by: Steven Rostedt (Google)
Signed-off-by: Jithu Joseph
Signed-off-by: Kuppuswamy Sathyanarayanan
---
include/trace/events/intel_ifs.h | 27
drivers/platform/x86/intel/ifs/runtest.c | 1
: Kuppuswamy Sathyanarayanan
---
Changes since v2:
* Removed unnecessary parenthesis for 2 * HZ.
* Changed "Non valid" to Non-valid.
* Use simplified confition for sbaf_bundle_completed().
drivers/platform/x86/intel/ifs/ifs.h | 30 +++
drivers/platform/x86/intel/ifs/runte
: Jithu Joseph
Co-developed-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/include/asm/msr-index.h | 2 ++
drivers/platform/x86/intel/ifs/ifs.h | 37 ++-
drivers/platform/x86/intel/ifs/core.c | 24 +
drivers
This is a preliminary patch in preparation for the addition of SBAF
support.
Reviewed-by: Ashok Raj
Reviewed-by: Tony Luck
Reviewed-by: Ilpo Järvinen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
drivers/platform/x86/intel/ifs/ifs.h | 25 +
drivers/platform/x86/intel/ifs/c
)
* Fixed initialization issue in ifs_sbaf_test_core() (Ilpo)
Jithu Joseph (3):
platform/x86/intel/ifs: Add SBAF test image loading support
platform/x86/intel/ifs: Add SBAF test support
trace: platform/x86/intel/ifs: Add SBAF trace support
Kuppuswamy Sathyanarayanan (1):
platform/x86/intel
On 4/20/21 4:53 PM, Dan Williams wrote:
On Tue, Apr 20, 2021 at 4:12 PM Kuppuswamy, Sathyanarayanan
wrote:
[..]
Also, do you *REALLY* need to do this from assembly? Can't it be done
in the C wrapper?
Its common for all use cases of TDVMCALL (vendor specific, in/out, etc).
so added
it
On 4/20/21 12:59 PM, Dave Hansen wrote:
On 4/20/21 12:20 PM, Kuppuswamy, Sathyanarayanan wrote:
approach is, it adds a few extra instructions for every
TDCALL use case when compared to distributed checks. Although
it's a bit less efficient, it's worth it to make the code mor
On 4/20/21 10:36 AM, Dave Hansen wrote:
On 3/26/21 4:38 PM, Kuppuswamy Sathyanarayanan wrote:
Implement common helper functions to communicate with
the TDX Module and VMM (using TDCALL instruction).
This is missing any kind of background. I'd say:
Guests communicate with VMMs
On 4/1/21 2:19 PM, Dave Hansen wrote:
On 4/1/21 2:15 PM, Kuppuswamy, Sathyanarayanan wrote:
On 4/1/21 2:08 PM, Dave Hansen wrote:
On 2/5/21 3:38 PM, Kuppuswamy Sathyanarayanan wrote:
+bool is_tdx_guest(void)
+{
+ return static_cpu_has(X86_FEATURE_TDX_GUEST);
+}
Why do you need
On 4/1/21 2:08 PM, Dave Hansen wrote:
On 2/5/21 3:38 PM, Kuppuswamy Sathyanarayanan wrote:
+bool is_tdx_guest(void)
+{
+ return static_cpu_has(X86_FEATURE_TDX_GUEST);
+}
Why do you need is_tdx_guest() as opposed to calling
cpu_feature_enabled(X86_FEATURE_TDX_GUEST) everywhere
TD.
After the above mentioned preventive measures, if TD guests still
execute these instructions, add appropriate warning messages in #VE
handler.
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
Changes since v4:
* Fixed commit log and comments as per Dave's com
On 3/31/21 2:49 PM, Dave Hansen wrote:
On 3/31/21 2:09 PM, Kuppuswamy Sathyanarayanan wrote:
As per Guest-Host Communication Interface (GHCI) Specification
for Intel TDX, sec 2.4.1, TDX architecture does not support
MWAIT, MONITOR and WBINVD instructions. So in non-root TDX mode,
if MWAIT
On 3/31/21 3:11 PM, Dave Hansen wrote:
On 3/31/21 3:06 PM, Sean Christopherson wrote:
I've no objection to a nice message in the #VE handler. What I'm objecting to
is sanity checking the CPUID model provided by the TDX module. If we don't
trust the TDX module to honor the spec, then there a
Hi All,
On 2/5/21 3:38 PM, Kuppuswamy Sathyanarayanan wrote:
Hi All,
NOTE: This series is not ready for wide public review. It is being
specifically posted so that Peter Z and other experts on the entry
code can look for problems with the new exception handler (#VE).
That's also why x8
this instruction and disable them for TD.
After the above mentioned preventive measures, if TD guest still
execute these instructions, add appropriate warning messages in #VE
handler.
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
Changes since v3:
* WARN user if SEAM
On 3/30/21 8:10 AM, Dave Hansen wrote:
On 3/30/21 8:00 AM, Andi Kleen wrote:
+ /* MWAIT is not supported in TDX platform, so suppress it */
+ setup_clear_cpu_cap(X86_FEATURE_MWAIT);
In fact, MWAIT bit returned by CPUID instruction is zero for TD guest. This
is enforced by SEAM mo
On 3/29/21 4:23 PM, Andy Lutomirski wrote:
On Mar 29, 2021, at 4:17 PM, Kuppuswamy Sathyanarayanan
wrote:
In non-root TDX guest mode, MWAIT, MONITOR and WBINVD instructions
are not supported. So handle #VE due to these instructions
appropriately.
Is there something I missed elsewhere
-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
Changes since v2:
* Added BUG() for WBINVD, WARN for MONITOR instructions.
* Fixed comments as per Dave's review.
Changes since v1:
* Added WARN() for MWAIT #VE exception.
Changes since previous series:
* Suppressed MWAIT featu
On 3/29/21 3:12 PM, Dave Hansen wrote:
On 3/29/21 3:09 PM, Kuppuswamy, Sathyanarayanan wrote:
+ case EXIT_REASON_MWAIT_INSTRUCTION:
+ /* MWAIT is supressed, not supposed to reach here. */
+ WARN(1, "MWAIT unexpected #VE Exception\n");
+ return -EFAULT;
Ho
On 3/29/21 3:02 PM, Dave Hansen wrote:
On 3/29/21 2:55 PM, Kuppuswamy, Sathyanarayanan wrote:
MONITOR is a privileged instruction, right? So we can only end up in
here if the kernel screws up and isn't reading CPUID correctly, right?
That dosen't seem to me like something
On 3/29/21 10:14 AM, Dave Hansen wrote:
On 3/27/21 3:54 PM, Kuppuswamy Sathyanarayanan wrote:
+ /*
+* Per Guest-Host-Communication Interface (GHCI) for Intel Trust
+* Domain Extensions (Intel TDX) specification, sec 2.4,
+* some instructions that unconditionally
On 3/16/21 9:13 PM, Lukas Wunner wrote:
On Fri, Mar 12, 2021 at 07:32:08PM -0800,
sathyanarayanan.kuppusw...@linux.intel.com wrote:
+ if ((events == PCI_EXP_SLTSTA_DLLSC) && is_dpc_reset_active(pdev)) {
+ ctrl_info(ctrl, "Slot(%s): DLLSC event(DPC), skipped\n",
+
In non-root TDX guest mode, MWAIT, MONITOR and WBINVD instructions
are not supported. So handle #VE due to these instructions as no ops.
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
Changes since v1:
* Added WARN() for MWAIT #VE exception.
Changes since previous
On 3/26/21 7:40 PM, Andy Lutomirski wrote:
On Mar 26, 2021, at 5:18 PM, Kuppuswamy Sathyanarayanan
wrote:
In non-root TDX guest mode, MWAIT, MONITOR and WBINVD instructions
are not supported. So handle #VE due to these instructions as no ops.
These should at least be WARN.
I will
In non-root TDX guest mode, MWAIT, MONITOR and WBINVD instructions
are not supported. So handle #VE due to these instructions as no ops.
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
Changes since previous series:
* Suppressed MWAIT feature as per Andi's co
code more
readable.
Originally-by: Sean Christopherson
Signed-off-by: Kuppuswamy Sathyanarayanan
---
Hi All,
Please let me know your review comments. If you agree with this patch
and want to see the use of these APIs in rest of the patches, I will
re-send the patch series with updated code. Ple
On 3/19/21 11:22 AM, Dave Hansen wrote:
On 3/19/21 10:42 AM, Kuppuswamy, Sathyanarayanan wrote:
@@ -4,6 +4,58 @@
#include
#include
+void tdcall(u64 leafid, struct tdcall_regs *regs)
+{
+ asm volatile(
+ /* RAX = leafid (TDCALL LEAF ID) */
+ " mo
Hi Sean,
Thanks for the review.
On 3/19/21 9:55 AM, Sean Christopherson wrote:
On Thu, Mar 18, 2021, Kuppuswamy Sathyanarayanan wrote:
diff --git a/arch/x86/kernel/tdx.c b/arch/x86/kernel/tdx.c
index e44e55d1e519..7ae1d25e272b 100644
--- a/arch/x86/kernel/tdx.c
+++ b/arch/x86/kernel/tdx.c
code more
readable.
Signed-off-by: Kuppuswamy Sathyanarayanan
---
Hi All,
As you have suggested, I have created common helper functions
for all tdcall() and tdvmcall() use cases. It uses inline
assembly and passes GPRs R8-15 and r[a-c]x registers to TDX
Module/VMM. Please take a look at it and l
Hi Bjorn,
On 1/22/21 5:11 PM, Kuppuswamy Sathyanarayanan wrote:
Currently, PCIe capabilities ownership status is detected by
verifying the status of pcie_ports_native, and _OSC negotiated
results (cached in struct pci_host_bridge->native_* members).
But this logic can be simplified, and we
On 3/17/21 12:01 PM, Lukas Wunner wrote:
On Wed, Mar 17, 2021 at 10:54:09AM -0700, Sathyanarayanan Kuppuswamy Natarajan
wrote:
Flush of hotplug event after successful recovery, and a simulated
hotplug link down event after link recovery fails should solve the
problems raised by Lukas. I assu
On 3/12/21 7:32 PM, sathyanarayanan.kuppusw...@linux.intel.com wrote:
From: Kuppuswamy Sathyanarayanan
When hotplug and DPC are both enabled on a Root port or
Downstream Port, during DPC events that cause a DLLSC link
down/up events, such events (DLLSC) must be suppressed to
let the DPC
On 3/12/21 3:14 PM, Bjorn Helgaas wrote:
On Fri, Mar 12, 2021 at 02:11:03PM -0800, Kuppuswamy, Sathyanarayanan wrote:
On 3/12/21 1:33 PM, Bjorn Helgaas wrote:
On Mon, Mar 08, 2021 at 10:34:10PM -0800,
sathyanarayanan.kuppusw...@linux.intel.com wrote:
From: Kuppuswamy Sathyanarayanan
On 3/12/21 1:33 PM, Bjorn Helgaas wrote:
[+cc Lukas, pciehp expert]
On Mon, Mar 08, 2021 at 10:34:10PM -0800,
sathyanarayanan.kuppusw...@linux.intel.com wrote:
From: Kuppuswamy Sathyanarayanan
When hotplug and DPC are both enabled on a Root port or
Downstream Port, during DPC events that
n future reviews.
Reviewed-by: Kuppuswamy Sathyanarayanan
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
On 2/25/21 6:37 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
Compile-testing these drivers is currently broken. Enabling
it causes a couple of build failures though:
drivers/pci/controller/pci-thunder-ecam.c:119:30: error: shift count >= width
of type [-Werror,-Wshift-count-overflow]
drive
On 2/8/21 2:00 AM, Peter Zijlstra wrote:
This needs a binutils version number.
Yes, we will add it in next version.
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
On 2/8/21 8:59 AM, Peter Zijlstra wrote:
'cute', might be useful to have that mentioned somewhere.
we will add a note for it in comments.
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
entry as the existing storage
for the pointer occupies the zero entry in the GDT itself.
Reported-by: Kai Huang
Signed-off-by: Sean Christopherson
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/include/asm/realmode.h | 1 +
arch/x86/kernel/smpboot.c
ean Christopherson
Signed-off-by: Sean Christopherson
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
arch/x86/include/asm/apic.h | 3 ++
arch/x86/kernel/acpi/boot.c | 56 +
arch/x86/kernel/apic/probe_32.c | 8 +
arch/x86/kernel/a
In non-root TDX guest mode, MWAIT, MONITOR and WBINVD instructions
are not supported. So handle #VE due to these instructions as no ops.
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
arch/x86/kernel/tdx.c | 17 +
1 file changed, 17 insertions(+)
diff
Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/kernel/tdx.c | 120 ++
1 file changed, 120 insertions(+)
diff --git a/arch/x86/kernel/tdx.c b/arch/x86/kernel/tdx.c
index 3846d2807a7a..eff58329751e 100644
--- a/arch/x86/kernel/tdx.c
+++ b/arch/
esion code cannot deal with alternatives: use branches
instead to implement inX() and outX() helpers.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/boot/compressed/Makefile | 1 +
arch/x86/boot/compressed/tdx_io.S |
From: "Kirill A. Shutemov"
The patch allows to override the implementation of the port IO
helpers. TDX code will provide an implementation that redirect the
helpers to paravirt calls.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathy
hypervisor specific CPUIDs unknown to the native CPU.
Therefore there is no risk of causing this in early CPUID code which
runs before the #VE handler is set up because it will never access
those exotic CPUID leaves.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by:
ned-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/kernel/tdx.c | 94 ++-
1 file changed, 93 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/tdx.c b/arch/x86/kernel/tdx.c
index bb
From: "Kirill A. Shutemov"
KVM hypercalls have to be wrapped into vendor-specific TDVMCALLs.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/include/asm/kvm_para.h | 21 ++
arch/x86/include/asm/tdx.h | 8
is used to handle #VE exception due to
EXIT_REASON_HLT.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/include/asm/tdx.h | 5
arch/x86/kernel/tdx.c | 61 ++
2 files changed, 60 insert
: Kuppuswamy Sathyanarayanan
---
arch/x86/boot/compressed/head_64.S | 5 -
arch/x86/kernel/head_64.S | 13 +++--
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/x86/boot/compressed/head_64.S
b/arch/x86/boot/compressed/head_64.S
index 37c2f37d4a0d
dden under CONFIG_PARAVIRT_XXL, but the rest of the
config would be a bloat for TDX.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/Kconfig | 4 +++
arch/x86/boot/compressed/misc.h | 1 +
arch/x86/include/asm/
Add helper function to detect TDX feature support. It will be used
to protect TDX specific code.
Co-developed-by: Sean Christopherson
Signed-off-by: Sean Christopherson
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/boot/compressed/Makefile | 1 +
arch/x86
rolled by the TDX module
which guarantees no EPT violations will result in #VE for the guest,
once the memory has been accepted.
Co-developed-by: Sean Christopherson
Signed-off-by: Sean Christopherson
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayan
v
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/include/asm/tdx.h | 9 +
arch/x86/kernel/tdx.c | 27 +++
2 files changed, 36 insertions(+)
diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h
index 0b9d571b1f95.
: 0
EBX/EDX/ECX: Vendor string:
EBX = “Inte”
EDX = ”lTDX”
ECX = ““
So when above condition is true, set X86_FEATURE_TDX_GUEST
feature cap bit
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/tdx.h
ess to the operation.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/include/asm/tdx.h | 2 ++
arch/x86/kernel/tdx.c | 28
2 files changed, 30 insertions(+)
diff --git a/arch/x86/include/asm/tdx.h
Hi Andy,
On 2/5/21 3:43 PM, Andy Lutomirski wrote:
MWAIT turning into NOP is no good. How about suppressing
X86_FEATURE_MWAIT instead?
Yes, we can suppress it in tdx_early_init().
+ setup_clear_cpu_cap(X86_FEATURE_MWAIT);
But do you want to leave the MWAIT #VE handler as it as
(just in case
plicitly
accepted by the
BUG() if TDACCEPTPAGE fails (except the above case), as the guest is
completely hosed if it can't access memory.
Tested-by: Kai Huang
Signed-off-by: Kirill A. Shutemov
Signed-off-by: Sean Christopherson
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathya
From: "Kirill A. Shutemov"
All ioremap()ed paged that are not backed by normal memory (NONE or
RESERVED) have to be mapped as shared.
Reuse the infrastructure we have for AMD SEV.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/kernel/pci-swiotlb.c| 2 +-
arch/x86/kernel/tdx.c| 3 +++
arch/x86/mm/mem_encrypt.c| 44 ---
arch/x86/mm/mem_encrypt_common.c | 45
4 fi
viewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/Kconfig | 8 +--
arch/x86/include/asm/io.h| 4 +++-
arch/x86/mm/Makefile | 2 ++
arch/x86/mm/mem_encrypt.c| 30 -
arch/x86/mm/mem_encryp
From: "Kirill A. Shutemov"
tdx_shared_mask() returns the mask that has to be set in page table
entry to make page shared with VMM.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/Kconfig | 1 +
arch/x86/i
Add INTEL_TDX_GUEST config option to selectively compile
TDX guest support.
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
arch/x86/Kconfig | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 8fe91114bfee
dynamic CPU
online/offline feature. So current generation of TDVF does not
support CPU hotplug feature. It may be supported in next generation.
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Andi Kleen
---
arch/x86/kernel/tdx.c | 14 ++
arch/x86/kernel/topology.c | 3
-by: Sean Christopherson
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/kernel/tdx.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/kernel/tdx.c b/arch/x86/kernel/tdx.c
index a36b6ae14942..ae37498df981 100644
--- a/arch/x86/kernel/tdx.c
+++ b/arch
mode.
Signed-off-by: Sean Christopherson
Reviewed-by: Andi Kleen
Signed-off-by: Kuppuswamy Sathyanarayanan
---
arch/x86/boot/compressed/head_64.S | 5 +++--
arch/x86/boot/compressed/pgtable.h | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/x86/boot/compressed/head_64
;native_X and we don't have to sprinkle tests of
pcie_ports_native everywhere.
[bhelgaas: commit log, rework OSC_PCI_EXPRESS_CONTROL_MASKS, logging]
Link:
https://lore.kernel.org/r/bc87c9e675118960949043a832bed86bc22becbd.1603766889.git.sathyanarayanan.kuppusw...@linux.intel.com
Signed-
From: Bjorn Helgaas
Downstream Ports may support DPC regardless of whether they support AER
(see PCIe r5.0, sec 6.2.10.2). Previously, if the user booted with
"pcie_ports=dpc-native", it was possible for dpc_probe() to succeed even if
the device had no AER Capability, but dpc_get_aer_uncorrect_s
on top of v5.8-rc1
Changes since v4:
* Changed the patch set title (Original link:
https://lkml.org/lkml/2020/5/26/1710)
* Added AER/DPC dependency logic cleanup fixes.
Bjorn Helgaas (2):
PCI/DPC: Ignore devices with no AER Capability
PCI/ACPI: Centralize pci_aer_available() checking
Kuppusw
Add OSC_OWNER() helper to prettify checking the _OSC control bits to learn
whether the platform has granted us control of PCI features. No functional
change intended.
[bhelgaas: split to separate patch, commit log]
Signed-off-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Bjorn Helgaas
From: Bjorn Helgaas
Check pci_aer_available() in acpi_pci_root_create() when we're interpreting
_OSC results so host_bridge->native_aer becomes the single way to determine
whether we control AER capabilities.
Signed-off-by: Bjorn Helgaas
---
drivers/acpi/pci_root.c | 3 +++
drivers/pci
,
tells us otherwise.
[bhelgaas: commit log]
Link:
https://lore.kernel.org/r/fcbe8a624166a1101a755edfef44a185d32ff493.1603766889.git.sathyanarayanan.kuppusw...@linux.intel.com
Signed-off-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Bjorn Helgaas
---
drivers/pci/probe.c | 6 --
1 file
On 1/8/21 2:30 PM, Bjorn Helgaas wrote:
Can we push this forward now? There are several pending patches in
this area from Keith and Sathyanarayanan; I haven't gotten to them
yet, so not sure whether they help address any of this.
Following two patches should also address the same issue.
My
ntroduce the "remove
affected device + rescan" functionality in fatal error recovery handler.
Also holding pci_lock_rescan_remove() will prevent the race between hotplug
and DPC handler.
Fixes: bdb5ac85777d ("PCI/ERR: Handle fatal error recovery")
Signed-off-by: Kuppuswamy Sathy
via report_slot_reset() without doing the actual device
reset is incorrect. So call pci_bus_reset() before triggering
->slot_reset() callback.
Signed-off-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Sinan Kaya
Reviewed-by: Ashok Raj
---
Changes since v7:
* Rebased on top of v5.11-
On 12/14/20 3:37 PM, Bjorn Helgaas wrote:
On Mon, Dec 14, 2020 at 06:18:54PM -0500, Alex Deucher wrote:
On Mon, Dec 14, 2020 at 6:16 PM Bjorn Helgaas wrote:
On Tue, Dec 15, 2020 at 07:34:31AM +1100, Stephen Rothwell wrote:
Hi all,
On Tue, 8 Dec 2020 13:56:20 +1100 Stephen Rothwell
wrote
On 10/26/20 12:37 PM, Kuppuswamy Sathyanarayanan wrote:
Currently if report_error_detected() or report_mmio_enabled()
functions requests PCI_ERS_RESULT_NEED_RESET, current
pcie_do_recovery() implementation does not do the requested
explicit device reset, but instead just calls the
Hi Bjorn,
On 11/30/20 5:11 PM, Kuppuswamy, Sathyanarayanan wrote:
Hi Bjorn,
On 11/25/20 7:48 PM, Kuppuswamy, Sathyanarayanan wrote:
Along with above patch, you also left following two cleanup patches. Is this
intentional? Following fixes have no dependency on pcie_ports_dpc_native change
Hi,
On 12/7/20 5:08 AM, Paul Menzel wrote:
[Bringing the issue up on the list in case the Linux Bugzilla is not
monitored/used.]
Dear Linux folks,
On Intel Tiger Lake Dell laptop, Linux logs the error below [1].
[ 0.507307] pci :00:07.0: DPC: RP PIO log size 0 is invalid
[
Hi Bjorn,
On 11/25/20 7:48 PM, Kuppuswamy, Sathyanarayanan wrote:
Along with above patch, you also left following two cleanup patches. Is this
intentional? Following fixes have no dependency on pcie_ports_dpc_native change.
[PATCH v11 4/5] PCI/portdrv: Remove redundant pci_aer_available
On 11/30/20 4:25 PM, Bjorn Helgaas wrote:
I think EDR is the same as DPC?
Yes, EDR is same as DPC.
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
On 11/28/20 3:25 PM, Bjorn Helgaas wrote:
On Sat, Nov 28, 2020 at 01:56:23PM -0800, Kuppuswamy, Sathyanarayanan wrote:
On 11/28/20 1:53 PM, Bjorn Helgaas wrote:
On Sat, Nov 28, 2020 at 01:49:46PM -0800, Kuppuswamy, Sathyanarayanan wrote:
On 11/28/20 12:24 PM, Bjorn Helgaas wrote:
On Wed
On 11/28/20 12:24 PM, Bjorn Helgaas wrote:
On Wed, Nov 25, 2020 at 06:01:57PM -0800, Kuppuswamy, Sathyanarayanan wrote:
On 11/25/20 5:18 PM, Bjorn Helgaas wrote:
From: Bjorn Helgaas
Downstream Ports may support DPC regardless of whether they support AER
(see PCIe r5.0, sec 6.2.10.2
On 11/28/20 1:53 PM, Bjorn Helgaas wrote:
On Sat, Nov 28, 2020 at 01:49:46PM -0800, Kuppuswamy, Sathyanarayanan wrote:
On 11/28/20 12:24 PM, Bjorn Helgaas wrote:
On Wed, Nov 25, 2020 at 06:01:57PM -0800, Kuppuswamy, Sathyanarayanan wrote:
On 11/25/20 5:18 PM, Bjorn Helgaas wrote:
From
* Temporarily drop pcie_ports_dpc_native changes
v11 posting:
https://lore.kernel.org/r/cover.1603766889.git.sathyanarayanan.kuppusw...@linux.intel.com
Bjorn Helgaas (2):
PCI/DPC: Ignore devices with no AER Capability
PCI/ACPI: Centralize pci_aer_available() checking
Kuppuswamy Sat
On 11/25/20 5:18 PM, Bjorn Helgaas wrote:
From: Kuppuswamy Sathyanarayanan
If the user booted with "pcie_ports=native", we take control of the PCIe
features unconditionally, regardless of what _OSC says.
Centralize the testing of pcie_ports_native in acpi_pci_root_create()
On 11/25/20 5:18 PM, Bjorn Helgaas wrote:
From: Bjorn Helgaas
Downstream Ports may support DPC regardless of whether they support AER
(see PCIe r5.0, sec 6.2.10.2). Previously, if the user booted with
"pcie_ports=dpc-native", it was possible for dpc_probe() to succeed even if
the device had
On 11/25/20 12:28 PM, Bjorn Helgaas wrote:
On Mon, Oct 26, 2020 at 07:57:05PM -0700, Kuppuswamy Sathyanarayanan wrote:
pcie_ports_native is set only if user requests native handling
of PCIe capabilities via pcie_port_setup command line option.
User input takes precedence over _OSC based
On 11/25/20 2:25 PM, Bjorn Helgaas wrote:
I've been fiddling with this, so let me post a v12 tonight and you can
see what you think.
Ok. I will wait for your update.
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
Hi Bjorn,
Thanks for the review.
On 11/25/20 12:12 PM, Bjorn Helgaas wrote:
On Mon, Oct 26, 2020 at 07:57:05PM -0700, Kuppuswamy Sathyanarayanan wrote:
pcie_ports_native is set only if user requests native handling
of PCIe capabilities via pcie_port_setup command line option.
User input takes
Hi Guilherme,
On 11/24/20 10:45 AM, Guilherme G. Piccoli wrote:
Hi Kuppuswamy Sathyanarayanan (and all involved here), thanks for the
patch! I'd like to ask what is the status of this patchset - I just
"parachuted" in the issue, and by tracking the linux-pci ML, I found
t
Hi,
On 11/19/20 2:08 PM, Raj, Ashok wrote:
If an Attention Button is present, the current behavior is to bring up
the hotplug slot as soon as presence or link is detected. We don't wait
for a button press. This is intended as a convience feature to bring up
slots as quickly as possible, but th
respective RCiEPs.
Extend the existing ability to link the RCECs with a walking function
pcie_walk_rcec(). Add RCEC support to the current AER service driver and
attach the AER service driver to the RCEC device.
Reviewed-by: Kuppuswamy Sathyanarayanan
[bhelgaas: kernel doc, whitespace cleanup]
Co
On 11/17/20 11:19 AM, Sean V Kelley wrote:
Root Complex Event Collectors (RCEC) appear as peers of Root Ports and also
have the PME capability. As with AER, there is a need to be able to walk
the RCiEPs associated with their RCEC for purposes of acting upon them with
callbacks.
Add RCEC suppo
On 11/17/20 11:19 AM, Sean V Kelley wrote:
From: Qiuxu Zhuo
Root Complex Event Collectors (RCEC) appear as peers to Root Ports and may
also have the AER capability.
Add RCEC support to the AER error injection driver.
Reviewed-by: Kuppuswamy Sathyanarayanan
Co-developed-by: Sean V
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