On Wed, 2019-10-16 at 02:40 -0700, Ooi, Joyce wrote:
> This patch adds QSPI flash interface in device tree for Intel Agilex
>
> Signed-off-by: Ooi, Joyce
> ---
> v2: update the qspi_rootfs partition size
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 35
> ++
>
de uses strncpy() when copying
> boot_command_line.
>
> Use strlcpy() instead.
>
> This issue is identified by a Coccinelle script.
>
> Signed-off-by: Wang Xiayang
Merged to v5.4-rc1. Thanks.
Acked-by: Ley Foon Tan
> ---
> arch/nios2/kernel/setup.c | 6 +++--
Hi Linus
Please pull the arch/nios2 update below.
Thanks.
Regards
Ley Foon
The following changes since commit 4d856f72c10ecb060868ed10ff1b1453943fc6c8:
Linux 5.3 (2019-09-15 14:19:32 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2
re [2]. In the Kconfig syntax, the first one
> > is effective. So, TRACE_IRQFLAGS_SUPPORT is always 'n'.
> >
> > The second define in arch/nios2/Kconfig.debug is dead code.
> >
> > Signed-off-by: Masahiro Yamada
> > ---
> Ping.
>
>
Acked-by: Ley F
targeting
the immediate device on the link.
The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.
Signed-off-by: Ley Foon Tan
---
v2:
- Add get_tlp_header() function.
---
drivers/pci
On Thu, May 30, 2019 at 11:25 PM Lorenzo Pieralisi
wrote:
>
> On Fri, May 24, 2019 at 02:07:25PM +0800, Ley Foon Tan wrote:
> > This fix issue when access config from PCIe switch.
> >
> > Stratix 10 PCIe controller does not support Type 1 to Type 0 conversion
> >
On Tue, Jun 4, 2019 at 9:18 PM Bjorn Helgaas wrote:
>
> On Wed, Apr 24, 2019 at 12:57:14PM +0800, Ley Foon Tan wrote:
> > Altera PCIe Rootport IP is a soft IP and is only available after
> > FPGA image is programmed.
> >
> > Make driver modulable to support use
No longer need cfgrdX and cfgwrX since we have separate defines for
TLP_CFG*_DW0 and S10_TLP_CFG*_DW0, so remove them.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 33 +++-
1 file changed, 8 insertions(+), 25 deletions(-)
diff --git a/drivers
targeting
the immediate device on the link.
The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.
Ley Foon Tan (2):
PCI: altera: Fix configuration type based on secondary number
PCI
targeting
the immediate device on the link.
The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 22
On Fri, May 24, 2019 at 10:15 AM Ley Foon Tan wrote:
>
> Fix compilation warning caused by patch "PCI: altera: Allow building as
> module".
>
> drivers/pci/controller/pcie-altera.c: In function ‘altera_pcie_irq_teardown’:
> drivers/pci/controller/pcie-altera.c:723:1:
ned-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 6c86bc69ace8..27222071ace7 100644
--- a/drivers/pci/controller/pcie-altera.c
+++
On Wed, May 15, 2019 at 9:59 PM Lorenzo Pieralisi
wrote:
>
> On Tue, May 14, 2019 at 01:35:20PM +0800, Ley Foon Tan wrote:
> > On Wed, Apr 24, 2019 at 12:57 PM Ley Foon Tan
> > wrote:
> > >
> > > Altera MSI IP is a soft IP and is only available
On Wed, Apr 24, 2019 at 12:57 PM Ley Foon Tan wrote:
>
> Altera MSI IP is a soft IP and is only available after
> FPGA image is programmed.
>
> Make driver modulable to support use case FPGA image is programmed
> after kernel is booted. User proram FPGA image in kernel then only
On Wed, Apr 24, 2019 at 12:57 PM Ley Foon Tan wrote:
>
> Altera PCIe Rootport IP is a soft IP and is only available after
> FPGA image is programmed.
>
> Make driver modulable to support use case FPGA image is programmed
> after kernel is booted. User proram FPGA image in ker
Altera MSI IP is a soft IP and is only available after
FPGA image is programmed.
Make driver modulable to support use case FPGA image is programmed
after kernel is booted. User proram FPGA image in kernel then only load
MSI driver module.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller
Altera PCIe Rootport IP is a soft IP and is only available after
FPGA image is programmed.
Make driver modulable to support use case FPGA image is programmed
after kernel is booted. User proram FPGA image in kernel then only load
PCIe driver module.
Signed-off-by: Ley Foon Tan
---
drivers/pci
Hi Linus
Please pull the arch/nios2 updates below.
Most of updates are MMU related.
Thanks.
Regards
Ley Foon
The following changes since commit 1c163f4c7b3f621efff9b28a47abb36f7378d783:
Linux 5.0 (2019-03-03 15:21:29 -0800)
are available in the git repository at:
git://git.kernel.org/pub
On Fri, 2019-03-01 at 14:15 +, Lorenzo Pieralisi wrote:
> On Fri, Mar 01, 2019 at 08:50:48AM +0800, Ley Foon Tan wrote:
> >
> > On Thu, 2019-02-28 at 10:56 +, Lorenzo Pieralisi wrote:
> > >
> > > On Thu, Feb 28, 2019 at 06:
o extend the generic
> ptrace API with PTRACE_GET_SYSCALL_INFO request.
>
> Acked-by: Paul Moore
> Cc: Elvira Khabirova
> Cc: Eugene Syromyatnikov
> Cc: Ley Foon Tan
> Cc: Oleg Nesterov
> Cc: Andy Lutomirski
> Cc: nios2-...@lists.rocketboards.org
> Cc: linux-
On Thu, 2019-02-28 at 10:56 +, Lorenzo Pieralisi wrote:
> On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote:
>
> [...]
>
> >
> > +static int s10_tlp_read_packet(struct altera_pcie *pcie, u32
> > *value)
> > +{
> > + int i;
> > +
Add support for altr,pcie-root-port-2.0.
Signed-off-by: Ley Foon Tan
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/altera-pcie.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt
b/Documentation
Enable PCIE_ALTERA on ARM64 platform.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 6671946dbf66..6012f3059acd 100644
--- a/drivers/pci
: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 264 ---
1 file changed, 240 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 7d05e51205b3..c57fd7f4e848 100644
--- a/drivers/pci/controller
2019/1/2/16
[v4]: https://lkml.org/lkml/2019/2/14/58
[v5]: https://lkml.org/lkml/2019/2/26/200
Ley Foon Tan (3):
PCI: altera: Add Stratix 10 PCIe support
PCI: altera: Enable driver on ARM64
dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0
.../devicetree/bindings/pci/altera-pcie.txt | 4
On Wed, 2019-02-27 at 17:38 +, Lorenzo Pieralisi wrote:
> On Tue, Feb 26, 2019 at 05:15:46PM +0800, Ley Foon Tan wrote:
> >
> > Add PCIe Root Port support for Stratix 10 device.
> >
> > Main differences compare with PCIe Root Port IP on Cyclone V
> > and
Enable PCIE_ALTERA on ARM64 platform.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 6671946dbf66..6012f3059acd 100644
--- a/drivers/pci
StratixXX to stratix10.
History:
[v1]: https://lkml.org/lkml/2018/12/26/68
[v2]: https://lkml.org/lkml/2018/12/31/46
[v3]: https://lkml.org/lkml/2019/1/2/16
[v4]: https://lkml.org/lkml/2019/2/14/58
Ley Foon Tan (3):
PCI: altera: Add Stratix 10 PCIe support
PCI: altera: Enable driver o
: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 266 ---
1 file changed, 242 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 7d05e51205b3..b3c05f2f309b 100644
--- a/drivers/pci/controller
Add support for altr,pcie-root-port-2.0.
Signed-off-by: Ley Foon Tan
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/altera-pcie.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt
b/Documentation
On Mon, Feb 25, 2019 at 5:35 PM Ley Foon Tan wrote:
>
> On Tue, 2019-02-19 at 16:23 +, Lorenzo Pieralisi wrote:
> > On Thu, Feb 14, 2019 at 11:20:36PM +0800, Ley Foon Tan wrote:
> > >
> > > Add PCIe Root Port support for Stratix 10 device.
> > >
>
On Tue, 2019-02-19 at 16:23 +, Lorenzo Pieralisi wrote:
> On Thu, Feb 14, 2019 at 11:20:36PM +0800, Ley Foon Tan wrote:
> >
> > Add PCIe Root Port support for Stratix 10 device.
> >
> > Main differences:
> Main differences with what ? We need to rewrite this c
On Fri, 2019-02-15 at 16:55 +0900, Masahiro Yamada wrote:
> +CC: Ley Foon Tan
> +CC: nios2-...@lists.rocketboards.org
>
>
> On Thu, Feb 14, 2019 at 2:40 AM Christoph Hellwig wrote:
>
> >
> > diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig
> > ind
Enable PCIE_ALTERA on ARM64 platform.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 6671946..6012f30 100644
--- a/drivers/pci
/lkml.org/lkml/2018/12/31/46
[v3]: https://lkml.org/lkml/2019/1/2/16
Ley Foon Tan (3):
PCI: altera: Add Stratix 10 PCIe support
PCI: altera: Enable driver on ARM64
dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0
.../devicetree/bindings/pci/altera-pcie.txt|4 +-
dr
Add support for altr,pcie-root-port-2.0.
Signed-off-by: Ley Foon Tan
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/altera-pcie.txt|4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt
b
Add PCIe Root Port support for Stratix 10 device.
Main differences:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c |
On Sat, Feb 9, 2019 at 12:29 AM Lorenzo Pieralisi
wrote:
>
> Apologies, I have dropped the ball on this one.
>
> On Wed, Jan 02, 2019 at 02:16:48PM +0800, Ley Foon Tan wrote:
> > Add PCIe Root Port support for Stratix 10 device.
> >
> > Main differences:
> >
On Wed, 2019-01-02 at 14:16 +0800, Ley Foon Tan wrote:
> Add PCIe Root Port support for Stratix 10 device and also update
> device tree binding documentation.
>
> v2 -> v3:
> -
> - Rename Stratix10 to Stratix 10.
> - Change bool s10_flag to enum version.
>
>
ers to NULL/zero.
- Rename *_funcs to *_data.
- Update comment and fix coding style warning from checkpatch.pl.
- Rename StratixXX to stratix10.
History:
[v1]: https://lkml.org/lkml/2018/12/26/68
[v2]: https://lkml.org/lkml/2018/12/31/46
Ley Foon Tan (2):
PCI: altera: Add Stratix 10 PCIe s
Add PCIe Root Port support for Stratix 10 device.
Main differences:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig |
Add support for altr,pcie-root-port-2.0.
Signed-off-by: Ley Foon Tan
---
.../devicetree/bindings/pci/altera-pcie.txt|4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt
b/Documentation/devicetree/bindings/pci
; 2a7275a3d867 PCI: altera: Fix TLP_CFG_DW0 for TLP write
>
> One of these is not like the others.
Okay, will change it.
>
> On Mon, Dec 31, 2018 at 04:24:52PM +0800, Ley Foon Tan wrote:
> ...
> >
> > +struct altera_pcie_data {
> > + int (*tlp_read_pkt)(struc
On Mon, 2018-12-31 at 10:15 -0600, Bjorn Helgaas wrote:
> On Mon, Dec 31, 2018 at 04:24:51PM +0800, Ley Foon Tan wrote:
> >
> > Add PCIe Root Port support for Stratix10 device and also update
> "Stratix10" is a big step better than "StratixXX" because a web
&
Add PCIe Root Port support for Stratix10 device.
Main differences:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig |2 +-
dr
rom checkpatch.pl.
- Rename StratixXX to stratix10.
History:
[v1]: https://lkml.org/lkml/2018/12/26/68
Ley Foon Tan (2):
pci: altera: Add Stratix10 PCIe support
Documentation: dt-bindings: pci: altera: Add altr,pcie-root-port-2.0
.../devicetree/bindings/pci/altera-pcie.txt|
Add support for altr,pcie-root-port-2.0.
Signed-off-by: Ley Foon Tan
---
.../devicetree/bindings/pci/altera-pcie.txt|4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt
b/Documentation/devicetree/bindings/pci
On Fri, 2018-12-28 at 21:12 -0600, Bjorn Helgaas wrote:
> Run "git log --oneline drivers/pci/controller" and make your subject
> line
> match in style, phrasing, and capitalization.
>
> On Thu, Dec 27, 2018 at 01:09:45AM +0800, Ley Foon Tan wrote:
> >
> > Ad
Add PCIe rootport support for StratixXX device.
Main differences:
- HIP interface
- TLP programming flow
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig |2 +-
drivers/pci/controller/pcie-altera.c | 228 +++---
2 files changed, 209
Add support for altr,pcie-root-port-2.0.
Signed-off-by: Ley Foon Tan
---
.../devicetree/bindings/pci/altera-pcie.txt|4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
mode change 100644 => 100755
Documentation/devicetree/bindings/pci/altera-pcie.txt
diff --gi
Add PCIe rootport support for StratixXX device family and also update
device tree binding documentation.
Ley Foon Tan (2):
pci: altera: Add StratixXX PCIe support
Documentation: dt-bindings: pci: altera: Add altr,pcie-root-port-2.0
.../devicetree/bindings/pci/altera-pcie.txt|4
isn't
> selected/implied).
> That might make it clearer to people that a bare 'default n' is
> redundant.
> ...
>
> Signed-off-by: Bartlomiej Zolnierkiewicz
Acked-by: Ley Foon Tan
> ---
> arch/nios2/Kconfig
ined!
>
> The problem is seen with gcc 7.3.0.
>
> Export the missing symbols.
>
> Fixes: 2fc8483fdcde ("nios2: Build infrastructure")
> Signed-off-by: Guenter Roeck
Acked-by: Ley Foon Tan
> ---
> arch/nios2/kernel/nios2_ksyms.c | 12
> 1 file ch
On Fri, 2018-09-07 at 13:09 -0500, Rob Herring wrote:
> On Thu, Sep 6, 2018 at 9:21 PM Ley Foon Tan
> wrote:
> >
> >
> > On Wed, 2018-09-05 at 18:53 -0500, Rob Herring wrote:
> > >
> > > Align nios2 with other architectures which build the dtb files in
help enable the 'dtbs' target which builds all the
> dtbs
> regardless of kernel config.
>
> This transition could break some scripts if they expect dtb files in
> the old location.
>
> Cc: Ley Foon Tan
> Cc: nios2-...@lists.rocketboards.org
> Signed-off-by:
Hi Linus
There is one arch/nios2 update for v4.19-rc2.
Please consider pulling.
Regards
Ley Foon
The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3:
Linux 4.19-rc1 (2018-08-26 14:11:59 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/lin
On Mon, 2018-08-27 at 20:52 -0500, Rob Herring wrote:
> In preparation to remove the node name pointer from struct
> device_node,
> convert printf users to use the %pOFn format specifier.
>
> Cc: Ley Foon Tan
> Cc: nios2-...@lists.rocketboards.org
> Signed-off-by: Rob Herrin
On Tue, 2018-08-21 at 01:15 +0900, Masahiro Yamada wrote:
> 2018-08-16 16:05 GMT+09:00 Tobias Klauser :
> >
> > DEBUG_STACK_USAGE is already defined in lib/Kconfig.debug
> >
> > Signed-off-by: Tobias Klauser
>
> Reviewed-by: Masahiro
> #include
> #include
> #include
> @@ -147,6 +148,7 @@ void __init setup_arch(char **cmdline_p)
>
> console_verbose();
>
> + memory_size = memblock_phys_mem_size();
> memory_start = PAGE_ALIGN((unsigned long)__pa(_end));
> memory_end = (unsigned long) CONFIG_NIOS2_MEM_BASE +
> memory_size;
>
> --
Acked-by: Ley Foon Tan
memblock_reserve(dram_start, memory_start - dram_start);
> #ifdef CONFIG_BLK_DEV_INITRD
> if (initrd_start) {
> - reserve_bootmem(virt_to_phys((void *)initrd_start),
> - initrd_end - initrd_start,
> BOOTMEM_DEFAULT);
> + memblock_reserve(virt_to_phys((void *)initrd_start),
> + initrd_end - initrd_start);
> }
> #endif /* CONFIG_BLK_DEV_INITRD */
>
> --
> 2.7.4
Acked-by: Ley Foon Tan
t; - No changes.
>
> Impact on "scripts/get_maintainer.pl -f
> Documentation/devicetree/bindings/nios2/":
>
> -Rob Herring (maintainer:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE
> BINDINGS,commit_signer:2/2=100%,authored:1/2=50%)
> +Ley Foon Tan (maintainer:N
d it can manually select it and move the
> > > > PCI_DOMAINS selection from PCI controllers configuration file
> > > > to ARM
> > > > sub-arch config entries that currently require it, fixing the
> > > > issue.
> > > >
> > > >
Hi Linus
Here is nios2 update for v4.17-rc1.
Please consider pulling.
Regards
Ley Foon
The following changes since commit 0adb32858b0bddf4ada5f364a84ed60b196dbcda:
Linux 4.16 (2018-04-01 14:20:27 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/gi
mplementation) and x86_64 (which doesn't).
>
> Signed-off-by: Shea Levy
Acked-by: Ley Foon Tan
> ---
> arch/nios2/mm/init.c | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/arch/nios2/mm/init.c b/arch/nios2/mm/init.c
> index c92fe4234009..3df75ff8c
On Mon, 2018-02-12 at 13:14 +1100, Stephen Rothwell wrote:
> Hi Ley,
>
> On Mon, 12 Feb 2018 09:23:49 +0800 Ley Foon Tan om> wrote:
> >
> >
> > On Mon, 2018-02-12 at 09:20 +1100, Stephen Rothwell wrote:
> > >
> > >
> > > Commits
> &
On Mon, 2018-02-12 at 09:20 +1100, Stephen Rothwell wrote:
> Hi Ley,
>
> Commits
>
> 5d13c7317998 ("nios2: dts: Remove leading 0x and 0s from bindings
> notation")
> e0691ebb33c1 ("nios2: defconfig: Cleanup from old Kconfig options")
>
> are missing a Signed-off-by from their committer.
>
>
Hi Linus
Here is nios2 update for v4.16-rc1.
Please consider pulling.
Regards
Ley Foon
The following changes since commit d8a5b80568a9cb66810e75b182018e9edb68e8ff:
Linux 4.15 (2018-01-28 13:20:33 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git
rch/nios2/Kconfig
> +++ b/arch/nios2/Kconfig
> @@ -152,7 +152,6 @@ menu "Advanced setup"
>
> config ADVANCED_OPTIONS
> bool "Prompt for advanced kernel configuration options"
> - help
>
> comment "Default settings for advanced configuration options are
> used"
> depends on !ADVANCED_OPTIONS
> --
> 2.14.1
>
Acked-by: Ley Foon Tan
se;
> u32 ctrl;
> u32 reg0, reg1;
> u32 comp_status = 1;
> --
> 2.7.4
Acked-by: Ley Foon Tan
Hi Linus
Here is nios2 update for v4.14-rc1.
Please consider pulling.
Regards
Ley Foon
The following changes since commit 569dbb88e80deb68974ef6fdd6a13edb9d686261:
Linux 4.13 (2017-09-03 13:56:17 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/gi
: implement flush_dcache_mmap_lock/unlock
Ley Foon Tan (1):
nios2: use generic strncpy_from_user() and strnlen_user()
Marek Vasut (3):
nios2: Add NIOS2_ARCH_REVISION to select between R1 and R2
nios2: Add BMX support
nios2: Add CDX support
Tobias Klauser (5):
nios2: add
lock)
> +#define flush_dcache_mmap_unlock(mapping) \
> + spin_unlock_irq(&(mapping)->tree_lock)
>
> #endif /* _ASM_NIOS2_CACHEFLUSH_H */
> --
> 2.11.0
>
Acked-by: Ley Foon Tan
Regards
Ley Foon
Hi Linus
There is one arch/nios2 fix for v4.11.
Please consider pulling.
Regards
Ley Foon
The following changes since commit a71c9a1c779f2499fb2afc0553e543f18aff6edf:
Linux 4.11-rc5 (2017-04-02 17:23:54 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/ke
gt; Reported-by: Guenter Roeck
> Reference: http://lkml.kernel.org/r/20170226210338.GA19476@roeck-us.n
> et
> Tested-by: Guenter Roeck
> Signed-off-by: Tobias Klauser
Acked-by: Ley Foon Tan
Thanks for the fix. Will add this for 4.11.
Regards
Ley Foon
> ---
> arch/nios2/ker
On Tue, Feb 28, 2017 at 6:31 PM, Ley Foon Tan wrote:
> Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
> and this cause writing to configuration space will fail. This patch
> fix it by using correct FMTTYPE for write operation.
>
> Signed-off-b
Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
and this cause writing to configuration space will fail. This patch
fix it by using correct FMTTYPE for write operation.
Signed-off-by: Ley Foon Tan
Cc: sta...@vger.kernel.org
---
drivers/pci/host/pcie-altera.c | 10
On Tue, Feb 28, 2017 at 6:37 PM, Ley Foon Tan wrote:
> Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
> and this cause writing to configuration space will fail. This patch
> fix it by using correct FMTTYPE for write operation.
>
> Signed-off-by: Ley Foon
Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
and this cause writing to configuration space will fail. This patch
fix it by using correct FMTTYPE for write operation.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 10 +++---
1 file changed, 7
Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
and this cause writing to configuration space will fail. This patch
fix it by using correct FMTTYPE for write operation.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 10 +++---
1 file changed, 7
to static inline
- Extend !__ASSEMBLY__ section in asm/page.h
Ley Foon Tan (1):
nios2: add screen_info
Tobias Klauser (2):
nios2: Extend !__ASSEMBLY__ section in asm/page.h
nios2: Convert pfn_valid to static inline
On Rab, 2016-11-23 at 14:52 +, Geliang Tang wrote:
> Use builtin_platform_driver() helper to simplify the code.
>
> Signed-off-by: Geliang Tang
Acked-by: Ley Foon Tan
> ---
> drivers/pci/host/pcie-altera.c | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
td.h, and adjust all
>> architectures using the generic syscall list to define it so that no
>> in-tree architectures are affected.
>>
>> Cc: Vineet Gupta
>> Cc: Catalin Marinas
>> Cc: Will Deacon
>> Cc: Mark Salter
>> Cc: Aurelien Jacquiot
>&
default:
> + ret = 0;
> break;
> }
Acked-by: Ley Foon Tan
/nios2/boot/dts/10m50_devboard.dts
> @@ -83,6 +83,7 @@
> fifo-size = <32>;
> reg-io-width = <4>;
> reg-shift = <2>;
> + tx-threshold = <16>;
> };
>
> sysid: sysid@18001528 {
Acked-by: Ley Foon Tan
On Fri, Aug 26, 2016 at 9:47 AM, Ley Foon Tan wrote:
> Altera PCIe IP can be configured as rootport or device and they might have
> same vendor ID. It will cause the system hang issue if Altera PCIe is in
> endpoint mode and work with other PCIe rootport that from other vendors.
>
&
Rework configs accessors so a future patch can use them in _probe()
with struct altera_pcie instead of struct pci_bus.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 64 +++---
1 file changed, 41 insertions(+), 23 deletions(-)
diff --git a
On Wed, Aug 10, 2016 at 8:27 PM, Tobias Klauser wrote:
> Use of_property_read_bool instead of open-coding it as fpcu_has. Convert
> the members of struct cpuinfo from u32 to bool accordingly as they are
> only used as boolean anyhow.
>
> Signed-off-by: Tobias Klauser
Acked-b
_FIXUP to altera_pcie_host_init().
History:
v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT
v3: Move retrain function to before pci_scan_root_bus and remove _FIXUP
v4: Split patch to 2 patches
Ley Foon Tan (2):
PCI: altera: Rework configs accessors
PCI: altera: Move retrain from
-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 151 +
1 file changed, 91 insertions(+), 60 deletions(-)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 34e6258..4ca50a2 100644
--- a/drivers/pci/host/pcie-altera.c
On Thu, Aug 25, 2016 at 9:56 PM, Bjorn Helgaas wrote:
> On Thu, Aug 25, 2016 at 01:59:56PM +0800, Ley Foon Tan wrote:
>> Altera PCIe IP can be configured as rootport or device and they might have
>> same vendor ID. It will cause the system hang issue if Altera PCIe is in
>> e
_altera_pcie_cfg_read() and _altera_pcie_cfg_write() to use struct
altera_pcie as argument instead of struct pci_bus.
Signed-off-by: Ley Foon Tan
---
v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT
v3: Move retrain function to before pci_scan_root_bus and remove _FIXUP
---
drivers/pci/host
On Thu, Aug 25, 2016 at 1:54 AM, Bjorn Helgaas wrote:
> [+cc Ray, Scott, Jon, bcm-kernel-feedback-list]
>
> On Wed, Aug 24, 2016 at 03:07:52PM +0800, Ley Foon Tan wrote:
>> On Mon, Aug 22, 2016 at 11:47 PM, Bjorn Helgaas wrote:
>> > On Fri, Aug 19, 2016 at 04:24:38PM +
On Mon, Aug 22, 2016 at 11:47 PM, Bjorn Helgaas wrote:
> On Fri, Aug 19, 2016 at 04:24:38PM +0800, Ley Foon Tan wrote:
>> Altera PCIe IP can be configured as rootport or device and they might have
>> same vendor ID. It will cause the system hang issue if Altera PCIe is in
>&
-off-by: Ley Foon Tan
---
v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT
---
drivers/pci/host/pcie-altera.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 58eef99..33b6968 100644
--- a/drivers/pci/host/pcie
On Fri, Aug 19, 2016 at 4:18 AM, Bjorn Helgaas wrote:
>
> On Mon, Aug 15, 2016 at 04:36:19PM +0800, Ley Foon Tan wrote:
> > Altera PCIe IP can be configured as rootport or device and they might have
> > same vendor ID. It will cause the system hang issue if Altera PCIe is in
>
On Fri, Aug 19, 2016 at 4:19 AM, Bjorn Helgaas wrote:
> On Mon, Aug 15, 2016 at 02:06:02PM +0800, Ley Foon Tan wrote:
>> Poll for link training status is cleared before poll for link up status.
>> This can help to get the reliable link up status, especially when PCIe
>&
Poll for link training status is cleared before poll for link up status.
This can help to get the reliable link up status, especially when PCIe
is in Gen 3 speed.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 45 ++
1 file changed, 37
-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 58eef99..6477738 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -139,6 +139,9
On Sat, Jul 23, 2016 at 5:07 AM, Bjorn Helgaas wrote:
>
> On Tue, Jun 21, 2016 at 04:53:11PM +0800, Ley Foon Tan wrote:
> > This 2 patches fix the issue before and after retrain link.
> >
> > Ley Foon Tan (2):
> > PCI: altera: check link status before retrain link
On Tue, Jul 12, 2016 at 6:19 PM, Ley Foon Tan wrote:
>
> On Tue, Jun 21, 2016 at 4:53 PM, Ley Foon Tan wrote:
> >
> > This 2 patches fix the issue before and after retrain link.
> >
> > Ley Foon Tan (2):
> > PCI: altera: check link status before retrain link
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