Hello My Dear.
Please do not feel disturbed for contacting you, based on the
critical condition I find mine self, though, it's not financial
problem, but my health, you might have know that cancer is not what to
talk home about, I am married to Mr. Abaulkarim Rail who worked with
Tunisia embassy
Bonjour mon cher correspondant,
Je m'appelle Linda GUERIN d'origine française et âgé de 30ans. Je suis
gestionnaire de projet au sein d'une organisation nommée OCID siégé au
Canada. L'ocid est une organisation qui œuvre dans le domaine du
développement, de la coopération internationale et de
being understaffed during peak processing periods.
Let's start it today if you have needs.
Thanks,
Linda
being understaffed during peak processing periods.
Let's start it today if you have needs.
Thanks,
Linda
being understaffed during peak processing periods.
Let's start it today if you have needs.
Thanks,
Linda
being understaffed during peak processing periods.
Let's start it today if you have needs.
Thanks,
Linda
being understaffed during peak processing periods.
Let's start it today if you have needs.
Thanks,
Linda
A week ago I upgraded to the latest Ubuntu distribution (Linux thunderbird
4.18.0-10-generic #11-Ubuntu SMP Thu Oct 11 15:13:55 UTC 2018 x86_64 x86_64
x86_64 GNU/Linux).
Whenever I run "shutdown -h now" or "reboot" I receive an immediate kernel
crash with a dump that has:
"Code: Bad RIP
A week ago I upgraded to the latest Ubuntu distribution (Linux thunderbird
4.18.0-10-generic #11-Ubuntu SMP Thu Oct 11 15:13:55 UTC 2018 x86_64 x86_64
x86_64 GNU/Linux).
Whenever I run "shutdown -h now" or "reboot" I receive an immediate kernel
crash with a dump that has:
"Code: Bad RIP
and skin images
and wedding photos.
We do also different kind of beauty retouching, portraits retouching.
We can send editing for your photos if you send us one or two photos.
Thanks,
Linda
and skin images
and wedding photos.
We do also different kind of beauty retouching, portraits retouching.
We can send editing for your photos if you send us one or two photos.
Thanks,
Linda
and skin images
and wedding photos.
We do also different kind of beauty retouching, portraits retouching.
We can send editing for your photos if you send us one or two photos.
Thanks,
Linda
and skin images
and wedding photos.
We do also different kind of beauty retouching, portraits retouching.
We can send editing for your photos if you send us one or two photos.
Thanks,
Linda
and skin images
and wedding photos.
We do also different kind of beauty retouching, portraits retouching.
We can send editing for your photos if you send us one or two photos.
Thanks,
Linda
and skin images
and wedding photos.
We do also different kind of beauty retouching, portraits retouching.
We can send editing for your photos if you send us one or two photos.
Thanks,
Linda
and skin images
and wedding photos.
We do also different kind of beauty retouching, portraits retouching.
We can send editing for your photos if you send us one or two photos.
Thanks,
Linda
and skin images
and wedding photos.
We do also different kind of beauty retouching, portraits retouching.
We can send editing for your photos if you send us one or two photos.
Thanks,
Linda
ld to build external modules failed.
It seems unlikely the two problems are related, but I wanted to fix
this first before going on to the compile-fails.
Please Cc me, as I'm not currently on the list.
Thanks,
Linda W.
ld to build external modules failed.
It seems unlikely the two problems are related, but I wanted to fix
this first before going on to the compile-fails.
Please Cc me, as I'm not currently on the list.
Thanks,
Linda W.
, Motorcycle Owners, Scuba Diver and many more…
Data Fields: Full name, Postal address, Email address, IP address, and the
source of the contact.
Please reply with your need, So that I would be able to assist you further.
Thank you,
Linda Jackson
Research Analyst
, Motorcycle Owners, Scuba Diver and many more…
Data Fields: Full name, Postal address, Email address, IP address, and the
source of the contact.
Please reply with your need, So that I would be able to assist you further.
Thank you,
Linda Jackson
Research Analyst
On 07/04/2017 04:37 PM, Dan Williams wrote:
> On Tue, Jul 4, 2017 at 1:08 PM, Jerry Hoemann wrote:
>> On Sat, Jul 01, 2017 at 01:46:03PM -0700, Dan Williams wrote:
>>> On Sat, Jul 1, 2017 at 1:38 PM, Jerry Hoemann wrote:
On Sat, Jul 01, 2017 at
On 07/04/2017 04:37 PM, Dan Williams wrote:
> On Tue, Jul 4, 2017 at 1:08 PM, Jerry Hoemann wrote:
>> On Sat, Jul 01, 2017 at 01:46:03PM -0700, Dan Williams wrote:
>>> On Sat, Jul 1, 2017 at 1:38 PM, Jerry Hoemann wrote:
On Sat, Jul 01, 2017 at 01:10:31PM -0700, Dan Williams wrote:
> On
On 06/29/2017 06:58 PM, Dan Williams wrote:
> On Thu, Jun 29, 2017 at 3:49 PM, Linda Knippers <linda.knipp...@hpe.com>
> wrote:
>>> The parent region of the namespace will have a 'volatile' type:
>>>
>>> # cat /sys/bus/nd/devices/region0/devtype
>>>
On 06/29/2017 06:58 PM, Dan Williams wrote:
> On Thu, Jun 29, 2017 at 3:49 PM, Linda Knippers
> wrote:
>>> The parent region of the namespace will have a 'volatile' type:
>>>
>>> # cat /sys/bus/nd/devices/region0/devtype
>>> nd_volatile
>>
>>
On 6/29/2017 6:43 PM, Dan Williams wrote:
On Thu, Jun 29, 2017 at 3:35 PM, Linda Knippers <linda.knipp...@hpe.com> wrote:
On 06/29/2017 06:28 PM, Dan Williams wrote:
On Thu, Jun 29, 2017 at 3:12 PM, Linda Knippers <linda.knipp...@hpe.com> wrote:
[..]
The /dev/pmem
device name ju
On 6/29/2017 6:43 PM, Dan Williams wrote:
On Thu, Jun 29, 2017 at 3:35 PM, Linda Knippers wrote:
On 06/29/2017 06:28 PM, Dan Williams wrote:
On Thu, Jun 29, 2017 at 3:12 PM, Linda Knippers wrote:
[..]
The /dev/pmem
device name just tells you that your block device is hosted by a
driver
On 06/29/2017 06:28 PM, Dan Williams wrote:
> On Thu, Jun 29, 2017 at 3:12 PM, Linda Knippers <linda.knipp...@hpe.com>
> wrote:
> [..]
>>> The /dev/pmem
>>> device name just tells you that your block device is hosted by a
>>> driver that knows how to han
On 06/29/2017 06:28 PM, Dan Williams wrote:
> On Thu, Jun 29, 2017 at 3:12 PM, Linda Knippers
> wrote:
> [..]
>>> The /dev/pmem
>>> device name just tells you that your block device is hosted by a
>>> driver that knows how to handle persistent memory constrai
On 6/29/2017 5:50 PM, Dan Williams wrote:
On Thu, Jun 29, 2017 at 2:16 PM, Linda Knippers <linda.knipp...@hpe.com> wrote:
On 06/29/2017 04:42 PM, Dan Williams wrote:
On Thu, Jun 29, 2017 at 12:20 PM, Linda Knippers <linda.knipp...@hpe.com> wrote:
On 06/29/2017 01:54 PM, Dan Wi
On 6/29/2017 5:50 PM, Dan Williams wrote:
On Thu, Jun 29, 2017 at 2:16 PM, Linda Knippers wrote:
On 06/29/2017 04:42 PM, Dan Williams wrote:
On Thu, Jun 29, 2017 at 12:20 PM, Linda Knippers wrote:
On 06/29/2017 01:54 PM, Dan Williams wrote:
Allow volatile nfit ranges to participate
On 06/29/2017 04:42 PM, Dan Williams wrote:
> On Thu, Jun 29, 2017 at 12:20 PM, Linda Knippers <linda.knipp...@hpe.com>
> wrote:
>> On 06/29/2017 01:54 PM, Dan Williams wrote:
>>> Allow volatile nfit ranges to participate in all the same infrastructure
>>> pr
On 06/29/2017 04:42 PM, Dan Williams wrote:
> On Thu, Jun 29, 2017 at 12:20 PM, Linda Knippers
> wrote:
>> On 06/29/2017 01:54 PM, Dan Williams wrote:
>>> Allow volatile nfit ranges to participate in all the same infrastructure
>>> provided for persistent me
On 06/29/2017 01:54 PM, Dan Williams wrote:
> Allow volatile nfit ranges to participate in all the same infrastructure
> provided for persistent memory regions.
This seems to be a bit more than "other rework".
> A resulting resulting namespace
> device will still be called "pmem", but the
On 06/29/2017 01:54 PM, Dan Williams wrote:
> Allow volatile nfit ranges to participate in all the same infrastructure
> provided for persistent memory regions.
This seems to be a bit more than "other rework".
> A resulting resulting namespace
> device will still be called "pmem", but the
On 6/7/2017 5:33 PM, Kani, Toshimitsu wrote:
On Wed, 2017-06-07 at 14:06 -0700, Dan Williams wrote:
On Wed, Jun 7, 2017 at 1:57 PM, Kani, Toshimitsu
wrote:
On Wed, 2017-06-07 at 12:09 -0700, Dan Williams wrote:
On Wed, Jun 7, 2017 at 11:49 AM, Toshi Kani
On 6/7/2017 5:33 PM, Kani, Toshimitsu wrote:
On Wed, 2017-06-07 at 14:06 -0700, Dan Williams wrote:
On Wed, Jun 7, 2017 at 1:57 PM, Kani, Toshimitsu
wrote:
On Wed, 2017-06-07 at 12:09 -0700, Dan Williams wrote:
On Wed, Jun 7, 2017 at 11:49 AM, Toshi Kani
wrote:
:
+
+static void
On 04/21/2017 07:48 PM, Dan Williams wrote:
> The nvdimm_flush() mechanism helps to reduce the impact of an ADR
> (asynchronous-dimm-refresh) failure. The ADR mechanism handles flushing
> platform WPQ (write-pending-queue) buffers when power is removed. The
> nvdimm_flush() mechanism performs that
On 04/21/2017 07:48 PM, Dan Williams wrote:
> The nvdimm_flush() mechanism helps to reduce the impact of an ADR
> (asynchronous-dimm-refresh) failure. The ADR mechanism handles flushing
> platform WPQ (write-pending-queue) buffers when power is removed. The
> nvdimm_flush() mechanism performs that
Your shipment(s) is scheduled for delivery
Scheduled Delivery Date: 12/02/2016
Shipper: Chambers Group.
Kindly view the attached document for shipment/delivery details and
tracking procedure. You can also request a delivery change (e.g.
reschedule or reroute) from the tracking detail.
Your shipment(s) is scheduled for delivery
Scheduled Delivery Date: 12/02/2016
Shipper: Chambers Group.
Kindly view the attached document for shipment/delivery details and
tracking procedure. You can also request a delivery change (e.g.
reschedule or reroute) from the tracking detail.
On 10/7/2016 3:52 PM, Dan Williams wrote:
> On Fri, Oct 7, 2016 at 11:19 AM, Linda Knippers <linda.knipp...@hpe.com>
> wrote:
>> Hi Dan,
>>
>> A couple of general questions...
>>
>> On 10/7/2016 12:38 PM, Dan Williams wrote:
>>> With t
On 10/7/2016 3:52 PM, Dan Williams wrote:
> On Fri, Oct 7, 2016 at 11:19 AM, Linda Knippers
> wrote:
>> Hi Dan,
>>
>> A couple of general questions...
>>
>> On 10/7/2016 12:38 PM, Dan Williams wrote:
>>> With the arrival of the device-dax
Hi Dan,
A couple of general questions...
On 10/7/2016 12:38 PM, Dan Williams wrote:
> With the arrival of the device-dax facility in 4.7 a pmem namespace can
> now be configured into a total of four distinct modes: 'raw', 'sector',
> 'memory', and 'dax'. Where raw, sector, and memory are block
Hi Dan,
A couple of general questions...
On 10/7/2016 12:38 PM, Dan Williams wrote:
> With the arrival of the device-dax facility in 4.7 a pmem namespace can
> now be configured into a total of four distinct modes: 'raw', 'sector',
> 'memory', and 'dax'. Where raw, sector, and memory are block
On 8/18/2016 3:48 PM, Dan Williams wrote:
> On Thu, Aug 18, 2016 at 11:48 AM, Vishal Verma
> wrote:
>> The nfit driver had an acpi event notification handler, but it never
>> would've worked because we weren't setting the
>> ACPI_DRIVER_ALL_NOTIFY_EVENTS flag in
On 8/18/2016 3:48 PM, Dan Williams wrote:
> On Thu, Aug 18, 2016 at 11:48 AM, Vishal Verma
> wrote:
>> The nfit driver had an acpi event notification handler, but it never
>> would've worked because we weren't setting the
>> ACPI_DRIVER_ALL_NOTIFY_EVENTS flag in acpi_driver.
>
> Let's update
On 07/22/2016 03:25 PM, Linda Knippers wrote:
>
>
> On 7/22/2016 11:36 AM, Viresh Kumar wrote:
>> On 22-07-16, 17:14, Andreas Herrmann wrote:
>>> diff --git a/drivers/cpufreq/pcc-cpufreq.c b/drivers/cpufreq/pcc-cpufreq.c
>>> index a7ecb9a..3f0ce2a 100644
>&g
On 07/22/2016 03:25 PM, Linda Knippers wrote:
>
>
> On 7/22/2016 11:36 AM, Viresh Kumar wrote:
>> On 22-07-16, 17:14, Andreas Herrmann wrote:
>>> diff --git a/drivers/cpufreq/pcc-cpufreq.c b/drivers/cpufreq/pcc-cpufreq.c
>>> index a7ecb9a..3f0ce2a 100644
>&g
On 7/22/2016 11:36 AM, Viresh Kumar wrote:
> On 22-07-16, 17:14, Andreas Herrmann wrote:
>> diff --git a/drivers/cpufreq/pcc-cpufreq.c b/drivers/cpufreq/pcc-cpufreq.c
>> index a7ecb9a..3f0ce2a 100644
>> --- a/drivers/cpufreq/pcc-cpufreq.c
>> +++ b/drivers/cpufreq/pcc-cpufreq.c
>> @@ -555,8
On 7/22/2016 11:36 AM, Viresh Kumar wrote:
> On 22-07-16, 17:14, Andreas Herrmann wrote:
>> diff --git a/drivers/cpufreq/pcc-cpufreq.c b/drivers/cpufreq/pcc-cpufreq.c
>> index a7ecb9a..3f0ce2a 100644
>> --- a/drivers/cpufreq/pcc-cpufreq.c
>> +++ b/drivers/cpufreq/pcc-cpufreq.c
>> @@ -555,8
On 7/20/2016 9:50 PM, Vishal Verma wrote:
> When a latent (unknown to 'badblocks') error is encountered, it will
> trigger a machine check exception. On a system with machine check
> recovery, this will only SIGBUS the process(es) which had the bad page
> mapped (as opposed to a kernel panic on
On 7/20/2016 9:50 PM, Vishal Verma wrote:
> When a latent (unknown to 'badblocks') error is encountered, it will
> trigger a machine check exception. On a system with machine check
> recovery, this will only SIGBUS the process(es) which had the bad page
> mapped (as opposed to a kernel panic on
On 7/21/2016 5:10 PM, Vishal Verma wrote:
> On 07/21, Linda Knippers wrote:
>>
>>
>> On 7/20/2016 9:50 PM, Vishal Verma wrote:
>>> When a latent (unknown to 'badblocks') error is encountered, it will
>>> trigger a machine check exception. On a
On 7/21/2016 5:10 PM, Vishal Verma wrote:
> On 07/21, Linda Knippers wrote:
>>
>>
>> On 7/20/2016 9:50 PM, Vishal Verma wrote:
>>> When a latent (unknown to 'badblocks') error is encountered, it will
>>> trigger a machine check exception. On a
On 07/20/2016 09:50 PM, Vishal Verma wrote:
> Normally, an ARS (Address Range Scrub) only happens at
> boot/initialization time. There can however arise situations where a
> bus-wide rescan is needed - notably, in the case of discovering a latent
> media error, we should do a full rescan to figure
On 07/20/2016 09:50 PM, Vishal Verma wrote:
> Normally, an ARS (Address Range Scrub) only happens at
> boot/initialization time. There can however arise situations where a
> bus-wide rescan is needed - notably, in the case of discovering a latent
> media error, we should do a full rescan to figure
On 7/21/2016 3:46 PM, Dan Williams wrote:
> On Thu, Jul 21, 2016 at 12:40 PM, Linda Knippers <linda.knipp...@hpe.com>
> wrote:
>> On 07/20/2016 09:50 PM, Vishal Verma wrote:
>>> Normally, an ARS (Address Range Scrub) only happens at
>>> boot/initiali
On 7/21/2016 3:46 PM, Dan Williams wrote:
> On Thu, Jul 21, 2016 at 12:40 PM, Linda Knippers
> wrote:
>> On 07/20/2016 09:50 PM, Vishal Verma wrote:
>>> Normally, an ARS (Address Range Scrub) only happens at
>>> boot/initialization time. There can however arise s
On 7/13/2016 10:48 AM, Alex Williamson wrote:
> On Wed, 13 Jul 2016 12:18:59 +0200
> Joerg Roedel wrote:
>
>> On Wed, Jul 13, 2016 at 12:58:24PM +0300, Meelis Roos wrote:
> Just got http://kodu.ut.ee/~mroos/4.6-dmar-fault2.png when playing with
> BIOS settings
On 7/13/2016 10:48 AM, Alex Williamson wrote:
> On Wed, 13 Jul 2016 12:18:59 +0200
> Joerg Roedel wrote:
>
>> On Wed, Jul 13, 2016 at 12:58:24PM +0300, Meelis Roos wrote:
> Just got http://kodu.ut.ee/~mroos/4.6-dmar-fault2.png when playing with
> BIOS settings (disabling NUMA). It is
describe system
>>> physical address ranges that describe Virtual CD and Virtual Disk. For
>>> Virtual CD Region and Virtual Disk Region (both volatile and persistent),
>>> the following fields - Proximity Domain, SPA Range Structure Index, Flags,
>>> and
>&g
nges that describe Virtual CD and Virtual Disk. For
>>> Virtual CD Region and Virtual Disk Region (both volatile and persistent),
>>> the following fields - Proximity Domain, SPA Range Structure Index, Flags,
>>> and
>>>
On 6/4/2016 7:01 AM, joeyli wrote:
> Hi Dan,
>
> Thanks for your review.
>
> On Fri, Jun 03, 2016 at 12:27:34PM -0700, Dan Williams wrote:
>> On Fri, Jun 3, 2016 at 12:13 AM, Lee, Chun-Yi
>> wrote:
>>> This patch adds codes to treat a volatile virtual CD region as a
On 6/4/2016 7:01 AM, joeyli wrote:
> Hi Dan,
>
> Thanks for your review.
>
> On Fri, Jun 03, 2016 at 12:27:34PM -0700, Dan Williams wrote:
>> On Fri, Jun 3, 2016 at 12:13 AM, Lee, Chun-Yi
>> wrote:
>>> This patch adds codes to treat a volatile virtual CD region as a
>>> read-only pmem region,
On 6/6/2016 4:36 PM, Dan Williams wrote:
> On Mon, Jun 6, 2016 at 1:20 PM, Linda Knippers <linda.knipp...@hpe.com> wrote:
> [..]
>>> A solution to the posted-write-queue flushing needs to be available
>>> and a platform can choose to use flush hints or ADR. If
On 6/6/2016 4:36 PM, Dan Williams wrote:
> On Mon, Jun 6, 2016 at 1:20 PM, Linda Knippers wrote:
> [..]
>>> A solution to the posted-write-queue flushing needs to be available
>>> and a platform can choose to use flush hints or ADR. If the NFIT
>>> defines
On 6/6/2016 3:46 PM, Dan Williams wrote:
> On Mon, Jun 6, 2016 at 12:36 PM, Linda Knippers <linda.knipp...@hpe.com>
> wrote:
>>
>>
>> On 6/6/2016 3:31 PM, Dan Williams wrote:
>>> On Mon, Jun 6, 2016 at 12:25 PM, Linda Knippers <linda.knipp...@hpe.com&
On 6/6/2016 3:46 PM, Dan Williams wrote:
> On Mon, Jun 6, 2016 at 12:36 PM, Linda Knippers
> wrote:
>>
>>
>> On 6/6/2016 3:31 PM, Dan Williams wrote:
>>> On Mon, Jun 6, 2016 at 12:25 PM, Linda Knippers
>>> wrote:
>>>> On 6/4/2016 4:52 P
On 6/6/2016 3:31 PM, Dan Williams wrote:
> On Mon, Jun 6, 2016 at 12:25 PM, Linda Knippers <linda.knipp...@hpe.com>
> wrote:
>> On 6/4/2016 4:52 PM, Dan Williams wrote:
>>> There are scenarios where we need a middle ground between disabling all
>>> man
On 6/6/2016 3:31 PM, Dan Williams wrote:
> On Mon, Jun 6, 2016 at 12:25 PM, Linda Knippers
> wrote:
>> On 6/4/2016 4:52 PM, Dan Williams wrote:
>>> There are scenarios where we need a middle ground between disabling all
>>> manual bind/unbind attempts (v
On 6/4/2016 4:52 PM, Dan Williams wrote:
> There are scenarios where we need a middle ground between disabling all
> manual bind/unbind attempts (via driver->suppress_bind_attrs) and
> allowing unbind at any userspace-determined time. Pinning modules takes
> away one vector for unwanted
On 6/4/2016 4:52 PM, Dan Williams wrote:
> There are scenarios where we need a middle ground between disabling all
> manual bind/unbind attempts (via driver->suppress_bind_attrs) and
> allowing unbind at any userspace-determined time. Pinning modules takes
> away one vector for unwanted
I raised a general concern on a previous patch so I found a 1P server
with Skylake and HWP to try. This doesn't qualify as a tested-by
since all I did was apply the patch and boot the server but hey, it booted.
I do have a question below...
On 3/23/2016 12:07 AM, Srinivas Pandruvada wrote:
>
I raised a general concern on a previous patch so I found a 1P server
with Skylake and HWP to try. This doesn't qualify as a tested-by
since all I did was apply the patch and boot the server but hey, it booted.
I do have a question below...
On 3/23/2016 12:07 AM, Srinivas Pandruvada wrote:
>
On 3/17/2016 2:24 PM, Srinivas Pandruvada wrote:
> There are several reports of freeze on enabling HWP (Hardware PStates)
> feature on Skylake based systems by Intel P states driver. The root
> cause is identified as the HWP interrupts causing BIOS code to freeze.
> HWP interrupts uses thermal
On 3/17/2016 2:24 PM, Srinivas Pandruvada wrote:
> There are several reports of freeze on enabling HWP (Hardware PStates)
> feature on Skylake based systems by Intel P states driver. The root
> cause is identified as the HWP interrupts causing BIOS code to freeze.
> HWP interrupts uses thermal
On 3/17/2016 4:36 PM, Srinivas Pandruvada wrote:
> On Thu, 2016-03-17 at 16:03 -0400, Linda Knippers wrote:
>> On 3/17/2016 2:24 PM, Srinivas Pandruvada wrote:
>>>
>>> There are several reports of freeze on enabling HWP (Hardware
>>> PStates)
>>>
On 3/17/2016 4:36 PM, Srinivas Pandruvada wrote:
> On Thu, 2016-03-17 at 16:03 -0400, Linda Knippers wrote:
>> On 3/17/2016 2:24 PM, Srinivas Pandruvada wrote:
>>>
>>> There are several reports of freeze on enabling HWP (Hardware
>>> PStates)
>>>
On 3/17/2016 5:12 PM, Srinivas Pandruvada wrote:
> This needs to be done
> before SMM code path looks for _OSC capabilities. The bit 12 of
> _OSC in processor scope defines whether OS will handle thermal
> interrupts.
> When bit 12 is set to 1, OS will handle thermal
On 3/17/2016 5:12 PM, Srinivas Pandruvada wrote:
> This needs to be done
> before SMM code path looks for _OSC capabilities. The bit 12 of
> _OSC in processor scope defines whether OS will handle thermal
> interrupts.
> When bit 12 is set to 1, OS will handle thermal
On 3/17/2016 8:17 PM, Rafael J. Wysocki wrote:
>>> This change introduces a new function
>>> acpi_early_processor_set_osc(),
>>> which walks acpi name space and finds acpi processor object and
>>> set capability via _OSC method to take over thermal LVT.
>> Does this change
On 3/17/2016 8:17 PM, Rafael J. Wysocki wrote:
>>> This change introduces a new function
>>> acpi_early_processor_set_osc(),
>>> which walks acpi name space and finds acpi processor object and
>>> set capability via _OSC method to take over thermal LVT.
>> Does this change
On 2/8/2016 2:10 PM, Linda Knippers wrote:
> On 2/8/2016 1:30 PM, Dan Williams wrote:
>> ACPI 6.1 clarified that multi-interface dimms require multiple control
>> region entries (DCRs) per dimm. Previously we were assuming that a
>> control region is only present wh
On 2/8/2016 1:30 PM, Dan Williams wrote:
> ACPI 6.1 clarified that multi-interface dimms require multiple control
> region entries (DCRs) per dimm. Previously we were assuming that a
> control region is only present when block-data-windows are present.
We need to give this a quick test with
On 2/8/2016 1:30 PM, Dan Williams wrote:
> ACPI 6.1 clarified that multi-interface dimms require multiple control
> region entries (DCRs) per dimm. Previously we were assuming that a
> control region is only present when block-data-windows are present.
We need to give this a quick test with
On 2/8/2016 2:10 PM, Linda Knippers wrote:
> On 2/8/2016 1:30 PM, Dan Williams wrote:
>> ACPI 6.1 clarified that multi-interface dimms require multiple control
>> region entries (DCRs) per dimm. Previously we were assuming that a
>> control region is only present wh
On 11/10/2015 3:27 PM, Dan Williams wrote:
On Tue, Nov 10, 2015 at 11:49 AM, Jerry Hoemann wrote:
On Tue, Nov 10, 2015 at 12:51:59PM -0500, Jeff Moyer wrote:
Jerry Hoemann writes:
Add IOCTL type 'P' to denote NVDIMM_TYPE_PASSTHRU.
Can't you just make passthrough a separate command? If
On 11/10/2015 3:27 PM, Dan Williams wrote:
On Tue, Nov 10, 2015 at 11:49 AM, Jerry Hoemann wrote:
On Tue, Nov 10, 2015 at 12:51:59PM -0500, Jeff Moyer wrote:
Jerry Hoemann writes:
Add IOCTL type 'P' to denote NVDIMM_TYPE_PASSTHRU.
Can't you
This patch and the 2/2 patch don't seem to have gone anywhere.
Willy? or Ross?
-- ljk
On 8/14/2015 4:53 PM, Linda Knippers wrote:
> On 8/14/2015 4:15 PM, Jeff Moyer wrote:
>> commit bbab37ddc20b (block: Add support for DAX reads/writes to
>> block devices) caused a regress
This patch and the 2/2 patch don't seem to have gone anywhere.
Willy? or Ross?
-- ljk
On 8/14/2015 4:53 PM, Linda Knippers wrote:
> On 8/14/2015 4:15 PM, Jeff Moyer wrote:
>> commit bbab37ddc20b (block: Add support for DAX reads/writes to
>> block devices) caused a regress
Commit-ID: 31e09b18c863718939e3e9c30eee55f9011d85ee
Gitweb: http://git.kernel.org/tip/31e09b18c863718939e3e9c30eee55f9011d85ee
Author: Linda Knippers
AuthorDate: Tue, 1 Sep 2015 15:41:55 -0400
Committer: Ingo Molnar
CommitDate: Wed, 2 Sep 2015 09:33:25 +0200
x86/mm/srat: Print non
Commit-ID: 31e09b18c863718939e3e9c30eee55f9011d85ee
Gitweb: http://git.kernel.org/tip/31e09b18c863718939e3e9c30eee55f9011d85ee
Author: Linda Knippers <linda.knipp...@hp.com>
AuthorDate: Tue, 1 Sep 2015 15:41:55 -0400
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Wed
.
If someone is setting it, we might want to ask them what they expect
to happen with it.
Right now this bit is only printed if all the ACPI debug information is
turned on.
Signed-off-by: Linda Knippers
---
arch/x86/mm/srat.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch
On 9/1/2015 3:17 PM, Thomas Gleixner wrote:
> On Tue, 1 Sep 2015, Linda Knippers wrote:
>> Nobody checks this flag but it would be interesting to know if it's being
>> set on any platforms.
>
> What you're omitting to explain, is WHY it would be interesting.
With the addit
Nobody checks this flag but it would be interesting to know if it's being
set on any platforms.
Signed-off-by: Linda Knippers
---
arch/x86/mm/srat.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/mm/srat.c b/arch/x86/mm/srat.c
index 66338a6..c2aea63 100644
On 9/1/2015 3:17 PM, Thomas Gleixner wrote:
> On Tue, 1 Sep 2015, Linda Knippers wrote:
>> Nobody checks this flag but it would be interesting to know if it's being
>> set on any platforms.
>
> What you're omitting to explain, is WHY it would be interesting.
With the addit
.
If someone is setting it, we might want to ask them what they expect
to happen with it.
Right now this bit is only printed if all the ACPI debug information is
turned on.
Signed-off-by: Linda Knippers <linda.knipp...@hp.com>
---
arch/x86/mm/srat.c | 5 +++--
1 file changed, 3 insertions
Nobody checks this flag but it would be interesting to know if it's being
set on any platforms.
Signed-off-by: Linda Knippers <linda.knipp...@hp.com>
---
arch/x86/mm/srat.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/mm/srat.c b/arch/x86/mm/srat.c
On 8/27/2015 1:04 PM, Dan Williams wrote:
> On Thu, Aug 27, 2015 at 9:32 AM, Linda Knippers wrote:
>> I know this seems like a nit but we've going to live with this stuff for
>> a long time.
>
> Along those lines, Bob just came by my office and gave me a decisive
> argu
1 - 100 of 314 matches
Mail list logo