On Tue, Jul 21, 2020 at 10:28:51PM -0500, Gustavo A. R. Silva wrote:
> Replace the existing /* fall through */ comments and its variants with
> the new pseudo-keyword macro fallthrough[1].
>
> [1]
>
On Tue, Jul 21, 2020 at 10:19:03PM -0500, Gustavo A. R. Silva wrote:
> Replace the existing /* fall through */ comments and its variants with
> the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
> fall-through markings when it is the case.
>
> [1]
>
On Tue, Jul 28, 2020 at 01:49:44PM -0600, Jon Derrick wrote:
> VMD retransmits child device MSI/X with the VMD endpoint's requester-id.
> In order to support direct interrupt remapping of VMD child devices,
> ensure that the IRTE is programmed with the VMD endpoint's requester-id
> using
On Mon, Aug 03, 2020 at 03:52:40PM +1200, Mark Tomlinson wrote:
> The core interrupt code expects the irq_set_affinity call to update the
> effective affinity for the interrupt. This was not being done, so update
> iproc_msi_irq_set_affinity() to do so.
>
> Fixes: 3bc2b2348835 ("PCI: iproc: Add
On Tue, Aug 11, 2020 at 09:29:24AM +0800, Anson Huang wrote:
> When devm_clk_get() returns -EPROBE_DEFER, i.MX6 PCI driver should
> NOT print error message, use dev_err_probe() to handle it.
>
> Signed-off-by: Anson Huang
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 35
>
On Mon, Aug 10, 2020 at 06:41:54PM +0100, Lad Prabhakar wrote:
> Hi All,
>
> This patch set adds PCIe instance to r8a7742 Soc dtsi.
> patches apply on-top of [1] + [2]
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/
> renesas-devel.git/log/?h=renesas-arm-dt-for-v5.10
> [2]
On Tue, Jun 23, 2020 at 09:48:51AM +0200, Flavio Suligoi wrote:
> This comment still refers to the old driver pathname,
> when all PCI drivers were located directly under the
> drivers/pci directory.
>
> Anyway the function name itself is enough, so we can
> remove the overabundant path
On Fri, Sep 04, 2020 at 11:38:48AM +0100, Lad Prabhakar wrote:
> Hi All,
>
> This patch series adds PCIe EP support to R8A774E1 SoC.
>
> patch 2/3 applies on top of [1] and patch 3/3 is dependent
> on series [2].
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/
>
On Tue, Sep 01, 2020 at 02:49:54PM +0200, Ansuel Smith wrote:
> Qsdk U-Boot can incorrectly leave the PCIe interface in an undefined
> state if bootm command is used instead of bootipq. This is caused by the
> not deinit of PCIe when bootm is called. Reset the PCIe before init
> anyway to fix this
On Fri, Aug 14, 2020 at 06:30:32PM +0100, Lad Prabhakar wrote:
> Hi All,
>
> This patch series adds support for PCIe EP nodes to Renesas r8a774a1,
> r8a774b1 and r8a774c0 SoC's.
>
> Patches are based on top of [1].
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/
>
On Fri, Aug 14, 2020 at 06:30:32PM +0100, Lad Prabhakar wrote:
> Hi All,
>
> This patch series adds support for PCIe EP nodes to Renesas r8a774a1,
> r8a774b1 and r8a774c0 SoC's.
>
> Patches are based on top of [1].
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/
>
On Tue, Aug 18, 2020 at 03:37:39PM +0200, Greg Kroah-Hartman wrote:
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something different based on this.
>
> Cc: Lorenzo Piera
On Tue, Aug 04, 2020 at 01:57:42PM +0200, Pali Rohár wrote:
> Hi,
>
> we have some more improvements for PCIe aardvark controller (Armada 3720
> SOC - EspressoBIN and Turris MOX).
>
> The main improvement is that with these patches the driver can be compiled
> as a module, and can be reloaded at
On Tue, Aug 18, 2020 at 05:27:46PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> The current check will result in the multiple function device
> fails to initialize. So fix the check by masking out the
> multiple function bit.
>
> Fixes: 0b24134f7888 ("PCI: dwc: Add validation that PCIe
On Thu, Aug 27, 2020 at 09:29:59AM -0400, Jim Quinlan wrote:
> On Thu, Aug 27, 2020 at 2:35 AM Christoph Hellwig wrote:
> >
> > On Tue, Aug 25, 2020 at 10:40:27AM -0700, Florian Fainelli wrote:
> > > Hi,
> > >
> > > On 8/24/2020 12:30 PM, Jim Quinlan wrote:
> > >>
> > >> Patchset Summary:
> > >>
On Wed, Sep 02, 2020 at 11:47:56PM -0400, Samuel Dionne-Riel wrote:
> On Wed, 2 Sep 2020 17:01:19 +0100
> Lorenzo Pieralisi wrote:
>
> > On Tue, Sep 01, 2020 at 02:33:56PM -0400, Samuel Dionne-Riel wrote:
> >
> > Please print a pointer as a pointer and print b
On Tue, Sep 01, 2020 at 02:33:56PM -0400, Samuel Dionne-Riel wrote:
> On Tue, 1 Sep 2020 17:42:49 +0100
> Lorenzo Pieralisi wrote:
>
> > On Tue, Sep 01, 2020 at 04:37:42PM +0100, Marc Zyngier wrote:
> > > On 2020-09-01 04:45, Samuel Dionne-Riel wrote:
> > >
g...@huawei.com
>
> Zenghui Yu (2):
> ACPI/IORT: Drop the unused @ops of iort_add_device_replay()
> ACPI/IORT: Remove the unused inline functions
>
> drivers/acpi/arm64/iort.c | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
On the series:
Acked-by: Lorenzo Pieralisi
On Tue, Sep 01, 2020 at 04:37:42PM +0100, Marc Zyngier wrote:
> On 2020-09-01 04:45, Samuel Dionne-Riel wrote:
> > On Mon, 31 Aug 2020 10:27:37 +0100
> > Marc Zyngier wrote:
> > >
> > > Ah, so actually anything that *enables pcie* kills your system.
> > > Great investigative work!
> > >
> > > >
On Thu, Aug 27, 2020 at 01:20:40PM -0500, Bjorn Helgaas wrote:
[...]
> And I can't figure out what's special about tegra, rcar, and xilinx
> that makes them need it as well. Is there something I could grep for
> to identify them? Is there a way to convert them so they don't need
> it?
I think
e. No
> need to do it manually here.
>
> Signed-off-by: Nicolas Saenz Julienne
> Reviewed-by: Florian Fainelli
> ---
> drivers/pci/controller/pcie-brcmstb.c | 17 -
> 1 file changed, 17 deletions(-)
Acked-by: Lorenzo Pieralisi
> diff --git a/drivers/pci/co
On Wed, Aug 05, 2020 at 06:30:50PM -0500, Bjorn Helgaas wrote:
> On Wed, Aug 05, 2020 at 05:03:26PM -0500, Bjorn Helgaas wrote:
> > On Wed, Aug 05, 2020 at 10:39:28PM +0100, Lorenzo Pieralisi wrote:
> > > On Wed, Aug 05, 2020 at 03:43:58PM -0500, Bjorn Helgaas wrote:
> >
On Wed, Aug 05, 2020 at 03:43:58PM -0500, Bjorn Helgaas wrote:
> On Tue, Jun 16, 2020 at 06:26:54PM +0530, Bharat Kumar Gogada wrote:
> > - Add support for Versal CPM as Root Port.
> > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
> > block for CPM along with the
On Tue, Aug 04, 2020 at 02:04:30PM +0200, Geert Uytterhoeven wrote:
> The conversion to modern host bridge probing made the driver allocate
> its private data using devm_pci_alloc_host_bridge(), but forgot to
> remove the old allocation. Hence part of the driver initialization is
> done using the
On Fri, Jul 24, 2020 at 10:03:11AM +0200, Philipp Zabel wrote:
> On Mon, 2020-07-20 at 22:21 +0800, Anson Huang wrote:
> > Use module_platform_driver(), add module device table, author,
> > description and license to support module build, and
> > CONFIG_RESET_IMX7 is changed to default 'y' ONLY
[CCing IMX6 maintainers]
On Mon, Jul 20, 2020 at 10:22:01PM +0800, Anson Huang wrote:
> i.MX7 reset driver now supports module build and it is no longer
> built in by default, so i.MX PCI driver needs to select it explicitly
> due to it is NOT supporting loadable module currently.
>
>
On Mon, Jul 27, 2020 at 03:17:31PM +0800, Wei Hu wrote:
> Kdump could fail sometime on Hyper-V guest over Accelerated Network
> interface. This is because the retry in hv_pci_enter_d0() releases
> child device strurctures in hv_pci_bus_exit(). Although there is
> a second asynchronous device
On Thu, Jul 23, 2020 at 03:52:39PM +, Wei Hu wrote:
> > -Original Message-
> > From: Lorenzo Pieralisi
> > > Kdump could fail sometime on Hyper-V guest over Accelerated Network
> > > interface. This is because the retry in hv_pci_enter_d0() relies on an
On Sat, Jul 18, 2020 at 11:47:52AM +0800, Wei Hu wrote:
> Kdump could fail sometime on Hyper-V guest over Accelerated Network
> interface. This is because the retry in hv_pci_enter_d0() relies on
> an asynchronous host event arriving before the guest calls
> hv_send_resources_allocated(). Fix the
On Wed, Jul 22, 2020 at 04:33:02PM +0530, Kishon Vijay Abraham I wrote:
> TI's J721E SoC uses Cadence PCIe core to implement both RC mode
> and EP mode.
>
> The high level features are:
> *) Supports Legacy, MSI and MSI-X interrupt
> *) Supports upto GEN4 speed mode
> *) Supports SR-IOV
>
On Wed, Jul 22, 2020 at 04:33:03PM +0530, Kishon Vijay Abraham I wrote:
> Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits"
> property to configure the number of bits passed through from PCIe
> address to internal address in Inbound Address Translation register.
> This only used
On Mon, Jul 13, 2020 at 04:31:30PM +0530, Kishon Vijay Abraham I wrote:
> Certain platforms like TI's J721E using Cadence PCIe IP can perform only
> 32-bit accesses for reading or writing to Cadence registers. Convert all
> read and write accesses to 32-bit in Cadence PCIe driver in preparation
>
On Tue, Jul 21, 2020 at 10:57:13AM +0200, Pali Rohár wrote:
> On Wednesday 15 July 2020 17:21:08 Lorenzo Pieralisi wrote:
> > On Wed, Jul 15, 2020 at 02:17:26PM +0200, Pali Rohár wrote:
> > > On Monday 13 July 2020 12:23:25 Lorenzo Pieralisi wrote:
> > > > On Mon, Ju
On Sat, Jul 18, 2020 at 05:39:36PM +0800, Tiezhu Yang wrote:
> According to the datasheet of Loongson LS7A bridge chip, the old version
> of Loongson LS7A PCIE port has a wrong value about PCI class which is
> 0x06, the correct value should be 0x060400, this bug can be fixed by
> "dev->class =
On Fri, Jul 17, 2020 at 09:30:07PM +0800, Dejin Zheng wrote:
> The kernel test robot reported a compile warning,
>
> drivers/pci/controller/dwc/pci-keystone.c:1236:18: warning: variable 'res'
> is uninitialized when used here [-Wuninitialized]
>
> The commit c59a7d771134b5 ("PCI: dwc: Convert to
On Thu, Jul 16, 2020 at 10:19:06AM +0800, Tiezhu Yang wrote:
> According to the datasheet of Loongson LS7A bridge chip, the old version
> of Loongson LS7A PCIE port has a hardware bug about PCI class. As far as
> I know, the latest version has already fixed this bug.
Please define the bug and how
On Sat, Jul 11, 2020 at 03:47:33PM +0800, Dejin Zheng wrote:
> On Mon, Jul 06, 2020 at 04:58:47PM +0100, Lorenzo Pieralisi wrote:
> > On Tue, Jun 02, 2020 at 09:01:13AM -0600, Rob Herring wrote:
> >
> > [...]
> >
> > > > The other 2 error cases as we
On Wed, Jul 15, 2020 at 02:17:26PM +0200, Pali Rohár wrote:
> On Monday 13 July 2020 12:23:25 Lorenzo Pieralisi wrote:
> > On Mon, Jul 13, 2020 at 10:27:47AM +0200, Pali Rohár wrote:
> > > On Friday 10 July 2020 10:18:00 Lorenzo Pieralisi wrote:
> > > > On Thu, Ju
On Tue, Jul 14, 2020 at 03:37:51PM +0800, Tiezhu Yang wrote:
> On 06/12/2020 09:30 AM, Tiezhu Yang wrote:
> > Use DECLARE_PCI_FIXUP_EARLY instead of DECLARE_PCI_FIXUP_HEADER
> > for bridge_class_quirk() in pci-loongson.c, otherwise the fixup
> > has no effect.
> >
> > Fixes: 1f58cca5cf2b ("PCI:
On Thu, Jun 18, 2020 at 05:38:09PM +0900, Kunihiko Hayashi wrote:
> The misc interrupts consisting of PME, AER, and Link event, is handled
> by INTx handler, however, these interrupts should be also handled by
> MSI handler.
Define what you mean please.
> This adds the function
On Mon, Jul 13, 2020 at 04:50:03PM +0200, Pali Rohár wrote:
> On Monday 13 July 2020 12:23:25 Lorenzo Pieralisi wrote:
> > I will go over the thread again but I suspect I can merge the patch even
> > though I still believe there is work to be done to understand the issue
&g
On Tue, Jun 16, 2020 at 06:26:52PM +0530, Bharat Kumar Gogada wrote:
> - Adding support for Versal CPM as Root port.
> - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
> block for CPM along with the integrated bridge can function
> as PCIe Root Port.
> - Versal CPM uses
On Fri, Jul 10, 2020 at 09:16:57AM -0600, Rob Herring wrote:
> On Tue, Jun 16, 2020 at 6:57 AM Bharat Kumar Gogada
> wrote:
> >
> > - Add support for Versal CPM as Root Port.
> > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
> > block for CPM along with the integrated
On Mon, Jul 13, 2020 at 10:27:47AM +0200, Pali Rohár wrote:
> On Friday 10 July 2020 10:18:00 Lorenzo Pieralisi wrote:
> > On Thu, Jul 09, 2020 at 05:09:59PM +0200, Pali Rohár wrote:
> > > > I understand that but the bridge bus resource can be trimmed to just
> > >
On Wed, Jul 01, 2020 at 11:18:29AM +0900, Kunihiko Hayashi wrote:
[...]
> > > > > -static void uniphier_pcie_irq_handler(struct irq_desc *desc)
> > > > > +static void uniphier_pcie_misc_isr(struct pcie_port *pp, bool is_msi)
> > > > > {
> > > > > - struct pcie_port *pp =
On Fri, Jul 10, 2020 at 09:54:12AM +0900, Kunihiko Hayashi wrote:
> Hi Lorenzo,
>
> This 6/6 patch has just been covered with the following patch:
> https://patchwork.ozlabs.org/project/linux-pci/patch/20200708164013.5076-1-zhengdej...@gmail.com/
>
> As a result, my other patches conflict with
On Thu, Jul 09, 2020 at 05:09:59PM +0200, Pali Rohár wrote:
[...]
> > I understand that but the bridge bus resource can be trimmed to just
> > contain the root bus because that's the only one where there is a
> > chance you can enumerate a device.
>
> It is possible to register only root bridge
On Thu, Jul 09, 2020 at 02:22:08PM +0200, Pali Rohár wrote:
> On Thursday 09 July 2020 12:35:09 Lorenzo Pieralisi wrote:
> > On Thu, Jul 02, 2020 at 10:30:36AM +0200, Pali Rohár wrote:
> > > When there is no PCIe card connected and advk_pcie_rd_conf() or
> > > advk_pcie_
On Thu, Jul 02, 2020 at 10:30:36AM +0200, Pali Rohár wrote:
> When there is no PCIe card connected and advk_pcie_rd_conf() or
> advk_pcie_wr_conf() is called for PCI bus which doesn't belong to emulated
> root bridge, the aardvark driver throws the following error message:
>
> advk-pcie
On Thu, Jul 09, 2020 at 12:40:13AM +0800, Dejin Zheng wrote:
> Use devm_platform_ioremap_resource_byname() to simplify codes.
> it contains platform_get_resource_byname() and devm_ioremap_resource().
>
> Signed-off-by: Dejin Zheng
> Reviewed-by: Gustavo Pimentel
> Reviewed-by: Rob Herring
>
On Wed, Jul 08, 2020 at 11:56:14PM +0800, Dejin Zheng wrote:
> use devm_platform_ioremap_resource() to simplify code, it
> contains platform_get_resource() and devm_ioremap_resource().
>
> Signed-off-by: Dejin Zheng
> Reviewed-by: Rob Herring
> ---
> v1 -> v2:
> - rebase to pci/misc
On Thu, Jul 09, 2020 at 02:43:56PM +0800, Dinghao Liu wrote:
> pm_runtime_get_sync() increments the runtime PM usage counter even
> the call returns an error code. Thus a corresponding decrement is
> needed on the error handling path to keep the counter balanced.
>
> Fixes: 0df6150e7ceb ("PCI:
On Tue, May 26, 2020 at 09:55:31PM -0500, wu000...@umn.edu wrote:
> From: Qiushi Wu
>
> This function contained improvable implementation details according to
> exception handling.
> 1. pm_runtime_put() should be called after pm_runtime_get_sync() failed,
> because the reference count will be
On Mon, Jun 15, 2020 at 11:05:56PM +0200, Ansuel Smith wrote:
> This contains multiple fix for PCIe qcom driver.
> Some optional reset and clocks were missing.
> Fix a problem with no PARF programming that cause kernel lock on load.
> Add support to force gen 1 speed if needed. (due to hardware
On Tue, Jul 07, 2020 at 04:02:44PM +0200, Pali Rohár wrote:
> On Tuesday 07 July 2020 14:53:11 Lorenzo Pieralisi wrote:
> > On Fri, Jun 19, 2020 at 12:56:18PM +0200, Pali Rohár wrote:
> > > Hello Lorenzo! Could you please review this patch?
> > >
> > > On Mon
On Mon, Jun 15, 2020 at 11:05:56PM +0200, Ansuel Smith wrote:
> This contains multiple fix for PCIe qcom driver.
> Some optional reset and clocks were missing.
> Fix a problem with no PARF programming that cause kernel lock on load.
> Add support to force gen 1 speed if needed. (due to hardware
On Fri, Jun 19, 2020 at 12:56:18PM +0200, Pali Rohár wrote:
> Hello Lorenzo! Could you please review this patch?
>
> On Monday 01 June 2020 15:03:15 Pali Rohár wrote:
> > Most callers of config read do not check for return value. But most of the
> > ones that do, checks for error indication in
On Wed, May 27, 2020 at 12:01:10AM +0800, Dejin Zheng wrote:
> use devm_platform_ioremap_resource() to simplify code, it
> contains platform_get_resource() and devm_ioremap_resource().
>
> Signed-off-by: Dejin Zheng
> ---
> drivers/pci/controller/dwc/pci-exynos.c | 4 +---
>
On Tue, Jul 07, 2020 at 12:31:17PM +0100, Lorenzo Pieralisi wrote:
> On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote:
> > Use devm_platform_ioremap_resource_byname() to simplify codes.
> > it contains platform_get_resource_byname() and devm_ioremap_resource().
>
On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote:
> Use devm_platform_ioremap_resource_byname() to simplify codes.
> it contains platform_get_resource_byname() and devm_ioremap_resource().
>
> Signed-off-by: Dejin Zheng
> ---
> v1 -> v2:
> - Discard changes to the file
On Sun, Jun 07, 2020 at 05:31:33PM +0800, Dinghao Liu wrote:
> pm_runtime_get_sync() increments the runtime PM usage counter even
> the call returns an error code. Thus a corresponding decrement is
> needed on the error handling path to keep the counter balanced.
>
> Signed-off-by: Dinghao Liu
>
On Tue, Jul 07, 2020 at 01:50:00PM +0800, Dinghao Liu wrote:
> pm_runtime_get_sync() increments the runtime PM usage counter even
> it returns an error code. Thus a pairing decrement is needed on
> the error handling path to keep the counter balanced.
>
> Signed-off-by: Dinghao Liu
> ---
>
>
On Tue, Jun 02, 2020 at 09:01:13AM -0600, Rob Herring wrote:
[...]
> > > In fact, I think its error handling is clear enough, It just goes
> > > wrong
> > > in three places, as follows:
> > >
> > > void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
> > >
On Thu, Apr 02, 2020 at 08:01:59PM +0530, Sriram Dash wrote:
[...]
> > So the patch itself is correct though the commit log has to be fixed. You
> > should
> > also check if all the endpoint controller drivers existing currently
> > provides
> > epc_features.
>
> At the moment, there is no
On Wed, May 20, 2020 at 04:47:56PM +0800, Dinghao Liu wrote:
> pm_runtime_get_sync() increments the runtime PM usage counter even
> it returns an error code. Thus a pairing decrement is needed on
> the error handling path to keep the counter balanced.
>
> Signed-off-by: Dinghao Liu
> ---
>
On Wed, May 20, 2020 at 05:02:53PM +0800, Dinghao Liu wrote:
> pm_runtime_get_sync() increments the runtime PM usage counter even
> it returns an error code. Thus a pairing decrement is needed on
> the error handling path to keep the counter balanced.
>
> Signed-off-by: Dinghao Liu
> ---
>
On Sat, Mar 14, 2020 at 11:30:27AM +0800, Xiaowei Bao wrote:
> Add the PCIe EP multiple PF support for DWC and Layerscape, add
> the doorbell MSIX function for DWC, use list to manage the PF of
> one PCIe controller, and refactor the Layerscape EP driver due to
> some platforms difference.
>
>
On Wed, May 20, 2020 at 04:58:37PM +0800, Dinghao Liu wrote:
> pm_runtime_get_sync() increments the runtime PM usage counter even
> it returns an error code. Thus a pairing decrement is needed on
> the error handling path to keep the counter balanced.
>
> Signed-off-by: Dinghao Liu
> ---
>
On Thu, Jun 04, 2020 at 10:16:43PM -0500, Navid Emamdoost wrote:
> Calling pm_runtime_get_sync increments the counter even in case of
> failure, causing incorrect ref count. Call pm_runtime_put if
> pm_runtime_get_sync fails.
>
> Signed-off-by: Navid Emamdoost
> ---
>
On Mon, Feb 17, 2020 at 12:08:48PM +, John Garry wrote:
> > >
> > > Right, and even worse is that it relies on the port driver even
> > > existing at all.
> > >
> > > All this iommu group assignment should be taken outside device
> > > driver probe paths.
> > >
> > > However we could still
> Reported-by: Will Deacon
> Suggested-by: Ard Biesheuvel
> Signed-off-by: Nick Desaulniers
> ---
> Changes V1 -> V2:
> * Just fix one of the two warnings, specific to arm64.
> * Put warning in commit message.
>
> arch/arm64/include/asm/acpi.h | 5 +++--
> 1 file ch
On Tue, Jun 02, 2020 at 09:10:33PM +0800, YueHaibing wrote:
> WARNING: unmet direct dependencies detected for PCIE_DW_EP
> Depends on [n]: PCI [=y] && PCI_ENDPOINT [=n]
> Selected by [y]:
> - PCIE_UNIPHIER_EP [=y] && PCI [=y] && (ARCH_UNIPHIER || COMPILE_TEST [=y])
> && OF [=y] && HAS_IOMEM
On Fri, May 29, 2020 at 08:05:18PM +0200, Thierry Reding wrote:
> On Thu, May 21, 2020 at 10:47:09AM +0800, Dinghao Liu wrote:
> > pm_runtime_get_sync() increments the runtime PM usage counter even
> > when it returns an error code. Thus a pairing decrement is needed on
> > the error handling path
On Thu, May 21, 2020 at 11:13:49AM +0800, Dinghao Liu wrote:
> pm_runtime_get_sync() increments the runtime PM usage counter even
> when it returns an error code. Thus a pairing decrement is needed on
> the error handling path to keep the counter balanced.
>
> Signed-off-by: Dinghao Liu
> ---
>
On Wed, May 20, 2020 at 11:39:08PM +0530, Vidya Sagar wrote:
> Thanks for pushing a patch to fix it. I've been under the wrong assumption
> that a failing pm_runtime_get_sync() wouldn't increment the usage counter.
> With Thierry's and Bjorn's comments addressed
>
> Acked-by: Vidya Sagar
On Thu, May 14, 2020 at 09:03:19PM +0900, Kunihiko Hayashi wrote:
> This series adds PCIe endpoint controller driver for Socionext UniPhier
> SoCs. This controller is based on the DesignWare PCIe core.
>
> This driver supports Pro5 SoC only, so Pro5 needs multiple clocks and
> resets in
On Mon, May 25, 2020 at 11:43:19AM -0500, Gustavo A. R. Silva wrote:
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elements for that array. For example:
>
> struct
On Sun, May 24, 2020 at 10:37:49PM +0100, Lad Prabhakar wrote:
> Hi All,
>
> This patch series adds support for HSUSB, USB2.0 and USB3.0 to
> R8A7742 SoC DT.
>
> This patch series applies on-top of [1].
>
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=288491
I think
On Tue, May 26, 2020 at 09:21:57PM +0100, Will Deacon wrote:
> Hi Lorenzo, Hanjun, [+Nick]
>
> On Thu, May 21, 2020 at 06:37:38PM +0100, Lorenzo Pieralisi wrote:
> > On Thu, May 21, 2020 at 11:09:53AM +0100, Will Deacon wrote:
> > > Hi folks,
> > >
>
On Thu, May 14, 2020 at 09:03:20PM +0900, Kunihiko Hayashi wrote:
> Add DT bindings for PCIe controller implemented in UniPhier SoCs
> when configured in endpoint mode. This controller is based on
> the DesignWare PCIe core.
>
> Signed-off-by: Kunihiko Hayashi
> ---
>
rt.c | 9 -
> 1 file changed, 9 deletions(-)
Acked-by: Lorenzo Pieralisi
If we miss v5.8 (which I think it is likely, even though this patch is
just removing dead code so it is safe at this stage) I will resend it
for v5.9 - not a problem.
Lorenzo
> diff --git a/drivers/acpi
On Sat, May 23, 2020 at 12:36:56AM +0200, Thomas Bogendoerfer wrote:
> On Fri, May 22, 2020 at 04:22:11PM +0100, Lorenzo Pieralisi wrote:
> > On Fri, May 22, 2020 at 04:25:50PM +0200, Thomas Bogendoerfer wrote:
> > > On Thu, May 14, 2020 at 09:16:41PM +0800, Jiaxun Yang wrote:
em_bus quirk and host bus quirk.
> ---
> drivers/pci/controller/Kconfig| 10 ++
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pci-loongson.c | 249 ++
> 3 files changed, 260 insertions(+)
> create mode 100644 drivers
On Fri, May 22, 2020 at 04:25:50PM +0200, Thomas Bogendoerfer wrote:
> On Thu, May 14, 2020 at 09:16:41PM +0800, Jiaxun Yang wrote:
> > We can now enable generic PCI driver in Kconfig, and remove legacy
> > PCI driver code.
> >
> > Radeon vbios quirk is moved to the platform folder to fit the
> >
On Tue, May 19, 2020 at 07:33:04PM -0700, Alan Mikhak wrote:
> Hi Lorenzo,
>
> I came across this issue when implementing a Linux NVMe endpoint function
> driver under the Linux PCI Endpoint Framework:
> https://lwn.net/Articles/804369/
>
> I needed to map up to 128GB of host memory using a
On Fri, May 22, 2020 at 09:32:10PM +0800, Jiaxun Yang wrote:
[...]
> >> Is it possible to let this series go into next tree soon?
> >>
> >> As LS7A dts patch would depend on this series, and I want to
> >> make the whole LS7A basic support as a part of 5.8 release.
> >
> >I think you have all
gt; > > On Tue, May 19, 2020 at 10:08:54PM +, Gustavo Pimentel wrote:
> > > > > On Tue, May 19, 2020 at 15:58:16, Lorenzo Pieralisi
> > > > > wrote:
> > > > >
> > > > > > On Tue, May 19, 2020 at 07:25:02PM +053
On Wed, May 20, 2020 at 07:57:29PM +0800, Jiaxun Yang wrote:
>
>
> 于 2020年5月14日 GMT+08:00 下午9:16:38, Jiaxun Yang 写到:
> >This controller can be found on Loongson-2K SoC, Loongson-3
> >systems with RS780E/LS7A PCH.
> >
> >The RS780E part of code was previously located at
>
On Tue, May 19, 2020 at 04:11:20PM +0100, Lad Prabhakar wrote:
> Fix allocation of epc windows with the correct size, this also fix smatch
> warning:
>
> drivers/pci/endpoint/pci-epc-mem.c:65 pci_epc_multi_mem_init()
> warn: double check that we're allocating correct size: 4 vs 112
>
> Fixes:
On Fri, Dec 20, 2019 at 03:35:50PM +0530, Kishon Vijay Abraham I wrote:
> No functional change. Get "struct pcie_port *" from private data
> pointer of "struct irq_domain" in dw_pcie_irq_domain_free() to make
> it look similar to how "struct pcie_port *" is obtained in
> dw_pcie_irq_domain_alloc()
On Thu, May 21, 2020 at 02:39:58AM +, Michael Kelley wrote:
> From: Lorenzo Pieralisi Sent: Monday, May 11,
> 2020 4:22 AM
> >
> > On Thu, May 07, 2020 at 01:01:26PM +0800, Wei Hu wrote:
> > > This series better handles some PCI HyperV error cases in general
>
On Thu, May 21, 2020 at 11:09:53AM +0100, Will Deacon wrote:
> Hi folks,
>
> I just tried booting the arm64 for-kernelci branch under QEMU (version
> 4.2.50 (v4.2.0-779-g4354edb6dcc7)) with UBSAN enabled, and I see a
> couple of NULL pointer dereferences reported at boot. I think they're
> both
>
> Fix iort_get_id_mapping_index() by checking for an overflow interrupt
> and mapping count.
>
> Fixes: 24e516049360 ("ACPI/IORT: Add support for PMCG")
>
> Acked-by: Lorenzo Pieralisi
> Reviewed-by: Hanjun Guo
> Signed-off-by: Tuan Phan
> ---
> v1 -> v2:
&g
s too late for v5.8 but this patch
is ready to be merged (minus the nits I have just mentioned).
Lorenzo
> Acked-by: Lorenzo Pieralisi
> Reviewed-by: Hanjun Guo
> Signed-off-by: Tuan Phan
> ---
> v1 -> v2:
> - Use pmcg node to detect wired base overflow interrupt.
>
> v2
On Tue, May 19, 2020 at 10:08:54PM +, Gustavo Pimentel wrote:
[...]
> > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > > b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > > index 42fbfe2a1b8f..a29396529ea4 100644
> > > > > > ---
On Tue, May 19, 2020 at 10:38:39PM +0530, Vidya Sagar wrote:
[...]
> > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > > b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > > index 42fbfe2a1b8f..a29396529ea4 100644
> > > > > > ---
On Tue, May 19, 2020 at 07:25:02PM +0530, Vidya Sagar wrote:
>
>
> On 18-May-20 9:24 PM, Lorenzo Pieralisi wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Wed, May 13, 2020 at 05:35:08PM -0500, Bjorn Helgaas wrote:
&
On Wed, May 13, 2020 at 05:35:08PM -0500, Bjorn Helgaas wrote:
> [+cc Alan; please cc authors of relevant commits,
> updated Andrew's email address]
>
> On Thu, May 14, 2020 at 12:38:55AM +0530, Vidya Sagar wrote:
> > commit 9e73fa02aa009 ("PCI: dwc: Warn if MEM resource size exceeds max for
> >
On Fri, May 08, 2020 at 06:36:42PM +0530, Kishon Vijay Abraham I wrote:
> This series is a result of comments given by Rob Herring @ [1].
> Patch series changes the DT bindings and makes the corresponding driver
> changes.
>
> Changes from v2:
> 1) Changed the order of patches (no solid reason.
On Thu, May 14, 2020 at 07:24:37PM +0530, Vidya Sagar wrote:
> Fix flag in PCIe controllers device-tree nodes 'ranges' property to correctly
> represent 64-bit resources.
>
> Signed-off-by: Vidya Sagar
> ---
> V2:
> * Extended the change to cover other controllers as well
>
>
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