Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
On Friday 03 March 2017 12:20 PM, Rob Herring wrote:
On Thu, Mar 02, 2017 at 05:48:36AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 76
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: Dikshit N
---
drivers/perf/hisilicon
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 489
2 files changed, 490 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch/arm64/boot/dts/hisilicon
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d662a83..9bb2ddb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5875,6
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 +++
.../devicetree
used to access registers of L3 cache and MN.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting.
drivers: perf: hisi
interval of 10 seconds is used for the hrtimer.
Signed-off-by: Dikshit N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 47 ++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 82
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 771
drivers/perf/hisilicon/djtag.h | 40 +++
4 files changed, 813 insertions(+)
create mode
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..5b988f5 100644
--- a
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644 Documentation
On Friday 24 February 2017 08:34 AM, Anurup M wrote:
+static int hisi_mn_init_irqs_fdt(struct device *dev,
+struct hisi_pmu *mn_pmu)
+{
+struct hisi_mn_data *mn_data = mn_pmu->hwmod_data;
+struct hisi_djtag_client *client = mn_data->client;
+int irq = -1, nu
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
On Tuesday 21 February 2017 05:39 PM, Will Deacon wrote:
On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you
Sorry for delay in reply.
On Tuesday 21 February 2017 05:33 PM, Mark Rutland wrote:
On Tue, Feb 21, 2017 at 05:19:58PM +0530, Anurup M wrote:
On Monday 20 February 2017 04:59 PM, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:22PM -0500, Anurup M wrote:
+ /* Clear
On Monday 20 February 2017 04:59 PM, Mark Rutland wrote:
Hi,
On Sun, Feb 19, 2017 at 01:51:22PM -0500, Anurup M wrote:
+static irqreturn_t hisi_pmu_mn_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *mn_pmu = dev_id;
+ struct hisi_mn_data *mn_data = mn_pmu->hwmod_d
Adding Marc.
On Monday 20 February 2017 04:39 PM, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you mean by this?
I don't understand what is meant
1. Add nodes for hip07 L3 cache to support uncore events.
2. Add nodes for hip07 support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 94 ++--
1 file changed, 64 insertions(+), 30 deletions
MN1 support IRQ for counter overflow handling.
MN1 use the index 26 of the Fabric Totem IRQ.
The interrupt parent will be Hisilicon Mbigen-v2.
The interrupt type is LPI.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_mn.c | 121
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 773
drivers/perf/hisilicon/djtag.h | 40 +++
4 files changed, 815 insertions(+)
create mode
N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 44 +++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 95
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17 ++
3 files changed, 156 insertions(+)
diff --git a/drivers/perf
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..5b988f5 100644
--- a
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 490
2 files changed, 491 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 +
.../devicetree
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d662a83..9bb2ddb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5875,6
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644 Documentation
M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting.
drivers: perf: hisi: Update Kconfig for Hisilicon PMU support
drivers: perf
Hello Dear.
My name is Miss Naya M Makhlouf I am 19yrs Old girl from Syrian, I am the only
child of Hassan Mohammed Makhlouf, who was a business man and deals in Crude
oil and gold and who was killed in 2012 and by all investigation it was
planned by my uncle ( Mr Rami Makhlouf) who took
On Tuesday 10 January 2017 11:13 PM, Mark Rutland wrote:
Hi,
On Mon, Jan 02, 2017 at 01:47:52AM -0500, Anurup M wrote:
ToDo:
1) The counter overflow handling is currently unsupported in this
patch series.
From a quick scan of the patches, I see mention of an interrupt in a
comment the
On Tuesday 10 January 2017 11:25 PM, Mark Rutland wrote:
On Mon, Jan 02, 2017 at 01:49:37AM -0500, Anurup M wrote:
+The Hisilicon SoC HiP05/06/07 chips consist of various independent system
+device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN).
+These PMU devices are independen
Am 09.01.2017 um 09:08 schrieb Johannes Berg:
> Does it make sense to implement the two in separate layers though?
>
> Clearly, this part needs to be implemented in the bridge layer due to
> the snooping knowledge, but the code is very similar to what mac80211
> has now.
Does the bridge always kn
Am 06.01.2017 um 14:54 schrieb Johannes Berg:
>
>> The bridge layer can use IGMP snooping to ensure that the multicast
>> stream is only transmitted to clients that are actually a member of
>> the group. Can the mac80211 feature do the same?
>
> No, it'll convert the packet for all clients that a
On Wednesday 04 January 2017 04:29 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:21AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by
On Wednesday 04 January 2017 04:26 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:03AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 72
1 file changed, 72
CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 53
drivers/perf/hisilicon/hisi_uncore_pmu.c | 39 +++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 21 +
3 fil
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c.c | 556 +++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 326
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 501
2 files changed, 502 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 ++
.../devicetree
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..2a5435b 100644
--- a
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 731
drivers/perf/hisilicon/djtag.h | 39 +++
4 files changed, 772 insertions(+)
create mode
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..fca339e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5725,6
series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (7):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings
On Monday 19 December 2016 10:07 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:59AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup
On Monday 19 December 2016 10:01 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:19AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm
CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 21
3 files ch
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 78
1 file changed, 78
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 516
2 files changed, 517 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 729
drivers/perf/hisilicon/djtag.h | 39 +++
4 files changed, 770 insertions(+)
create mode
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c.c | 572 +++
drivers/perf
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..ce86c07 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5725,6
Update Kconfig for Hip05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..2befa55 100644
--- a
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 ++
.../devicetree
djtag
hw version.
- use devm_kzalloc.
- Remove DDRC changes in this series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (7
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation
.
Anurup M (7):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HIP05/06/07 PMU event
counting.
perf: hisi: Update Kconfig for Hisilicon PMU support
perf: hisi: Add
On 11/13/2016 09:04 PM, Boris Ostrovsky wrote:
> On 11/12/2016 05:05 PM, M. Vefa Bicakci wrote:
>> On 11/10/2016 06:31 PM, Boris Ostrovsky wrote:
>>> On 11/10/2016 10:05 AM, Charles (Chas) Williams wrote:
>>>>
>>>> On 11/10/2016 09:02 AM, Boris Ostrovsky w
On 11/10/2016 01:50 PM, Charles (Chas) Williams wrote:
>
>
> On 11/09/2016 10:57 PM, M. Vefa Bicakci wrote:
>> [0.002000] mvb: CPU: Physical Processor ID: 0
>> [0.002000] mvb: CPU: Processor Core ID: 0
>> [0.002000] mvb: identify_cpu:1112: c: 880013b0
On 11/10/2016 06:31 PM, Boris Ostrovsky wrote:
> On 11/10/2016 10:05 AM, Charles (Chas) Williams wrote:
>>
>>
>> On 11/10/2016 09:02 AM, Boris Ostrovsky wrote:
>>> On 11/10/2016 06:13 AM, Thomas Gleixner wrote:
>>>> On Thu, 10 Nov 2016, M. Vefa Bicakc
On Wednesday 09 November 2016 02:36 PM, John Garry wrote:
I'd suggest requiring #address-cells=<1> and #size-cells=<0> in the
master
node, and listing the children by reg property. If the address is not
easily expressed as a single integer, use a larger #address-cells
value.
We already have
On Thursday 10 November 2016 03:10 AM, Arnd Bergmann wrote:
On Wednesday, November 9, 2016 9:58:38 AM CET Anurup M wrote:
I also see that the compatible strings have the version included in
them, and you can probably drop them by requiring them only in the
fallback:
compatible
This patch fixes block comment coding style warnings.
And added new line after variable declaration.
Signed-off-by: Y M Patil
---
drivers/staging/rtl8192e/dot11d.c | 2 +-
drivers/staging/rtl8192e/rtl819x_BAProc.c | 3 ++-
drivers/staging/rtl8192e/rtl819x_HTProc.c | 2 +-
drivers
s differ use the package information from the ACPI/MP tables so
> the existing logical package map just works.
>
> Reported-by: "Charles (Chas) Williams" ,
> Reported-by: M. Vefa Bicakci
> Signed-off-by: Thomas Gleixner
Hello Thomas and Sebastian,
Sorry for the delay
On Tuesday 08 November 2016 08:40 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 1:49:43 PM CET John Garry wrote:
Hi Arnd,
Thanks for the reference.
I think the i2c interface doesn't fully satisfy our requirements as we
need more than just a slave bus address when accessing the slave
On Tuesday 08 November 2016 08:38 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 7:16:30 PM CET Anurup M wrote:
If these are backwards compatible, just mark them as compatible in DT,
e.g. hip06 can use
compatible = "hisilicon,hip06-cpu-djtag-v1", "hisilicon,hip
On Tuesday 08 November 2016 05:15 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 11:23:35 AM CET John Garry wrote:
On 07/11/2016 20:08, Arnd Bergmann wrote:
On Monday, November 7, 2016 2:15:10 PM CET John Garry wrote:
Hi Arnd,
The new bus type tries to model the djtag in a similar wa
On Tuesday 08 November 2016 05:13 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 1:08:31 PM CET Anurup M wrote:
On Tuesday 08 November 2016 12:32 PM, Tan Xiaojun wrote:
On 2016/11/7 21:26, Arnd Bergmann wrote:
On Wednesday, November 2, 2016 11:42:46 AM CET Anurup M wrote:
From
On Tuesday 08 November 2016 12:32 PM, Tan Xiaojun wrote:
On 2016/11/7 21:26, Arnd Bergmann wrote:
On Wednesday, November 2, 2016 11:42:46 AM CET Anurup M wrote:
From: Tan Xiaojun
The Hisilicon Djtag is an independent component which connects
with some other components in the
On 11/4/2016 10:06 PM, Salil Mehta wrote:
> From: Shaobo Xu
>
> IB core has implemented the calculation of GIDs and the management
> of GID tables, and it is now responsible to supply query function
> for GIDs. So the calculation of GIDs and the management of GID
> tables in the RoCE driver is
On 11/4/2016 10:06 PM, Salil Mehta wrote:
> From: Lijun Ou
>
> In old code, It only added the interface for querying non-specific
> QP. This patch mainly adds an interface for querying QP1.
>
> Signed-off-by: Lijun Ou
> Reviewed-by: Wei Hu (Xavier)
> Signed-off-by: Salil Mehta
> ---
> dri
Ahoj.
Dobry vecer a jak se mas? Jen rychly jedno, je tu oficialni prilezitosti
bych chtel diskutovat s vami soukrome.
Ocenil bych vasi rychlou reakci tady na mem osobnim soukromeho e-mailu
nize pro dalsi komunikaci.
S pratelskym pozdravem,
Paní Ko May Leung
email: kleung...@gmail.com
On 11/02/2016 08:23 PM, Sebastian Andrzej Siewior wrote:
> On 2016-11-01 13:15:53 [+0300], M. Vefa Bicakci wrote:
>> Hello Sebastian,
>
> Hi,
>
>> The patch fixes the kernel oops for me.
>>
>> I am using a custom 4.8.5-based kernel on Qubes OS R3.2, which is ba
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..839abc8 100644
--- a/MAINTAINERS
+++ b
1. Update Kconfig for Hip05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..da8dd97 100644
. Routines to enable/disable/add/del/start/stop hardware
event counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Makefile| 1 +
drivers/perf
From: Tan Xiaojun
1) Add Hisilicon HiP05/06/07 CPU and ALGSUB system controller dts
bindings.
2) Add Hisilicon Djtag dts binding.
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../bindings/arm/hisilicon/hisilicon.txt | 82
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/pmu.txt | 127 +
1 file changed, 127 insertions
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node, DDR cntroller etc. These events are
all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
attribute group for showing the available CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++
drivers/perf
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
3. Add nodes for hip06 DDRC to support uncore events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
arch/arm64/boot/dts
-off-by: Tan Xiaojun
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile| 1 +
drivers/soc/hisilicon/Kconfig | 12 +
drivers/soc/hisilicon/Makefile | 1 +
drivers/soc/hisilicon/djtag.c | 639
1. Add support for counting Hisilicon DDRC
statistics events in perf.
2. Support a total of 13 statistics events.
3. Events listed in /sys/devices//
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/Makefile | 2
event format is
-e "hisi_mn2/read_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 571
drivers/perf/hisilicon/hisi_uncore_mn.h |
perf tool can list the event names.
ToDo:
1) The counter overflow handling is currently unsupported in this
patch series.
2) ACPI support.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
Documentation: perf: hisi: Documentation for HIP05/06/07
> On 2016-10-27 15:00:32 [-0400], Charles (Chas) Williams wrote:
>>
>> [snip]
>>
>> But sometimes the topology info is correct and if I get lucky, the
>> package id could be valid for all the CPU's. Given the behavior,
>> I have seen so far it makes me thing the RAPL isn't being emulated.
>> So ev
From: Kyyaly M.
Sent: 30 October 2016 00:12
To: Kyyaly M.
Subject: RE: Is This Email Still Working.
Transaction offer contact me---> jonathan_symond...@outlook.com for
details.
Ahoj.
Dobry vecer a jak se mas? Jen rychly jedno, je tu oficialni prilezitosti
bych chtel diskutovat s vami soukrome.
Ocenil bych vasi rychlou reakci tady na mem osobnim soukromeho e-mailu
nize pro dalsi komunikaci.
S pratelskym pozdravem,
Paní Ko May Leung
email: kmyln...@gmail.com
M
On 2016-08-08 15:32, dirk.eib...@gdsys.cc wrote:
From: Dirk Eibach
sc16is7xx_port_irq() is laid out as an endless loop. It will exit only
when there is no more interrupt left to service. This not common
practice.
In our case it lead to some strange hangup situation when there was an
unexpected
Hi,
I have two processors on the same die. One is an ARM processor running
linux and another is a non-ARM processor running linux operating
system (Proprietary Proc). We do not have any medium like Network
Interface or PCI or USB running between the two processors, except 1GB
of shared memory.
W
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