cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 771
drivers/perf/hisilicon/djtag.h | 40 +++
4 files changed, 813 insertions(+)
create mode
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..5b988f5 100644
From: Tan Xiaojun <tanxiao...@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644 Documentation
On Friday 24 February 2017 08:34 AM, Anurup M wrote:
+static int hisi_mn_init_irqs_fdt(struct device *dev,
+struct hisi_pmu *mn_pmu)
+{
+struct hisi_mn_data *mn_data = mn_pmu->hwmod_data;
+struct hisi_djtag_client *client = mn_data->client;
+int irq = -1, nu
On Friday 24 February 2017 08:34 AM, Anurup M wrote:
+static int hisi_mn_init_irqs_fdt(struct device *dev,
+struct hisi_pmu *mn_pmu)
+{
+struct hisi_mn_data *mn_data = mn_pmu->hwmod_data;
+struct hisi_djtag_client *client = mn_data->client;
+int irq = -1, nu
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
Dear Sir,
Did you recieved my mail?
I have sent it twice without a response.
Mr Masella Giuseppe
On Tuesday 21 February 2017 05:39 PM, Will Deacon wrote:
On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you
On Tuesday 21 February 2017 05:39 PM, Will Deacon wrote:
On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you
Sorry for delay in reply.
On Tuesday 21 February 2017 05:33 PM, Mark Rutland wrote:
On Tue, Feb 21, 2017 at 05:19:58PM +0530, Anurup M wrote:
On Monday 20 February 2017 04:59 PM, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:22PM -0500, Anurup M wrote:
+ /* Clear
Sorry for delay in reply.
On Tuesday 21 February 2017 05:33 PM, Mark Rutland wrote:
On Tue, Feb 21, 2017 at 05:19:58PM +0530, Anurup M wrote:
On Monday 20 February 2017 04:59 PM, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:22PM -0500, Anurup M wrote:
+ /* Clear
On Monday 20 February 2017 04:59 PM, Mark Rutland wrote:
Hi,
On Sun, Feb 19, 2017 at 01:51:22PM -0500, Anurup M wrote:
+static irqreturn_t hisi_pmu_mn_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *mn_pmu = dev_id;
+ struct hisi_mn_data *mn_data = mn_pmu->hwmod_d
On Monday 20 February 2017 04:59 PM, Mark Rutland wrote:
Hi,
On Sun, Feb 19, 2017 at 01:51:22PM -0500, Anurup M wrote:
+static irqreturn_t hisi_pmu_mn_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *mn_pmu = dev_id;
+ struct hisi_mn_data *mn_data = mn_pmu->hwmod_d
Adding Marc.
On Monday 20 February 2017 04:39 PM, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you mean by this?
I don't understand what is meant here
Adding Marc.
On Monday 20 February 2017 04:39 PM, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you mean by this?
I don't understand what is meant here
1. Add nodes for hip07 L3 cache to support uncore events.
2. Add nodes for hip07 support uncore events.
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 94 ++-
1. Add nodes for hip07 L3 cache to support uncore events.
2. Add nodes for hip07 support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 94 ++--
1 file changed, 64 insertions(+), 30 deletions
MN1 support IRQ for counter overflow handling.
MN1 use the index 26 of the Fabric Totem IRQ.
The interrupt parent will be Hisilicon Mbigen-v2.
The interrupt type is LPI.
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
MN1 support IRQ for counter overflow handling.
MN1 use the index 26 of the Fabric Totem IRQ.
The interrupt parent will be Hisilicon Mbigen-v2.
The interrupt type is LPI.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_mn.c | 121
ed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 773
drivers/perf/hisilicon/djtag.h | 40 +++
4 files changed, 815 insertions(+)
create mode
N <dikshi...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 44 +++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 95
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17 ++
3 files
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --
is -e "hisi_mn_2/read_req/"
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 490
2 files c
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Ga
N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 44 +++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 95
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17 ++
3 files changed, 156 insertions(+)
diff --git a/drivers/perf
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..5b988f5 100644
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 490
2 files changed, 491 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
.../devicetree/
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 +
.../devicetree
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M <anuru...@huawei.com>
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d662a83..9bb2ddb 100644
--- a/MAINTAINERS
From: Tan Xiaojun <tanxiao...@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d662a83..9bb2ddb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5875,6
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644 Documentation
M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting.
drivers: perf: hisi: Update Kconfig for Hisilicon PMU support
drivers: perf
M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting.
drivers: perf: hisi: Update Kconfig for Hisilicon PMU support
drivers: perf
Hello Dear.
My name is Miss Naya M Makhlouf I am 19yrs Old girl from Syrian, I am the only
child of Hassan Mohammed Makhlouf, who was a business man and deals in Crude
oil and gold and who was killed in 2012 and by all investigation it was
planned by my uncle ( Mr Rami Makhlouf) who took
Hello Dear.
My name is Miss Naya M Makhlouf I am 19yrs Old girl from Syrian, I am the only
child of Hassan Mohammed Makhlouf, who was a business man and deals in Crude
oil and gold and who was killed in 2012 and by all investigation it was
planned by my uncle ( Mr Rami Makhlouf) who took
On Tuesday 10 January 2017 11:13 PM, Mark Rutland wrote:
Hi,
On Mon, Jan 02, 2017 at 01:47:52AM -0500, Anurup M wrote:
ToDo:
1) The counter overflow handling is currently unsupported in this
patch series.
From a quick scan of the patches, I see mention of an interrupt in a
comment
On Tuesday 10 January 2017 11:13 PM, Mark Rutland wrote:
Hi,
On Mon, Jan 02, 2017 at 01:47:52AM -0500, Anurup M wrote:
ToDo:
1) The counter overflow handling is currently unsupported in this
patch series.
From a quick scan of the patches, I see mention of an interrupt in a
comment
On Tuesday 10 January 2017 11:25 PM, Mark Rutland wrote:
On Mon, Jan 02, 2017 at 01:49:37AM -0500, Anurup M wrote:
+The Hisilicon SoC HiP05/06/07 chips consist of various independent system
+device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN).
+These PMU devices are independent
On Tuesday 10 January 2017 11:25 PM, Mark Rutland wrote:
On Mon, Jan 02, 2017 at 01:49:37AM -0500, Anurup M wrote:
+The Hisilicon SoC HiP05/06/07 chips consist of various independent system
+device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN).
+These PMU devices are independent
Am 09.01.2017 um 09:08 schrieb Johannes Berg:
> Does it make sense to implement the two in separate layers though?
>
> Clearly, this part needs to be implemented in the bridge layer due to
> the snooping knowledge, but the code is very similar to what mac80211
> has now.
Does the bridge always
Am 09.01.2017 um 09:08 schrieb Johannes Berg:
> Does it make sense to implement the two in separate layers though?
>
> Clearly, this part needs to be implemented in the bridge layer due to
> the snooping knowledge, but the code is very similar to what mac80211
> has now.
Does the bridge always
Am 06.01.2017 um 14:54 schrieb Johannes Berg:
>
>> The bridge layer can use IGMP snooping to ensure that the multicast
>> stream is only transmitted to clients that are actually a member of
>> the group. Can the mac80211 feature do the same?
>
> No, it'll convert the packet for all clients that
Am 06.01.2017 um 14:54 schrieb Johannes Berg:
>
>> The bridge layer can use IGMP snooping to ensure that the multicast
>> stream is only transmitted to clients that are actually a member of
>> the group. Can the mac80211 feature do the same?
>
> No, it'll convert the packet for all clients that
On Wednesday 04 January 2017 04:29 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:21AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off
On Wednesday 04 January 2017 04:29 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:21AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off
On Wednesday 04 January 2017 04:26 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:03AM -0500, Anurup M wrote:
From: Tan Xiaojun <tanxiao...@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
On Wednesday 04 January 2017 04:26 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:03AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
a
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 72
1 file changed, 72
ilable CPU
for counting.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 53
drivers/perf/hisilicon/hisi_uncore_pmu.c | 39 +++
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore
is -e "hisi_mn_2/read_req/"
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 501
2 files c
ilable CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 53
drivers/perf/hisilicon/hisi_uncore_pmu.c | 39 +++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 21 +
3 fil
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c.c | 556 +++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 326
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 501
2 files changed, 502 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
.../devicetree/
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 ++
.../devicetree
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --
ed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisi
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..2a5435b 100644
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 731
drivers/perf/hisilicon/djtag.h | 39 +++
4 files changed, 772 insertions(+)
create mode
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
From: Tan Xiaojun <tanxiao...@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 41
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M <anuru...@huawei.com>
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..fca339e 100644
--- a/MAINTAINERS
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..fca339e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5725,6
in this series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (7):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings
in this series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (7):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings
On Monday 19 December 2016 10:07 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:59AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup
On Monday 19 December 2016 10:07 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:59AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup
On Monday 19 December 2016 10:01 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:19AM -0500, Anurup M wrote:
From: Tan Xiaojun <tanxiao...@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
On Monday 19 December 2016 10:01 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:19AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm
ilable CPU
for counting.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++
ilable CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 21
3 files ch
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
a
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 78
1 file changed, 78
is -e "hisi_mn_2/read_req/"
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 516
2 files c
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 516
2 files changed, 517 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
ed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
driv
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M <anuru...@huawei.com>
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..ce86c07 100644
--- a/MAINTAINERS
Update Kconfig for Hip05/06/07 PMU support.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 729
drivers/perf/hisilicon/djtag.h | 39 +++
4 files changed, 770 insertions(+)
create mode
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c.c | 572 +++
drivers/perf
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..ce86c07 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5725,6
Update Kconfig for Hip05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..2befa55 100644
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
.../devicetree/
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisi
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 ++
.../devicetree
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