From: MaJun <majun...@huawei.com>
Just skip the irq affinity setting when the target cpu is the same as
current setting.
This is a small optimization for irq affinity setting logic.
Signed-off-by: MaJun <majun...@huawei.com>
---
drivers/irqchip/irq-gic-v3-its.c | 9 ++---
1 fil
From: MaJun
Just skip the irq affinity setting when the target cpu is the same as
current setting.
This is a small optimization for irq affinity setting logic.
Signed-off-by: MaJun
---
drivers/irqchip/irq-gic-v3-its.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
Commit-ID: 9459a04b6a5a09967eec94a1b66f0a74312819d9
Gitweb: http://git.kernel.org/tip/9459a04b6a5a09967eec94a1b66f0a74312819d9
Author: MaJun <majun...@huawei.com>
AuthorDate: Fri, 12 May 2017 11:55:28 +0800
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Fri, 12
Commit-ID: 9459a04b6a5a09967eec94a1b66f0a74312819d9
Gitweb: http://git.kernel.org/tip/9459a04b6a5a09967eec94a1b66f0a74312819d9
Author: MaJun
AuthorDate: Fri, 12 May 2017 11:55:28 +0800
Committer: Thomas Gleixner
CommitDate: Fri, 12 May 2017 10:25:38 +0200
irqchip/mbigen: Fix the clear
Hi Hanjun,
This patchset is fine to me and make my
D05 machine work again.So,
Tested-by: MaJun <majun...@huawei.com>
Thanks
Majun
在 2017/5/12 11:55, Hanjun Guo 写道:
> From: Hanjun Guo <hanjun@linaro.org>
>
> Here are 3 bugfixes for mbigen:
>
> Patch 1
Hi Hanjun,
This patchset is fine to me and make my
D05 machine work again.So,
Tested-by: MaJun
Thanks
Majun
在 2017/5/12 11:55, Hanjun Guo 写道:
> From: Hanjun Guo
>
> Here are 3 bugfixes for mbigen:
>
> Patch 1 is a critical bugfix which to fix the mbigen probe fa
Hi Marc:
在 2017/4/26 16:01, Marc Zyngier 写道:
> On 26/04/17 04:10, Hanjun Guo wrote:
>> Hi Majun,
>>
>> On 2017/4/25 10:16, Majun wrote:
>>> From: MaJun <majun...@huawei.com>
>>>
>>> Don't minus reserved interrupts (64) when get the clear reg
Hi Marc:
在 2017/4/26 16:01, Marc Zyngier 写道:
> On 26/04/17 04:10, Hanjun Guo wrote:
>> Hi Majun,
>>
>> On 2017/4/25 10:16, Majun wrote:
>>> From: MaJun
>>>
>>> Don't minus reserved interrupts (64) when get the clear register
>>> offse
From: MaJun <majun...@huawei.com>
Don't minus reserved interrupts (64) when get the clear register offset,because
the clear register space includes the space of these 64 interrupts.
Signed-off-by: MaJun <majun...@huawei.com>
---
drivers/irqchip/irq-mbigen.c | 1 -
1 file changed
From: MaJun
Don't minus reserved interrupts (64) when get the clear register offset,because
the clear register space includes the space of these 64 interrupts.
Signed-off-by: MaJun
---
drivers/irqchip/irq-mbigen.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/irqchip/irq-mbigen.c
v4.12
>>>
>>> You should try to merge it with Marc's branch:
>>>
>>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>>> irq/irqchip-4.12
>>>
>>> and test the resulting branch, that's how they will go upstream.
&
v4.12
>>>
>>> You should try to merge it with Marc's branch:
>>>
>>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>>> irq/irqchip-4.12
>>>
>>> and test the resulting branch, that's how they will go upstream.
&
> a PR to Catalin by the end of the week (first 7 patches up to
>> 7fc3061df075 ("ACPI: platform: setup MSI domain for ACPI based platform
>> device")).
>
> Perfect for me too, Lorenzo, Marc, Thank you very much.
>
> I'm currently in paternity leave and can't reach the machine,
> I had a detail review with the patches, they looks good to me,
> Ma Jun and Wei Xu will test on Hisilicon machines and give the
> feedback.
The sas/xge/uart are working fine on my hisilicon board with
Lorenzo's branch (arm64-acpi-4.12)
Thanks
Majun
>
> Thanks
> Hanjun
>
> .
>
> a PR to Catalin by the end of the week (first 7 patches up to
>> 7fc3061df075 ("ACPI: platform: setup MSI domain for ACPI based platform
>> device")).
>
> Perfect for me too, Lorenzo, Marc, Thank you very much.
>
> I'm currently in paternity leave and can't reach the machine,
> I had a detail review with the patches, they looks good to me,
> Ma Jun and Wei Xu will test on Hisilicon machines and give the
> feedback.
The sas/xge/uart are working fine on my hisilicon board with
Lorenzo's branch (arm64-acpi-4.12)
Thanks
Majun
>
> Thanks
> Hanjun
>
> .
>
Hi hanjun:
This patch works fine on my D05 board.
Tested-by: MaJun <majun...@huawei.com>
Best Regards
Majun
在 2017/3/28 20:21, Hanjun Guo 写道:
> With the preparation of platform msi support and interrupt producer
> in commit d44fa3d46079 ("ACPI: Add support for R
Hi hanjun:
This patch works fine on my D05 board.
Tested-by: MaJun
Best Regards
Majun
在 2017/3/28 20:21, Hanjun Guo 写道:
> With the preparation of platform msi support and interrupt producer
> in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
> domain map
Hi:
在 2016/12/26 16:57, majun (Euler7) 写道:
> Hi Hanjun:
> This patch set works fine on my Hisilicon D05 board.
> Feel free to add
Based on the Patch 1/3, 2/3 of [PATCH V9 0/3] irqchip: qcom: Add IRQ combiner
driver
from Agustin Vega-Frias
https://lwn.net/Articles/709222/
>
Hi:
在 2016/12/26 16:57, majun (Euler7) 写道:
> Hi Hanjun:
> This patch set works fine on my Hisilicon D05 board.
> Feel free to add
Based on the Patch 1/3, 2/3 of [PATCH V9 0/3] irqchip: qcom: Add IRQ combiner
driver
from Agustin Vega-Frias
https://lwn.net/Articles/709222/
>
r, then devices
> will get the virq from mbi-gen's irqdomain.
>
> Signed-off-by: Hanjun Guo <hanjun@linaro.org>
> Cc: Marc Zyngier <marc.zyng...@arm.com>
> Cc: Thomas Gleixner <t...@linutronix.de>
> Cc: Ma Jun <majun...@huawei.com>
> ---
> drivers
dev, mgn_chip);
> return 0;
> @@ -302,10 +359,17 @@ static int mbigen_device_probe(struct platform_device
> *pdev)
> };
> MODULE_DEVICE_TABLE(of, mbigen_of_match);
>
> +static const struct acpi_device_id mbigen_acpi_match[] = {
> +{ "HISI0152", 0 },
> + {}
> +};
> +MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
> +
> static struct platform_driver mbigen_platform_driver = {
> .driver = {
> .name = "Hisilicon MBIGEN-V2",
> .of_match_table = mbigen_of_match,
> + .acpi_match_table = ACPI_PTR(mbigen_acpi_match),
> },
> .probe = mbigen_device_probe,
> };
>
Reviewed-by: MaJun
..@huawei.com>
> Signed-off-by: Hanjun Guo <hanjun@linaro.org>
> Cc: Marc Zyngier <marc.zyng...@arm.com>
> Cc: Thomas Gleixner <t...@linutronix.de>
> Cc: Ma Jun <majun...@huawei.com>
> ---
> drivers/irqchip/irq-mbigen.c | 42
rg>
> Cc: Marc Zyngier <marc.zyng...@arm.com>
> Cc: Thomas Gleixner <t...@linutronix.de>
> Cc: Ma Jun <majun...@huawei.com>
> ---
> drivers/irqchip/irq-mbigen.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-mbigen.c b/driver
if (IS_ERR(mgn_chip->base))
> + return PTR_ERR(mgn_chip->base);
> +
> + err = mbigen_of_create_domain(pdev, mgn_chip);
> + if (err)
> + return err;
> +
> platform_set_drvdata(pdev, mgn_chip);
> return 0;
> }
>
Reviewed-by: MaJun
mbigen_of_match,
> },
> .probe = mbigen_device_probe,
>
Reviewed-by: MaJun
Hi Hanjun:
This patch set works fine on my Hisilicon D05 board.
Feel free to add
Tested-by: Majun <majun...@huawei.com>
在 2016/12/22 13:35, Hanjun Guo 写道:
> From: Hanjun Guo <hanjun@linaro.org>
>
> v4 -> v5:
> - Add mbigen support back wi
Hi Hanjun:
This patch set works fine on my Hisilicon D05 board.
Feel free to add
Tested-by: Majun
在 2016/12/22 13:35, Hanjun Guo 写道:
> From: Hanjun Guo
>
> v4 -> v5:
> - Add mbigen support back with tested on with Agustin's patchset,
> and i
Hi Marc:
在 2016/12/2 17:35, Marc Zyngier 写道:
> On 02/12/16 09:29, majun (Euler7) wrote:
>>
>>
>> 在 2016/12/1 17:07, Marc Zyngier 写道:
>>> On 01/12/16 07:45, Majun wrote:
>>>> From: MaJun <majun...@huawei.com>
>>>>
>>>>
Hi Marc:
在 2016/12/2 17:35, Marc Zyngier 写道:
> On 02/12/16 09:29, majun (Euler7) wrote:
>>
>>
>> 在 2016/12/1 17:07, Marc Zyngier 写道:
>>> On 01/12/16 07:45, Majun wrote:
>>>> From: MaJun
>>>>
>>>> For current ITS driver, two
在 2016/12/1 17:07, Marc Zyngier 写道:
> On 01/12/16 07:45, Majun wrote:
>> From: MaJun <majun...@huawei.com>
>>
>> For current ITS driver, two level table (indirect route) is enabled when the
>> memory used
>> for LPI route table over the limit(6
在 2016/12/1 17:07, Marc Zyngier 写道:
> On 01/12/16 07:45, Majun wrote:
>> From: MaJun
>>
>> For current ITS driver, two level table (indirect route) is enabled when the
>> memory used
>> for LPI route table over the limit(64KB * 2) size. But this function impa
From: MaJun <majun...@huawei.com>
Add the two-level-route property in ITS node.
When this property string defined, two-level route(indirect) function
will be enabled in ITS driver, otherwise disable it.
Signed-off-by: MaJun <majun...@huawei.com>
---
Documentation/devicetree/bindin
From: MaJun <majun...@huawei.com>
Add a new flag to control indirect route function for ACPI mode.
To carry the user defined flags information, we used the reserved byte
in ITS MADT table
Signed-off-by: MaJun <majun...@huawei.com>
---
drivers/irqchip/irq-gic-v3-its.c | 5 -
From: MaJun
Add the two-level-route property in ITS node.
When this property string defined, two-level route(indirect) function
will be enabled in ITS driver, otherwise disable it.
Signed-off-by: MaJun
---
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 3 +++
1 file
From: MaJun
Add a new flag to control indirect route function for ACPI mode.
To carry the user defined flags information, we used the reserved byte
in ITS MADT table
Signed-off-by: MaJun
---
drivers/irqchip/irq-gic-v3-its.c | 5 -
include/acpi/actbl1.h| 3 ++-
2 files changed
From: MaJun <majun...@huawei.com>
For current ITS driver, two level table (indirect route) is enabled when the
memory used
for LPI route table over the limit(64KB * 2) size. But this function impact the
performance of LPI interrupt actually because need more time to look up the
From: MaJun
For current ITS driver, two level table (indirect route) is enabled when the
memory used
for LPI route table over the limit(64KB * 2) size. But this function impact the
performance of LPI interrupt actually because need more time to look up the
table.
Although this function can
From: MaJun <majun...@huawei.com>
Add a new flag for ITS node in DT mode so we can disable/enable the
indirect route function.
Signed-off-by: MaJun <majun...@huawei.com>
---
drivers/irqchip/irq-gic-v3-its.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
From: MaJun
Add a new flag for ITS node in DT mode so we can disable/enable the
indirect route function.
Signed-off-by: MaJun
---
drivers/irqchip/irq-gic-v3-its.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers
sorry, ignore this one..
在 2016/12/1 15:41, Majun 写道:
> From: MaJun <majun...@huawei.com>
>
> The return value 0 from acpi_register_gsi() means irq mapping failed.
> So, we should process this case in else branch.
>
> Signed-off-by: MaJun <majun...@huawei.com>
&g
sorry, ignore this one..
在 2016/12/1 15:41, Majun 写道:
> From: MaJun
>
> The return value 0 from acpi_register_gsi() means irq mapping failed.
> So, we should process this case in else branch.
>
> Signed-off-by: MaJun
> ---
> drivers/acpi/resource.c | 2 +-
>
From: MaJun <majun...@huawei.com>
The return value 0 from acpi_register_gsi() means irq mapping failed.
So, we should process this case in else branch.
Signed-off-by: MaJun <majun...@huawei.com>
---
drivers/acpi/resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: MaJun
The return value 0 from acpi_register_gsi() means irq mapping failed.
So, we should process this case in else branch.
Signed-off-by: MaJun
---
drivers/acpi/resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/acpi/resource.c b/drivers/acpi
This patch works fine on my D05 board.
Tested-by: Majun <majun...@huawei.com>
在 2016/11/14 5:59, Agustin Vega-Frias 写道:
> This allows probe deferral to work properly when a dependent device
> fails to get a valid IRQ because the IRQ domain was not registered
> at the time the
This patch works fine on my D05 board.
Tested-by: Majun
在 2016/11/14 5:59, Agustin Vega-Frias 写道:
> This allows probe deferral to work properly when a dependent device
> fails to get a valid IRQ because the IRQ domain was not registered
> at the time the resources w
The return value 0 from acpi_register_gsi() means irq mapping failed.
So, we should process this case in else branch.
Signed-off-by: MaJun <majun...@huawei.com>
---
drivers/acpi/resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/acpi/resource.c b/driver
The return value 0 from acpi_register_gsi() means irq mapping failed.
So, we should process this case in else branch.
Signed-off-by: MaJun
---
drivers/acpi/resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/acpi/resource.c b/drivers/acpi/resource.c
index
在 2016/8/31 16:35, Marc Zyngier 写道:
> On 31/08/16 07:35, majun (F) wrote:
[...]
>>>
>>
>> I just checked the status of irq 30 during capture kernel booting.
>>
>> The irq 30 status is: mask, pending after arch_timer_starting_cpu() called.
>> Because i
在 2016/8/31 16:35, Marc Zyngier 写道:
> On 31/08/16 07:35, majun (F) wrote:
[...]
>>>
>>
>> I just checked the status of irq 30 during capture kernel booting.
>>
>> The irq 30 status is: mask, pending after arch_timer_starting_cpu() called.
>> Because i
Hi Marc & Mark:
在 2016/8/30 19:21, Mark Rutland 写道:
> On Tue, Aug 30, 2016 at 12:07:36PM +0100, Marc Zyngier wrote:
>> +Mark
>> On 30/08/16 11:35, majun (F) wrote:
>>> 在 2016/8/30 16:50, Marc Zyngier 写道:
>>>> On 30/08/16 05:17, MaJun wrote:
Hi Marc & Mark:
在 2016/8/30 19:21, Mark Rutland 写道:
> On Tue, Aug 30, 2016 at 12:07:36PM +0100, Marc Zyngier wrote:
>> +Mark
>> On 30/08/16 11:35, majun (F) wrote:
>>> 在 2016/8/30 16:50, Marc Zyngier 写道:
>>>> On 30/08/16 05:17, MaJun wrote:
>>>&
在 2016/8/30 16:50, Marc Zyngier 写道:
> On 30/08/16 05:17, MaJun wrote:
>> From: Ma Jun <majun...@huawei.com>
>>
>> During system booting, if the interrupt which has no action registered
>> is triggered, it would cause system panic when try to access the
>
在 2016/8/30 16:50, Marc Zyngier 写道:
> On 30/08/16 05:17, MaJun wrote:
>> From: Ma Jun
>>
>> During system booting, if the interrupt which has no action registered
>> is triggered, it would cause system panic when try to access the
>> action member.
>
>
From: Ma Jun <majun...@huawei.com>
During system booting, if the interrupt which has no action registered
is triggered, it would cause system panic when try to access the
action member.
Signed-off-by: Ma Jun <majun...@huawei.com>
---
kernel/irq/chip.c | 20 -
From: Ma Jun
During system booting, if the interrupt which has no action registered
is triggered, it would cause system panic when try to access the
action member.
Signed-off-by: Ma Jun
---
kernel/irq/chip.c | 20
1 files changed, 16 insertions(+), 4 deletions(-)
diff
Hi Marc:
在 2016/5/6 15:32, Marc Zyngier 写道:
> On 06/05/16 02:12, majun (F) wrote:
>> Hi Marc:
>>
>> 在 2016/5/5 22:49, Marc Zyngier 写道:
>>> On 22/03/16 03:10, majun (F) wrote:
>>>>
>>>>
>>>> 在 2016/3/21 18:29, Thomas Gleixner
Hi Marc:
在 2016/5/6 15:32, Marc Zyngier 写道:
> On 06/05/16 02:12, majun (F) wrote:
>> Hi Marc:
>>
>> 在 2016/5/5 22:49, Marc Zyngier 写道:
>>> On 22/03/16 03:10, majun (F) wrote:
>>>>
>>>>
>>>> 在 2016/3/21 18:29, Thomas Gleixner
Hi Marc:
在 2016/5/5 22:49, Marc Zyngier 写道:
> On 22/03/16 03:10, majun (F) wrote:
>>
>>
>> 在 2016/3/21 18:29, Thomas Gleixner 写道:
>>> On Thu, 17 Mar 2016, MaJun wrote:
>>>> This patch set is used to fix the problem of remap a set of register
Hi Marc:
在 2016/5/5 22:49, Marc Zyngier 写道:
> On 22/03/16 03:10, majun (F) wrote:
>>
>>
>> 在 2016/3/21 18:29, Thomas Gleixner 写道:
>>> On Thu, 17 Mar 2016, MaJun wrote:
>>>> This patch set is used to fix the problem of remap a set of register
From: Ma Jun <majun...@huawei.com>
When the CPU of a non-balanced irq bounded is off line, the irq will be
migrated to other CPUs,
usually the first cpu on-line.
We can suppose the situation if a system has more than one non-balanced irq.
At extreme case, these irqs will be migrated to th
From: Ma Jun
When the CPU of a non-balanced irq bounded is off line, the irq will be
migrated to other CPUs,
usually the first cpu on-line.
We can suppose the situation if a system has more than one non-balanced irq.
At extreme case, these irqs will be migrated to the same CPU and will cause
Commit-ID: 9a7c4abd41c0d553f4fb9845bdd4328155426ac7
Gitweb: http://git.kernel.org/tip/9a7c4abd41c0d553f4fb9845bdd4328155426ac7
Author: MaJun <majun...@huawei.com>
AuthorDate: Wed, 23 Mar 2016 17:06:33 +0800
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Wed, 23
Commit-ID: 9a7c4abd41c0d553f4fb9845bdd4328155426ac7
Gitweb: http://git.kernel.org/tip/9a7c4abd41c0d553f4fb9845bdd4328155426ac7
Author: MaJun
AuthorDate: Wed, 23 Mar 2016 17:06:33 +0800
Committer: Thomas Gleixner
CommitDate: Wed, 23 Mar 2016 12:02:29 +0100
irqchip/mbigen: Make
Commit-ID: dd17a3c40d46adea7215cad3f8fa0afb7c616290
Gitweb: http://git.kernel.org/tip/dd17a3c40d46adea7215cad3f8fa0afb7c616290
Author: MaJun <majun...@huawei.com>
AuthorDate: Wed, 23 Mar 2016 17:06:32 +0800
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Wed, 23
Commit-ID: dd17a3c40d46adea7215cad3f8fa0afb7c616290
Gitweb: http://git.kernel.org/tip/dd17a3c40d46adea7215cad3f8fa0afb7c616290
Author: MaJun
AuthorDate: Wed, 23 Mar 2016 17:06:32 +0800
Committer: Thomas Gleixner
CommitDate: Wed, 23 Mar 2016 12:02:29 +0100
ARM64: Kconfig: Select mbigen
From: Ma Jun <majun...@huawei.com>
As a interrupt controller used on some of hisilicon SOCs(660,1610 etc.),
mbigen driver should be enabled when CONFIG_ARCH_HISI is enabled.
Signed-off-by: Ma Jun <majun...@huawei.com>
---
arch/arm64/Kconfig.platforms |1 +
1 files changed, 1 inse
From: Ma Jun
As a interrupt controller used on some of hisilicon SOCs(660,1610 etc.),
mbigen driver should be enabled when CONFIG_ARCH_HISI is enabled.
Signed-off-by: Ma Jun
---
arch/arm64/Kconfig.platforms |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git
From: Ma Jun <majun...@huawei.com>
This config is selected by CONFIG_ARCH_HISI, So we change
this config to non-configurable.
I also adjust the mbigen config position try to sort the configs
in alphabetical order.
Signed-off-by: Ma Jun <majun...@huawei.com>
---
drivers/irqchip/Kc
From: Ma Jun <majun...@huawei.com>
In current driver, the config of mbigen driver is a configurable option and
have nothing to do with CONFIG_ARCH_HISI.
As a module of Hisilicon SOC, the config of mbigen driver should be selected
by CONFIG_ARCH_HISI on Hisilicon platform, but not a config
From: Ma Jun
This config is selected by CONFIG_ARCH_HISI, So we change
this config to non-configurable.
I also adjust the mbigen config position try to sort the configs
in alphabetical order.
Signed-off-by: Ma Jun
---
drivers/irqchip/Kconfig | 14 ++
1 files changed, 6
From: Ma Jun
In current driver, the config of mbigen driver is a configurable option and
have nothing to do with CONFIG_ARCH_HISI.
As a module of Hisilicon SOC, the config of mbigen driver should be selected
by CONFIG_ARCH_HISI on Hisilicon platform, but not a configurable option.
This patch
在 2016/3/21 18:29, Thomas Gleixner 写道:
> On Thu, 17 Mar 2016, MaJun wrote:
>> This patch set is used to fix the problem of remap a set of registers
>> repeatedly in current mbigen driver.
>>
>> irqchip/mbigen:Change the mbigen node definition in dt binding file
在 2016/3/21 18:29, Thomas Gleixner 写道:
> On Thu, 17 Mar 2016, MaJun wrote:
>> This patch set is used to fix the problem of remap a set of registers
>> repeatedly in current mbigen driver.
>>
>> irqchip/mbigen:Change the mbigen node definition in dt binding file
Commit-ID: d0e286415dc1f4fea2971d6186b0775c7062575b
Gitweb: http://git.kernel.org/tip/d0e286415dc1f4fea2971d6186b0775c7062575b
Author: MaJun <majun...@huawei.com>
AuthorDate: Thu, 17 Mar 2016 16:34:00 +0800
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Mon, 21
Commit-ID: d0e286415dc1f4fea2971d6186b0775c7062575b
Gitweb: http://git.kernel.org/tip/d0e286415dc1f4fea2971d6186b0775c7062575b
Author: MaJun
AuthorDate: Thu, 17 Mar 2016 16:34:00 +0800
Committer: Thomas Gleixner
CommitDate: Mon, 21 Mar 2016 11:24:10 +0100
irqchip/mbigen: Adjust DT
Commit-ID: ed2a1002d25ccdb6606c8ccb608524118bd30614
Gitweb: http://git.kernel.org/tip/ed2a1002d25ccdb6606c8ccb608524118bd30614
Author: MaJun <majun...@huawei.com>
AuthorDate: Thu, 17 Mar 2016 16:34:01 +0800
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Mon, 21
Commit-ID: ed2a1002d25ccdb6606c8ccb608524118bd30614
Gitweb: http://git.kernel.org/tip/ed2a1002d25ccdb6606c8ccb608524118bd30614
Author: MaJun
AuthorDate: Thu, 17 Mar 2016 16:34:01 +0800
Committer: Thomas Gleixner
CommitDate: Mon, 21 Mar 2016 11:24:11 +0100
irqchip/mbigen: Handle
From: Ma Jun <majun...@huawei.com>
For mbigen module, there is a special case that more than one mbigen
device nodes use the same reg definition in DTS when these devices
exist in the same mbigen hardware module.
In current mbigen driver, these mbigen devices definition as below:
mbige
From: Ma Jun
For mbigen module, there is a special case that more than one mbigen
device nodes use the same reg definition in DTS when these devices
exist in the same mbigen hardware module.
In current mbigen driver, these mbigen devices definition as below:
mbigen_dev1:intc_dev1 {
...
From: Ma Jun <majun...@huawei.com>
This patch set is used to fix the problem of remap a set of registers
repeatedly in current mbigen driver.
Changes in v3:
--- Change the log to make more detail description about
the IO remap problem.
Changes in v2:
--- Change the mbigen devic
From: Ma Jun
This patch set is used to fix the problem of remap a set of registers
repeatedly in current mbigen driver.
Changes in v3:
--- Change the log to make more detail description about
the IO remap problem.
Changes in v2:
--- Change the mbigen device node definition as Mark
From: Ma Jun <majun...@huawei.com>
In current mbigen driver, each mbigen device is initialized as a platform
device.
When these devices belong to same mbigen hardware module(chip), they use the
same register definition in their device node and caused the problem of
registers
remapped repe
From: Ma Jun
In current mbigen driver, each mbigen device is initialized as a platform
device.
When these devices belong to same mbigen hardware module(chip), they use the
same register definition in their device node and caused the problem of
registers
remapped repeatedly.
Now, I try to
Hi Thomas:
Thanks for pointing out the problems.
I'll make detail description about this problem and resend this patch set.
在 2016/3/14 15:49, Thomas Gleixner 写道:
> Majun,
>
> On Mon, 14 Mar 2016, MaJun wrote:
>
> First of all the prefix for irq chip drivers is not &q
Hi Thomas:
Thanks for pointing out the problems.
I'll make detail description about this problem and resend this patch set.
在 2016/3/14 15:49, Thomas Gleixner 写道:
> Majun,
>
> On Mon, 14 Mar 2016, MaJun wrote:
>
> First of all the prefix for irq chip drivers is not &q
From: Ma Jun <majun...@huawei.com>
To fix the IO remap problem, change the mbigen driver based on the
new mbigen node definition.
Signed-off-by: Ma Jun <majun...@huawei.com>
---
drivers/irqchip/irq-mbigen.c | 30 +-
1 files changed, 21 insertions(+),
From: Ma Jun <majun...@huawei.com>
For mbigen module, there is a special case that more than one mbigen
device nodes use the same reg definition in DTS when these devices
exist in the same mbigen hardware module.
To fix the mbigen IO remap problem, the mbigen node definition and
str
From: Ma Jun
For mbigen module, there is a special case that more than one mbigen
device nodes use the same reg definition in DTS when these devices
exist in the same mbigen hardware module.
To fix the mbigen IO remap problem, the mbigen node definition and
structure are changed based on Mark
From: Ma Jun
To fix the IO remap problem, change the mbigen driver based on the
new mbigen node definition.
Signed-off-by: Ma Jun
---
drivers/irqchip/irq-mbigen.c | 30 +-
1 files changed, 21 insertions(+), 9 deletions(-)
diff --git
From: Ma Jun <majun...@huawei.com>
This patch set is used to fix the problem of remap a set of registers
repeatedly.
Changes in v2:
--- Change the mbigen device node definition
--- Change the mbigen driver based on the new mbigen dts structure.
Ma Jun (2):
Irq/mbigen:Change the mbige
From: Ma Jun
This patch set is used to fix the problem of remap a set of registers
repeatedly.
Changes in v2:
--- Change the mbigen device node definition
--- Change the mbigen driver based on the new mbigen dts structure.
Ma Jun (2):
Irq/mbigen:Change the mbigen node definition in dt
在 2016/3/2 11:09, Al Viro 写道:
> On Wed, Mar 02, 2016 at 10:47:59AM +0800, MaJun wrote:
>> From: Ma Jun <majun...@huawei.com>
>>
>> The spin_lock/unlock_irq interface is not safe when this function is called
>> at some case which need irq disabled.
>
>&
在 2016/3/2 11:09, Al Viro 写道:
> On Wed, Mar 02, 2016 at 10:47:59AM +0800, MaJun wrote:
>> From: Ma Jun
>>
>> The spin_lock/unlock_irq interface is not safe when this function is called
>> at some case which need irq disabled.
>
>> Fo
From: Ma Jun <majun...@huawei.com>
The spin_lock/unlock_irq interface is not safe when this function is called
at some case which need irq disabled.
For example:
spin_lock_irqsave()
|
request_irq() --> proc_alloc_inum()
|
spin_unlock_irqrestore()
From: Ma Jun
The spin_lock/unlock_irq interface is not safe when this function is called
at some case which need irq disabled.
For example:
spin_lock_irqsave()
|
request_irq() --> proc_alloc_inum()
|
spin_unlock_irqrestore()
Reported-by: Fan Jinke
From: Ma Jun <majun...@huawei.com>
Using module_platform_driver() to register mbigen driver is
too late for some driver to apply irq, because the mbigen irq
domain is not created yet.
Signed-off-by: Ma Jun <majun...@huawei.com>
---
drivers/irqchip/irq-mbigen.c |9 -
1 f
From: Ma Jun
Using module_platform_driver() to register mbigen driver is
too late for some driver to apply irq, because the mbigen irq
domain is not created yet.
Signed-off-by: Ma Jun
---
drivers/irqchip/irq-mbigen.c |9 -
1 files changed, 8 insertions(+), 1 deletions(-)
diff
在 2016/2/16 16:50, Marc Zyngier 写道:
> On Tue, 16 Feb 2016 14:37:27 +0800
> MaJun <majun...@huawei.com> wrote:
>
>> From: Ma Jun <majun...@huawei.com>
[...]
>> +unsigned int nid;
>> +
>> +nid = get_mbigen_nid(hwirq);
>> +
&
在 2016/2/16 16:50, Marc Zyngier 写道:
> On Tue, 16 Feb 2016 14:37:27 +0800
> MaJun wrote:
>
>> From: Ma Jun
[...]
>> +unsigned int nid;
>> +
>> +nid = get_mbigen_nid(hwirq);
>> +
>> +if (nid < 4)
>> +
From: Ma Jun <majun...@huawei.com>
Add the platform device driver for mbigen chip v1.
This patch just same as mbigen v2.
Signed-off-by: Ma Jun <majun...@huawei.com>
---
drivers/irqchip/Makefile|2 +-
drivers/irqchip/irq-mbigen-v1.c | 76 ++
From: Ma Jun
Add the platform device driver for mbigen chip v1.
This patch just same as mbigen v2.
Signed-off-by: Ma Jun
---
drivers/irqchip/Makefile|2 +-
drivers/irqchip/irq-mbigen-v1.c | 76 +++
2 files changed, 77 insertions(+), 1
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