Breaking the error message will make it harder to grep for it in the
driver. So let's put the error message in a single line.
Signed-off-by: Manivannan Sadhasivam
---
drivers/virtio/virtio_pci_modern.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/v
s not have
VIRTIO_F_VERSION_1
So remove the 'virtio:' prefix which is redundant.
Signed-off-by: Manivannan Sadhasivam
---
drivers/virtio/virtio.c| 3 +--
drivers/virtio/virtio_pci_modern.c | 4 ++--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/virtio/virti
+ Jason Wang (email got truncated).
On Fri, Jul 12, 2024 at 07:59:14PM +0530, Manivannan Sadhasivam wrote:
> Virtio spec has so far only supported MSI-X and INTX for receiving the
> interrupts from the virtio device on PCI transport. But this becomes a
> limiting factor for devices s
ies such as IRQ affinity are also reused for MSI (but the
affinity setting really depends on the underlying IRQCHIP controller).
[1]
https://lore.kernel.org/virtio-comment/20240712140144.12066-1-manivannan.sadhasi...@linaro.org/
Signed-off-by: Manivannan Sadhasivam
---
drivers/virtio/virtio_pc
On Fri, Mar 22, 2024 at 08:59:12AM +0100, Luca Weiss wrote:
> On Mon Dec 4, 2023 at 6:28 PM CET, Manivannan Sadhasivam wrote:
> > On Mon, Dec 04, 2023 at 01:21:42PM +0100, Luca Weiss wrote:
> > > On Mon Dec 4, 2023 at 1:15 PM CET, Nitin Rawat wrote:
> > > >
> &
On Sun, Feb 18, 2024 at 02:13:39PM +0530, Krishna chaitanya chundru wrote:
> User space tools can't map strings if we use directly, as the string
> address is internal to kernel.
>
> So add trace point strings for the user space tools to map strings
> properly.
>
> Signed-off-by: Krishna chaitany
On Wed, Feb 21, 2024 at 09:11:03AM -0500, Steven Rostedt wrote:
> On Wed, 21 Feb 2024 11:41:46 +0530
> Manivannan Sadhasivam wrote:
>
> > On Sun, Feb 18, 2024 at 02:13:39PM +0530, Krishna chaitanya chundru wrote:
> > > User space tools can't map strings if w
gt; Signed-off-by: Krishna chaitanya chundru
Reported-by: Steven Rostedt
Reviewed-by: Manivannan Sadhasivam
- Mani
> ---
> drivers/bus/mhi/host/main.c | 4 ++--
> drivers/bus/mhi/host/trace.h | 2 ++
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/bus/m
t in both trace header file and other files.
>
> Where ever the trace events are added, debug messages are removed.
>
> Signed-off-by: Krishna chaitanya chundru
Applied to mhi-next!
- Mani
> Reviewed-by: Manivannan Sadhasivam
> Reviewed-by: "Steven Rostedt (Google)&qu
On Tue, Feb 06, 2024 at 02:33:12PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Feb 06, 2024 at 12:25:30PM +0530, Krishna Chaitanya Chundru wrote:
> >
> >
> > On 2/6/2024 11:56 AM, Manivannan Sadhasivam wrote:
> > > On Tue, Feb 06, 2024 at 10:02:05AM +0530, K
On Tue, Feb 06, 2024 at 12:25:30PM +0530, Krishna Chaitanya Chundru wrote:
>
>
> On 2/6/2024 11:56 AM, Manivannan Sadhasivam wrote:
> > On Tue, Feb 06, 2024 at 10:02:05AM +0530, Krishna chaitanya chundru wrote:
> > > This change adds ftrace support for following functi
t in both trace header file and other files.
>
> Where ever the trace events are added, debug messages are removed.
>
> Signed-off-by: Krishna chaitanya chundru
There are a lot of checkpatch errors. Please fix them and resubmit.
- Mani
> Reviewed-by: Manivannan Sadhasivam
&g
On Wed, Jan 31, 2024 at 09:54:04AM +0530, Krishna chaitanya chundru wrote:
> This change adds ftrace support for following functions which
> helps in debugging the issues when there is Channel state & MHI
> state change and also when we receive data and control events:
> 1. mhi_intvec_mhi_states
>
t in both trace header file and other files.
>
> Where ever the trace events are added, debug messages are removed.
>
> Signed-off-by: Krishna chaitanya chundru
Reviewed-by: Manivannan Sadhasivam
- Mani
> Reviewed-by: "Steven Rostedt (Google)"
> ---
> Changes i
On Tue, Jan 30, 2024 at 09:22:52AM -0500, Steven Rostedt wrote:
> On Tue, 30 Jan 2024 13:41:52 +0530
> Manivannan Sadhasivam wrote:
>
> > So same trace will get printed for both mhi_channel_command_start() and
> > mhi_channel_command_end()?
>
> The trace output will
On Fri, Jan 05, 2024 at 05:53:03PM +0530, Krishna chaitanya chundru wrote:
> This change adds ftrace support for following functions which
> helps in debugging the issues when there is Channel state & MHI
> state change and also when we receive data and control events:
> 1. mhi_intvec_mhi_states
>
additions as written in the cover letter]
> Signed-off-by: Luca Weiss
Acked-by: Manivannan Sadhasivam
- Mani
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 74
> +++-
> 1 file changed, 73 insertions(+), 1 deletion(-)
>
> diff --git a/a
On Tue, Dec 05, 2023 at 08:51:05AM +0100, Luca Weiss wrote:
> On Mon Dec 4, 2023 at 6:28 PM CET, Manivannan Sadhasivam wrote:
> > On Mon, Dec 04, 2023 at 01:21:42PM +0100, Luca Weiss wrote:
> > > On Mon Dec 4, 2023 at 1:15 PM CET, Nitin Rawat wrote:
> > > >
> &
On Mon, Dec 04, 2023 at 01:21:42PM +0100, Luca Weiss wrote:
> On Mon Dec 4, 2023 at 1:15 PM CET, Nitin Rawat wrote:
> >
> >
> > On 12/4/2023 3:54 PM, Luca Weiss wrote:
> > > From: Nitin Rawat
> > >
> > > Add UFS host controller and PHY nodes for sc7280 soc.
> > >
> > > Signed-off-by: Nitin Rawat
On Mon, Nov 27, 2023 at 04:39:12PM +0530, Krishna chaitanya chundru wrote:
> This change adds ftrace support for following functions which
> helps in debugging the issues when there is Channel state & MHI
> state change and also when we receive data and control events:
> 1. mhi_intvec_mhi_states
>
Hi Greg,
On Sun, Apr 11, 2021 at 08:57:03AM +0200, Greg KH wrote:
> On Sun, Apr 11, 2021 at 11:25:59AM +0530, Manivannan Sadhasivam wrote:
> > Hi Greg,
> >
> > Here is the MHI Pull request for the v5.13 cycle. I stayed with the PR as
> > the
> > number patche
: pci_generic: Add FIREHOSE channels
Manivannan Sadhasivam (2):
bus: mhi: pci_generic: Constify mhi_controller_config struct definitions
bus: mhi: core: Fix shadow declarations
drivers/bus/mhi/core/boot.c | 64 ++--
drivers/bus/mhi/core/debugfs.c | 2 +-
drivers/bus/mhi/core
On Fri, Apr 09, 2021 at 08:44:07AM -0500, Alex Elder wrote:
> The IPA core clock is required for SDX55. Define it.
>
> Signed-off-by: Alex Elder
I tested this patch on couple of SDX55 based boards like Telit FN980 and
Thundercomm T55. Hence,
Tested-by: Manivannan Sadhasivam
A
On Thu, Apr 08, 2021 at 03:02:20AM -0700, Jarvis Jiang wrote:
> The word 'rung' is a typo in below comment, fix it.
> * @event_ring: The event rung index that services this channel
>
> Signed-off-by: Jarvis Jiang
Applied to mhi-next!
Thanks,
Mani
> ---
> include/linux/mhi.h | 2 +-
> 1 file c
On Thu, Apr 08, 2021 at 03:02:20AM -0700, Jarvis Jiang wrote:
> The word 'rung' is a typo in below comment, fix it.
> * @event_ring: The event rung index that services this channel
>
> Signed-off-by: Jarvis Jiang
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> -
On Fri, Apr 09, 2021 at 08:49:45AM +0800, Bixuan Cui wrote:
> There is a error message after devm_ioremap_resource failed, and the ret
> is needs to be obtained through PTR_ERR(qcom->qscratch_base).
> We need to move the dev_err() downwards to ensure that the ret value is
> correct.
>
> Fixes: a43
ter balanced.
>
> Reported-by: Hulk Robot
> Signed-off-by: Wang Li
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> drivers/spi/spi-qup.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
> index 8d
", ret);
Does the userspace need to know how many bytes were not copied? I don't
think this is a useful information. So you could remove this err print.
With that,
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> + return -EFAULT;
> + }
> +
> +
On Sun, Apr 04, 2021 at 12:17:52PM -0500, Bjorn Andersson wrote:
> On Fri 02 Apr 01:17 CDT 2021, Deepak Kumar Singh wrote:
>
> > Not all upcoming usecases will have an interface to allow the aoss
> > driver to hook onto. Expose the send api and create a get function to
> > enable drivers to send t
On Fri, Apr 09, 2021 at 09:54:24AM +0800, Jia Yang wrote:
> devm_ioremap_resource() has recorded error log, so it's
> unnecessary to record log again.
>
> Reported-by: Hulk Robot
> Signed-off-by: Jia Yang
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> dr
> cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
> if (!cpu0_base) {
> pr_err("Failed to map source base\n");
> - return -EINVAL;
Missing "ret = -EINVAL" assignment. With that fixed,
Reviewed-by: Manivan
On Thu, Apr 08, 2021 at 09:55:09PM +0800, Chen Hui wrote:
> Add missing MODULE_DEVICE_TABLE entries to support module autoloading,
> as these drivers can be compiled as external modules.
>
> Signed-off-by: Chen Hui
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> dr
On Fri, Apr 09, 2021 at 10:33:49AM +0800, Laibin Qiu wrote:
> devm_ioremap_resource() has recorded error log, so it's
> unnecessary to record log again.
>
> Reported-by: Hulk Robot
> Signed-off-by: Laibin Qiu
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
local [-Wshadow]
856 | enum mhi_pm_state new_state;
| ^
drivers/bus/mhi/core/main.c:837:19: note: shadowed declaration is here
837 |enum mhi_state new_state;
| ^
Signed-off-by: Manivannan Sadhasivam
---
Changes in v3
Add remoteproc support for Hexagon modem found on the Qualcomm SDX55
platform.
Signed-off-by: Manivannan Sadhasivam
---
drivers/remoteproc/qcom_q6v5_pas.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc
Enable the Qualcomm Q6V5_PAS (Peripheral Authentication Service)
remoteproc driver to manage the modem co-processor in SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b
Not all platforms are able to allocate CMA size of 256MB. One such
platform is SDX55. Hence, use the standard 64MB size for CMA.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/configs
Enable the Qualcomm GLINK SMEM driver to support GLINK protocol over
shared memory.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 5955aeb0646e
Enable interconnect driver for SDX55 platform to manage the interconnect
providers.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 695612829503
Enable CPUFreq and CPUFreq DT drivers to carry out CPU Frequency scaling
duties on platforms like SDX55.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs
Enable A7 PLL driver and APCS clock driver on SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 0b9da27f923a..02f6185f31a6 100644
Enable Qualcomm APCS IPC mailbox driver for IPC communication between
application processor and other masters in platforms like SDX55.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b
Hi Bjorn,
This series updates the qcom_defconfig by enabling the drivers required
for the SDX55 platform.
Please consider merging!
Thanks,
Mani
Manivannan Sadhasivam (7):
ARM: configs: qcom_defconfig: Enable APCS IPC mailbox driver
ARM: configs: qcom_defconfig: Enable SDX55 A7 PLL and APCS
Add modem support to SDX55 using the PAS remoteproc driver.
Signed-off-by: Manivannan Sadhasivam
---
.../boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 5 +++
arch/arm/boot/dts/qcom-sdx55.dtsi | 33 +++
2 files changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts
Add devicetree binding for SDX55 remoteproc.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc
Thundercomm T55 is the development platform based on the Qualcomm SDX55
chipset. This basic support includes support for debug serial, NAND
flash, BAM DMA, USB and regulators support.
https://www.thundercomm.com/app_en/product/1593506006365532
Signed-off-by: Manivannan Sadhasivam
---
arch/arm
Add devicetree binding for Thundercomm T55 Dev kit based on SDX55.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm
Telit FN980 TLB is the development platform based on the Qualcomm SDX55
chipset. This basic support includes support for debug serial, NAND
flash, BAM DMA, USB and regulators support.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/Makefile| 3 +-
.../boot/dts
Add devicetree binding for Telit FN980 TLB board based on SDX55.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm
Use the common "nand-controller" node name for NAND controller node to
fix the `make dtbs_check` validation for Qcom platforms.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +-
2 files changed, 2 insert
Add interconnect nodes for the providers in SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 33 +++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot/dts/qcom-sdx55.dtsi
Add SCM node to enable SCM functionality on SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot/dts/qcom-sdx55.dtsi
index 4ca871735025
Add devicetree compatible for SCM present in SDX55 platform.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings
Add a simple-mfd representing IMEM on SDX55 and define the PIL
relocation info region, so that post mortem tools will be able to locate
the loaded remoteproc.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff
Add SMP2P nodes for the SDX55 platform to communicate with the modem.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot/dts/qcom-sdx55
Add CPUFreq support to SDX55 platform using the cpufreq-dt driver.
There is no dedicated hardware block available on this platform to
carry on the CPUFreq duties. Hence, it is accomplished using the CPU
clock and regulators tied together by the operating points table.
Signed-off-by: Manivannan
The APCS block on SDX55 acts as a mailbox controller and also provides
clock output for the Cortex A7 CPU.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot
On SDX55 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm
already merged. Remoteproc
patch will be submitted separately.
Thanks,
Mani
Manivannan Sadhasivam (15):
ARM: dts: qcom: sdx55: Add support for A7 PLL clock
ARM: dts: qcom: sdx55: Add support for APCS block
ARM: dts: qcom: sdx55: Add CPUFreq support
ARM: dts: qcom: sdx55: Add modem SMP2P node
On Thu, Apr 08, 2021 at 02:55:24AM -0700, Jarvis Jiang wrote:
> Add support for T99W175 modems, this modem series is based on SDX55
> qcom chip. The modem is mainly based on MBIM protocol for both the
> data and control path.
>
> This patch adds support for below modems:
>
> - T99W175(based on s
"mhi_controller_config" struct is not modified inside "mhi_pci_dev_info"
struct. So constify the instances.
Signed-off-by: Manivannan Sadhasivam
---
drivers/bus/mhi/pci_generic.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/bus/mhi/pci
,
[PATCH v2] bus: mhi: pci_generic: Introduce Foxconn T99W175 support
> Signed-off-by: Jarvis Jiang
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
Also you need to add the changelog here.
> drivers/bus/mhi/pci_generic.c | 47 +++
> 1 file c
local [-Wshadow]
856 | enum mhi_pm_state new_state;
| ^
drivers/bus/mhi/core/main.c:837:19: note: shadowed declaration is here
837 |enum mhi_state new_state;
| ^
Signed-off-by: Manivannan Sadhasivam
---
Changes in v2
On Wed, Mar 10, 2021 at 02:30:55PM -0700, Jeffrey Hugo wrote:
> When parsing the structures in the shared memory, there are values which
> come from the remote device. For example, a transfer completion event
> will have a pointer to the tre in the relevant channel's transfer ring.
> As another ex
local [-Wshadow]
856 | enum mhi_pm_state new_state;
| ^
drivers/bus/mhi/core/main.c:837:19: note: shadowed declaration is here
837 |enum mhi_state new_state;
| ^
Signed-off-by: Manivannan Sadhasivam
---
drivers/bus
red to be
> untrusted, and validated before use. If we blindly use such values, we
> may access invalid data or crash if the values are corrupted.
>
> If validation fails, drop the relevant event.
>
> Signed-off-by: Jeffrey Hugo
Looks good to me, but I need an ACK from Hemant/
On Thu, Apr 01, 2021 at 02:16:09PM -0700, Bhaumik Bhatt wrote:
> Subject: [PATCH v8 0/9] Updates to MHI channel handling
>
Subject is present in the body ;)
> MHI specification shows a state machine with support for STOP channel command
> and the validity of certain state transitions. MHI host c
On Fri, Apr 02, 2021 at 02:33:19PM -0700, Bhaumik Bhatt wrote:
> Add generic info for SDX65 based modems.
>
> Signed-off-by: Bhaumik Bhatt
Applied to mhi-next!
Thanks,
Mani
> ---
> This patch was tested on SDX65 hardware with Ubuntu X86_64 PC as host.
>
> drivers/bus/mhi/pci_generic.c | 11 +
On Thu, Apr 01, 2021 at 02:41:49PM -0700, Bhaumik Bhatt wrote:
> Some controllers can choose to skip preparation for power up.
> In that case, device context is initialized based on the pre_init
> flag not being set during mhi_prepare_for_power_up(). There is no
> reason MHI host driver should main
On Tue, Apr 06, 2021 at 07:50:29PM -0700, Jarvis Jiang wrote:
> Add support for T99W175 modems, this modem series is based on SDX55
> qcom chip. The modem is mainly based on MBIM protocol for both the
> data and control path.
>
List the modems whose support is being added.
> This patch was teste
a timeout if the send were to fail. This
> can help improve the design and enable shorter wait periods for
> device to respond as votes are already held.
>
> Signed-off-by: Bhaumik Bhatt
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> drivers/bus/mhi/core/main.c | 19
for channel updates.
>
> Suggested-by: Manivannan Sadhasivam
> Signed-off-by: Bhaumik Bhatt
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> drivers/bus/mhi/core/main.c | 12 +---
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drive
ation. Using this common function allows MHI to
> eliminate some unnecessary debug messages and code duplication.
>
> Signed-off-by: Bhaumik Bhatt
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> drivers/bus/mhi/core/init.c | 6 ++
> drivers/bus/mhi/core/internal.h
: Manivannan Sadhasivam
---
Changes in v2:
* Fixed CLASS_ATTR_RW as spotted by Greg
.../driver-api/driver-model/class.rst | 144 --
1 file changed, 66 insertions(+), 78 deletions(-)
diff --git a/Documentation/driver-api/driver-model/class.rst
b/Documentation/driver-api
On Fri, Apr 02, 2021 at 02:33:19PM -0700, Bhaumik Bhatt wrote:
> Add generic info for SDX65 based modems.
>
> Signed-off-by: Bhaumik Bhatt
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> This patch was tested on SDX65 hardware with Ubuntu X86_64 PC as host.
>
> pre_init flag and sets up a common way for all controllers to use
> MHI. This also helps controllers fail early on during preparation
> phase in some failure cases.
>
> Signed-off-by: Bhaumik Bhatt
I hope Jeff is also okay with this patch for AIC100.
Reviewed-by: Manivannan Sad
dma_mapping_error() should be used for checking the error value of
dma_map_resource() API.
Signed-off-by: Manivannan Sadhasivam
---
drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw
On Sat, Apr 03, 2021 at 03:04:42PM +0200, Greg KH wrote:
> On Sat, Apr 03, 2021 at 05:30:50PM +0530, Manivannan Sadhasivam wrote:
> > The current documentation about the device class is out of date such
> > that it refers to non-existent APIs and structures. This commit updates
: Manivannan Sadhasivam
---
.../driver-api/driver-model/class.rst | 144 --
1 file changed, 66 insertions(+), 78 deletions(-)
diff --git a/Documentation/driver-api/driver-model/class.rst
b/Documentation/driver-api/driver-model/class.rst
index fff55b80e86a..4e1779a37939
On Tue, Mar 30, 2021 at 04:48:18PM +0300, Cristian Ciocaltea wrote:
> The driver provides information about the Action Semi Owl family of
> SoCs (S500, S700 and S900) to user space via sysfs: machine, family,
> soc_id, serial_number.
>
> Note the serial number is currently provided only for the S5
On Thu, Apr 01, 2021 at 08:40:01PM +0300, Cristian Ciocaltea wrote:
> On Thu, Apr 01, 2021 at 12:07:04PM -0500, Rob Herring wrote:
> > On Tue, Mar 30, 2021 at 04:48:16PM +0300, Cristian Ciocaltea wrote:
> > > Add devicetree binding for the Actions Semi Owl SoC serial number
> > > reserved-memory ra
On Tue, Mar 30, 2021 at 04:48:17PM +0300, Cristian Ciocaltea wrote:
> Add devicetree binding for the Actions Semi Owl socinfo driver.
>
Devicetree binding shouldn't be added for a driver instead for an IP or hw.
> Signed-off-by: Cristian Ciocaltea
> ---
> .../bindings/soc/actions/owl-socinfo.y
regions (including reading).
The regions are declared using a NAND chip DT property,
"secure-regions". So let's make use of this property in the raw NAND
core and skip access to the secure regions present in a system.
Signed-off-by: Manivannan Sadhasivam
---
drivers/mtd/nand/raw/na
Add missing nand_cleanup() in the alloc_bam_transaction() error path
to cleanup the resources properly.
Signed-off-by: Manivannan Sadhasivam
---
drivers/mtd/nand/raw/qcom_nandc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw
regions (including reading).
So let's add a property for declaring such secure regions so that the
drivers can skip touching them.
Reviewed-by: Rob Herring
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++
1 file changed, 7 inser
Convert Qcom NANDc devicetree binding to YAML.
Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/qcom,nandc.yaml | 196 ++
.../devicetree/bindings/mtd/qcom_nandc.txt| 142 -
2 files changed, 196 insertions(+), 142
operty parsing
logic before nand_scan() in driver.
Changes in v2:
* Moved the secure-regions property to generic NAND binding as a NAND
chip property and renamed it as "nand-secure-regions".
Manivannan Sadhasivam (4):
dt-bindings: mtd: Convert Qcom NANDc binding to YAML
dt-bin
On Fri, Apr 02, 2021 at 10:51:54AM +0200, Boris Brezillon wrote:
> On Thu, 1 Apr 2021 21:46:22 +0530
> Manivannan Sadhasivam wrote:
>
> > On Thu, Apr 01, 2021 at 05:54:21PM +0200, Boris Brezillon wrote:
> > > On Thu, 1 Apr 2021 20:49:54 +0530
> >
Add missing nand_cleanup() in the alloc_bam_transaction() error path
to cleanup the resources properly.
Signed-off-by: Manivannan Sadhasivam
---
drivers/mtd/nand/raw/qcom_nandc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw
regions (including reading).
So let's add a property for declaring such secure regions so that the
drivers can skip touching them.
Reviewed-by: Rob Herring
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++
1 file changed, 7 inser
On Thu, Apr 01, 2021 at 05:54:21PM +0200, Boris Brezillon wrote:
> On Thu, 1 Apr 2021 20:49:54 +0530
> Manivannan Sadhasivam wrote:
>
> > @@ -565,6 +608,11 @@ static int nand_block_isreserved(struct mtd_info *mtd,
> > loff_t ofs)
> >
> > if (!ch
view tag for binding conversion patch
Changes in v3:
* Removed the nand prefix from DT property and moved the property parsing
logic before nand_scan() in driver.
Changes in v2:
* Moved the secure-regions property to generic NAND binding as a NAND
chip property and renamed it as "nan
2-array" as per Rob's review.
* Collected Rob's review tag for binding conversion patch
Changes in v3:
* Removed the nand prefix from DT property and moved the property parsing
logic before nand_scan() in driver.
Changes in v2:
* Moved the secure-regions property to generic NAND b
Convert Qcom NANDc devicetree binding to YAML.
Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/qcom,nandc.yaml | 196 ++
.../devicetree/bindings/mtd/qcom_nandc.txt| 142 -
2 files changed, 196 insertions(+), 142
regions (including reading).
So let's add a property for declaring such secure regions so that the
drivers can skip touching them.
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --
Add missing nand_cleanup() in the alloc_bam_transaction() error path
to cleanup the resources properly.
Signed-off-by: Manivannan Sadhasivam
---
drivers/mtd/nand/raw/qcom_nandc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw
regions (including reading).
The regions are declared using a NAND chip DT property,
"secure-regions". So let's make use of this property in the raw NAND
core and skip access to the secure regions present in a system.
Signed-off-by: Manivannan Sadhasivam
---
drivers/mtd/nand/raw/na
Convert Qcom NANDc devicetree binding to YAML.
Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/qcom,nandc.yaml | 196 ++
.../devicetree/bindings/mtd/qcom_nandc.txt| 142 -
2 files changed, 196 insertions(+), 142
regions (including reading).
The regions are declared using a NAND chip DT property,
"secure-regions". So let's make use of this property in the raw NAND
core and skip access to the secure regions present in a system.
Signed-off-by: Manivannan Sadhasivam
---
drivers/mtd/nand/raw/na
+ Matheus
On Thu, Apr 01, 2021 at 01:58:05PM +0300, Cristian Ciocaltea wrote:
> Hi Mani, Andreas,
>
> On Thu, Apr 01, 2021 at 12:49:37PM +0200, Andreas Färber wrote:
> > Hi,
> >
> > On 01.04.21 12:27, Manivannan Sadhasivam wrote:
> > > On Thu, Apr 01
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