On Thu, May 08, 2025 at 07:26:31PM +0200, Thomas Gleixner wrote:
> On Mon, Apr 14 2025 at 14:30, Frank Li wrote:
> > This patches add new API to pci-epf-core, so any EP driver can use it.
> > platform-msi: Add msi_remove_device_irq_domain() in
> > platform_device_msi_free_irqs_all()
> >
b2ba9225e031 ("misc: pci_endpoint_test: Avoid using module parameter
> to determine irqtype")
> Reviewed-by: Niklas Cassel
> Signed-off-by: Kunihiko Hayashi
Reviewed-by: Manivannan Sadhasivam
- Mani
> ---
> drivers/misc/pci_endpoint_test.c | 1 +
> 1 file change
ioctl(SET_IRQTYPE) will return an error.
>
> Suggested-by: Niklas Cassel
> Suggested-by: Manivannan Sadhasivam
> Signed-off-by: Kunihiko Hayashi
Reviewed-by: Manivannan Sadhasivam
- Mani
> ---
> drivers/misc/pci_endpoint_test.c | 18 +++---
> 1 file
Cassel
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
Documentation/PCI/endpoint/pci-test-howto.rst | 173 +---
tools/testing/selftests/Makefile | 1 +
.../testing/selftests/pci_endpoint/.gitignore | 3 +-
tools/testing/selftests/pci_endpoint/Build
Fixes: 2c156ac71c6b ("misc: Add host side PCI driver for PCI test function
device")
Reviewed-by: Damien Le Moal
Reviewed-by: Niklas Cassel
Tested-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/misc/pci_endpoint_test.c | 255 +++
tool
This just moves the existing tests under tools/pci to
tools/testing/selftests/pci_endpoint and adjusts the paths in Makefile
accordingly. Migration to Kselftest framework will be done in subsequent
commits.
Tested-by: Niklas Cassel
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
reword the error message.
Reported-by: Niklas Cassel
Closes: https://lore.kernel.org/linux-pci/Z3QtEihbiKIGogWA@ryzen
Fixes: 8353813c88ef ("PCI: endpoint: Enable DMA tests for endpoints with DMA
capabilities")
Tested-by: Niklas Cassel
Reviewed-by: Niklas Cassel
Signed-off-by:
fix for BARs on Qcom devices
* Updated documentation and also added fixture variants for memcpy & DMA modes
Manivannan Sadhasivam (4):
PCI: endpoint: pci-epf-test: Fix the check for DMA MEMCPY test
misc: pci_endpoint_test: Fix the return value of IOCTL
selftests: Move PCI Endpoint
On Thu, Jan 16, 2025 at 05:39:30PM +0100, Niklas Cassel wrote:
>
[...]
> So the output matched the suggested values in the documentation.
>
> After this series, the documentation still suggests msi == 16 and msi-x == 8,
> but the example output now shows that
> there was no failures.
>
Ah, I
On Thu, Jan 16, 2025 at 04:36:07PM +0100, Niklas Cassel wrote:
> On Thu, Jan 16, 2025 at 07:21:02PM +0530, Manivannan Sadhasivam wrote:
> > Hi,
> >
> > This series carries forward the effort to add Kselftest for PCI Endpoint
> > Subsystem started by Aman Gupta [1]
: Manivannan Sadhasivam
---
Documentation/PCI/endpoint/pci-test-howto.rst | 169 +--
tools/testing/selftests/Makefile | 1 +
.../testing/selftests/pci_endpoint/.gitignore | 3 +-
tools/testing/selftests/pci_endpoint/Build| 1 -
tools/testing/selftests/pci_endpoint
This just moves the existing tests under tools/pci to
tools/testing/selftests/pci_endpoint and adjusts the paths in Makefile
accordingly. Migration to Kselftest framework will be done in subsequent
commits.
Signed-off-by: Manivannan Sadhasivam
---
Documentation/PCI/endpoint/pci-test-howto.rst
Fixes: 2c156ac71c6b ("misc: Add host side PCI driver for PCI test function
device")
Reviewed-by: Damien Le Moal
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/misc/pci_endpoint_test.c | 255 +++
tools/pci/pcitest.c | 51 +
reword the error message.
Reported-by: Niklas Cassel
Closes: https://lore.kernel.org/linux-pci/Z3QtEihbiKIGogWA@ryzen
Fixes: 8353813c88ef ("PCI: endpoint: Enable DMA tests for endpoints with DMA
capabilities")
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/endpoint/functio
their addresses are
bouncing.
Changes in v2:
* Added a patch that fixes return values of IOCTL in pci_endpoint_test driver
* Moved the existing tests to new location before migrating
* Added a fix for BARs on Qcom devices
* Updated documentation and also added fixture variants for memcpy &
On Thu, Jan 02, 2025 at 03:23:14PM +0100, Niklas Cassel wrote:
> Hello Mani, Vinod,
>
> On Thu, Jan 02, 2025 at 12:34:04PM +0530, Manivannan Sadhasivam wrote:
> > On Tue, Dec 31, 2024 at 08:33:57PM +0100, Niklas Cassel wrote:
> > >
> > > I have some patches tha
On Tue, Dec 31, 2024 at 08:33:57PM +0100, Niklas Cassel wrote:
>
>
> On 31 December 2024 20:18:12 CET, Manivannan Sadhasivam
> wrote:
> >On Tue, Dec 31, 2024 at 06:42:42PM +0100, Niklas Cassel wrote:
> >> On Tue, Dec 31, 2024 at 06:43:41PM +0530,
On Tue, Dec 31, 2024 at 06:42:42PM +0100, Niklas Cassel wrote:
> On Tue, Dec 31, 2024 at 06:43:41PM +0530, Manivannan Sadhasivam wrote:
>
> (...)
>
> > + # RUN pci_ep_data_transfer.dma.COPY_TEST ...
> > + #OK pci_ep_data_transfer.dma
On Tue, Dec 31, 2024 at 06:17:05PM +0100, Niklas Cassel wrote:
> On Tue, Dec 31, 2024 at 06:43:40PM +0530, Manivannan Sadhasivam wrote:
> > This just moves the existing tests under tools/pci to
> > tools/testing/selftests/pci_endpoint and adjusts the paths in Makefile
> > acco
On Tue, Dec 31, 2024 at 05:57:47PM +0100, Niklas Cassel wrote:
> On Tue, Dec 31, 2024 at 06:43:39PM +0530, Manivannan Sadhasivam wrote:
> > IOCTLs are supposed to return 0 for success and negative error codes for
> > failure. Currently, this driver is returning 0 for failure and 1
(excluding MEMCPY tests)
Co-developed-by: Aman Gupta
Signed-off-by: Aman Gupta
Co-developed-by: Padmanabhan Rajanbabu
Signed-off-by: Padmanabhan Rajanbabu
[mani: reworked based on the IOCTL fix, cleanups, documentation, commit message]
Signed-off-by: Manivannan Sadhasivam
---
Documentation
This just moves the existing tests under tools/pci to
tools/testing/selftests/pci_endpoint and adjusts the paths in Makefile
accordingly. Migration to Kselftest framework will be done in subsequent
commits.
Signed-off-by: Manivannan Sadhasivam
---
Documentation/PCI/endpoint/pci-test-howto.rst
Fixes: 2c156ac71c6b ("misc: Add host side PCI driver for PCI test function
device")
Reviewed-by: Damien Le Moal
Signed-off-by: Manivannan Sadhasivam
---
drivers/misc/pci_endpoint_test.c | 250 +++
tools/pci/pcitest.c | 51 +++
2 files changed,
BARs on Qcom devices
* Updated documentation and also added fixture variants for memcpy & DMA modes
Manivannan Sadhasivam (3):
misc: pci_endpoint_test: Fix the return value of IOCTL
selftests: Move PCI Endpoint tests from tools/pci to Kselftests
selftests: pci_endpoint: Migrate to Kselftest f
On Thu, Dec 12, 2024 at 10:25:53AM +0100, Niklas Cassel wrote:
> Hello Mani,
>
> On Wed, Dec 11, 2024 at 01:31:01PM +0530, Manivannan Sadhasivam wrote:
> > Hi,
> >
> > This series carries forward the effort to add Kselftest for PCI Endpoint
> > Subsystem started
On Wed, Dec 11, 2024 at 05:37:27PM +0900, Damien Le Moal wrote:
> On 12/11/24 5:01 PM, Manivannan Sadhasivam wrote:
> > struct pci_test {
> > @@ -52,63 +51,65 @@ static int run_test(struct pci_test *test)
> > ret = ioctl(fd, PCITEST_BAR, test->barnum);
> &
)
Co-developed-by: Aman Gupta
Signed-off-by: Aman Gupta
Co-developed-by: Padmanabhan Rajanbabu
Signed-off-by: Padmanabhan Rajanbabu
[mani: reworked based on the IOCTL fix, cleanups, documentation, commit message]
Signed-off-by: Manivannan Sadhasivam
---
Documentation/PCI/endpoint/pci-test
Fixes: 2c156ac71c6b ("misc: Add host side PCI driver for PCI test function
device")
Reviewed-by: Damien Le Moal
Signed-off-by: Manivannan Sadhasivam
---
drivers/misc/pci_endpoint_test.c | 236 +++
tools/pci/pcitest.c | 47 +++---
2 files changed, 140 ins
This just moves the existing tests under tools/pci to
tools/testing/selftests/pci_endpoint and adjusts the paths in Makefile
accordingly. Migration to Kselftest framework will be done in subsequent
commits.
Signed-off-by: Manivannan Sadhasivam
---
Documentation/PCI/endpoint/pci-test-howto.rst
only_64bit flag
Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller
driver")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/cont
r memcpy & DMA modes
Manivannan Sadhasivam (4):
PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED
misc: pci_endpoint_test: Fix the return value of IOCTL
selftests: Move PCI Endpoint tests from tools/pci to Kselftests
selftests: pci_endpoint: Migrate to Kselftest framework
Do
On Fri, Nov 29, 2024 at 10:00:30PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 29, 2024 at 07:51:30PM +0900, Damien Le Moal wrote:
> > On 11/29/24 18:24, Manivannan Sadhasivam wrote:
> > > IOCTLs are supposed to return 0 for success and negative error codes for
> > &g
On Fri, Nov 29, 2024 at 01:55:37PM -0600, Bjorn Helgaas wrote:
> On Fri, Nov 29, 2024 at 02:54:12PM +0530, Manivannan Sadhasivam wrote:
> > On all Qcom endpoint SoCs, BAR0/BAR2 are 64bit BARs by default and software
> > cannot change the type. So mark the those BARs as 64bit BAR
On Fri, Nov 29, 2024 at 06:13:12PM +0100, Niklas Cassel wrote:
> On Fri, Nov 29, 2024 at 10:22:56PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Nov 29, 2024 at 05:42:26PM +0100, Niklas Cassel wrote:
> > > On Fri, Nov 29, 2024 at 10:05:55PM +0530, Manivannan Sadhasivam wro
On Fri, Nov 29, 2024 at 05:42:26PM +0100, Niklas Cassel wrote:
> On Fri, Nov 29, 2024 at 10:05:55PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Nov 29, 2024 at 02:51:26PM +0100, Niklas Cassel wrote:
> > > Hello Mani,
> > >
> > > On Fri, Nov 29, 2024 at 02:
On Fri, Nov 29, 2024 at 02:51:26PM +0100, Niklas Cassel wrote:
> Hello Mani,
>
> On Fri, Nov 29, 2024 at 02:54:15PM +0530, Manivannan Sadhasivam wrote:
> > Migrate the PCI endpoint test to Kselftest framework. All the tests that
> > were part of the previous pcitest.
On Fri, Nov 29, 2024 at 07:51:30PM +0900, Damien Le Moal wrote:
> On 11/29/24 18:24, Manivannan Sadhasivam wrote:
> > IOCTLs are supposed to return 0 for success and negative error codes for
> > failure. Currently, this driver is returning 0 for failure and 1 for
> > succes
fix for BARs on Qcom devices
* Updated documentation and also added fixture variants for memcpy & DMA modes
Manivannan Sadhasivam (4):
PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED
misc: pci_endpoint_test: Fix the return value of IOCTL
selftests: Move PCI Endpoint
)
Co-developed-by: Aman Gupta
Signed-off-by: Aman Gupta
Co-developed-by: Padmanabhan Rajanbabu
Signed-off-by: Padmanabhan Rajanbabu
[mani: reworked based on the IOCTL fix, cleanups, documentation, commit message]
Signed-off-by: Manivannan Sadhasivam
---
Documentation/PCI/endpoint/pci-test
Fixes: 2c156ac71c6b ("misc: Add host side PCI driver for PCI test function
device")
Signed-off-by: Manivannan Sadhasivam
---
drivers/misc/pci_endpoint_test.c | 236 +++
tools/pci/pcitest.c | 47 +++---
2 files changed, 140 insertions(+), 143 deletions(-
This just moves the existing tests under tools/pci to
tools/testing/selftests/pci_endpoint and adjusts the paths in Makefile
accordingly. Migration to Kselftest framework will be done in subsequent
commits.
Signed-off-by: Manivannan Sadhasivam
---
Documentation/PCI/endpoint/pci-test-howto.rst
only_64bit flag
Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller
driver")
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c
b/d
On Wed, Nov 06, 2024 at 04:37:57AM -0500, Michael S. Tsirkin wrote:
> On Fri, Jul 12, 2024 at 07:59:14PM +0530, Manivannan Sadhasivam wrote:
> > Virtio spec has so far only supported MSI-X and INTX for receiving the
> > interrupts from the virtio device on PCI transport. But
Breaking the error message will make it harder to grep for it in the
driver. So let's put the error message in a single line.
Signed-off-by: Manivannan Sadhasivam
---
drivers/virtio/virtio_pci_modern.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/v
s not have
VIRTIO_F_VERSION_1
So remove the 'virtio:' prefix which is redundant.
Signed-off-by: Manivannan Sadhasivam
---
drivers/virtio/virtio.c| 3 +--
drivers/virtio/virtio_pci_modern.c | 4 ++--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/virtio/virti
+ Jason Wang (email got truncated).
On Fri, Jul 12, 2024 at 07:59:14PM +0530, Manivannan Sadhasivam wrote:
> Virtio spec has so far only supported MSI-X and INTX for receiving the
> interrupts from the virtio device on PCI transport. But this becomes a
> limiting factor for devices s
ies such as IRQ affinity are also reused for MSI (but the
affinity setting really depends on the underlying IRQCHIP controller).
[1]
https://lore.kernel.org/virtio-comment/20240712140144.12066-1-manivannan.sadhasi...@linaro.org/
Signed-off-by: Manivannan Sadhasivam
---
drivers/virtio/virtio_pc
On Fri, Mar 22, 2024 at 08:59:12AM +0100, Luca Weiss wrote:
> On Mon Dec 4, 2023 at 6:28 PM CET, Manivannan Sadhasivam wrote:
> > On Mon, Dec 04, 2023 at 01:21:42PM +0100, Luca Weiss wrote:
> > > On Mon Dec 4, 2023 at 1:15 PM CET, Nitin Rawat wrote:
> > > >
> &
On Sun, Feb 18, 2024 at 02:13:39PM +0530, Krishna chaitanya chundru wrote:
> User space tools can't map strings if we use directly, as the string
> address is internal to kernel.
>
> So add trace point strings for the user space tools to map strings
> properly.
>
> Signed-off-by: Krishna chaitany
On Wed, Feb 21, 2024 at 09:11:03AM -0500, Steven Rostedt wrote:
> On Wed, 21 Feb 2024 11:41:46 +0530
> Manivannan Sadhasivam wrote:
>
> > On Sun, Feb 18, 2024 at 02:13:39PM +0530, Krishna chaitanya chundru wrote:
> > > User space tools can't map strings if w
gt; Signed-off-by: Krishna chaitanya chundru
Reported-by: Steven Rostedt
Reviewed-by: Manivannan Sadhasivam
- Mani
> ---
> drivers/bus/mhi/host/main.c | 4 ++--
> drivers/bus/mhi/host/trace.h | 2 ++
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/bus/m
t in both trace header file and other files.
>
> Where ever the trace events are added, debug messages are removed.
>
> Signed-off-by: Krishna chaitanya chundru
Applied to mhi-next!
- Mani
> Reviewed-by: Manivannan Sadhasivam
> Reviewed-by: "Steven Rostedt (Google)&qu
On Tue, Feb 06, 2024 at 02:33:12PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Feb 06, 2024 at 12:25:30PM +0530, Krishna Chaitanya Chundru wrote:
> >
> >
> > On 2/6/2024 11:56 AM, Manivannan Sadhasivam wrote:
> > > On Tue, Feb 06, 2024 at 10:02:05AM +0530, K
On Tue, Feb 06, 2024 at 12:25:30PM +0530, Krishna Chaitanya Chundru wrote:
>
>
> On 2/6/2024 11:56 AM, Manivannan Sadhasivam wrote:
> > On Tue, Feb 06, 2024 at 10:02:05AM +0530, Krishna chaitanya chundru wrote:
> > > This change adds ftrace support for following functi
t in both trace header file and other files.
>
> Where ever the trace events are added, debug messages are removed.
>
> Signed-off-by: Krishna chaitanya chundru
There are a lot of checkpatch errors. Please fix them and resubmit.
- Mani
> Reviewed-by: Manivannan Sadhasivam
&g
On Wed, Jan 31, 2024 at 09:54:04AM +0530, Krishna chaitanya chundru wrote:
> This change adds ftrace support for following functions which
> helps in debugging the issues when there is Channel state & MHI
> state change and also when we receive data and control events:
> 1. mhi_intvec_mhi_states
>
t in both trace header file and other files.
>
> Where ever the trace events are added, debug messages are removed.
>
> Signed-off-by: Krishna chaitanya chundru
Reviewed-by: Manivannan Sadhasivam
- Mani
> Reviewed-by: "Steven Rostedt (Google)"
> ---
> Changes i
On Tue, Jan 30, 2024 at 09:22:52AM -0500, Steven Rostedt wrote:
> On Tue, 30 Jan 2024 13:41:52 +0530
> Manivannan Sadhasivam wrote:
>
> > So same trace will get printed for both mhi_channel_command_start() and
> > mhi_channel_command_end()?
>
> The trace output will
On Fri, Jan 05, 2024 at 05:53:03PM +0530, Krishna chaitanya chundru wrote:
> This change adds ftrace support for following functions which
> helps in debugging the issues when there is Channel state & MHI
> state change and also when we receive data and control events:
> 1. mhi_intvec_mhi_states
>
additions as written in the cover letter]
> Signed-off-by: Luca Weiss
Acked-by: Manivannan Sadhasivam
- Mani
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 74
> +++-
> 1 file changed, 73 insertions(+), 1 deletion(-)
>
> diff --git a/a
On Tue, Dec 05, 2023 at 08:51:05AM +0100, Luca Weiss wrote:
> On Mon Dec 4, 2023 at 6:28 PM CET, Manivannan Sadhasivam wrote:
> > On Mon, Dec 04, 2023 at 01:21:42PM +0100, Luca Weiss wrote:
> > > On Mon Dec 4, 2023 at 1:15 PM CET, Nitin Rawat wrote:
> > > >
> &
On Mon, Dec 04, 2023 at 01:21:42PM +0100, Luca Weiss wrote:
> On Mon Dec 4, 2023 at 1:15 PM CET, Nitin Rawat wrote:
> >
> >
> > On 12/4/2023 3:54 PM, Luca Weiss wrote:
> > > From: Nitin Rawat
> > >
> > > Add UFS host controller and PHY nodes for sc7280 soc.
> > >
> > > Signed-off-by: Nitin Rawat
On Mon, Nov 27, 2023 at 04:39:12PM +0530, Krishna chaitanya chundru wrote:
> This change adds ftrace support for following functions which
> helps in debugging the issues when there is Channel state & MHI
> state change and also when we receive data and control events:
> 1. mhi_intvec_mhi_states
>
Hi Greg,
On Sun, Apr 11, 2021 at 08:57:03AM +0200, Greg KH wrote:
> On Sun, Apr 11, 2021 at 11:25:59AM +0530, Manivannan Sadhasivam wrote:
> > Hi Greg,
> >
> > Here is the MHI Pull request for the v5.13 cycle. I stayed with the PR as
> > the
> > number patche
: pci_generic: Add FIREHOSE channels
Manivannan Sadhasivam (2):
bus: mhi: pci_generic: Constify mhi_controller_config struct definitions
bus: mhi: core: Fix shadow declarations
drivers/bus/mhi/core/boot.c | 64 ++--
drivers/bus/mhi/core/debugfs.c | 2 +-
drivers/bus/mhi/core
On Fri, Apr 09, 2021 at 08:44:07AM -0500, Alex Elder wrote:
> The IPA core clock is required for SDX55. Define it.
>
> Signed-off-by: Alex Elder
I tested this patch on couple of SDX55 based boards like Telit FN980 and
Thundercomm T55. Hence,
Tested-by: Manivannan Sadhasivam
A
On Thu, Apr 08, 2021 at 03:02:20AM -0700, Jarvis Jiang wrote:
> The word 'rung' is a typo in below comment, fix it.
> * @event_ring: The event rung index that services this channel
>
> Signed-off-by: Jarvis Jiang
Applied to mhi-next!
Thanks,
Mani
> ---
> include/linux/mhi.h | 2 +-
> 1 file c
On Thu, Apr 08, 2021 at 03:02:20AM -0700, Jarvis Jiang wrote:
> The word 'rung' is a typo in below comment, fix it.
> * @event_ring: The event rung index that services this channel
>
> Signed-off-by: Jarvis Jiang
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> -
On Fri, Apr 09, 2021 at 08:49:45AM +0800, Bixuan Cui wrote:
> There is a error message after devm_ioremap_resource failed, and the ret
> is needs to be obtained through PTR_ERR(qcom->qscratch_base).
> We need to move the dev_err() downwards to ensure that the ret value is
> correct.
>
> Fixes: a43
ter balanced.
>
> Reported-by: Hulk Robot
> Signed-off-by: Wang Li
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> drivers/spi/spi-qup.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
> index 8d
", ret);
Does the userspace need to know how many bytes were not copied? I don't
think this is a useful information. So you could remove this err print.
With that,
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> + return -EFAULT;
> + }
> +
> +
On Sun, Apr 04, 2021 at 12:17:52PM -0500, Bjorn Andersson wrote:
> On Fri 02 Apr 01:17 CDT 2021, Deepak Kumar Singh wrote:
>
> > Not all upcoming usecases will have an interface to allow the aoss
> > driver to hook onto. Expose the send api and create a get function to
> > enable drivers to send t
On Fri, Apr 09, 2021 at 09:54:24AM +0800, Jia Yang wrote:
> devm_ioremap_resource() has recorded error log, so it's
> unnecessary to record log again.
>
> Reported-by: Hulk Robot
> Signed-off-by: Jia Yang
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> dr
> cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
> if (!cpu0_base) {
> pr_err("Failed to map source base\n");
> - return -EINVAL;
Missing "ret = -EINVAL" assignment. With that fixed,
Reviewed-by: Manivan
On Thu, Apr 08, 2021 at 09:55:09PM +0800, Chen Hui wrote:
> Add missing MODULE_DEVICE_TABLE entries to support module autoloading,
> as these drivers can be compiled as external modules.
>
> Signed-off-by: Chen Hui
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
> dr
On Fri, Apr 09, 2021 at 10:33:49AM +0800, Laibin Qiu wrote:
> devm_ioremap_resource() has recorded error log, so it's
> unnecessary to record log again.
>
> Reported-by: Hulk Robot
> Signed-off-by: Laibin Qiu
Reviewed-by: Manivannan Sadhasivam
Thanks,
Mani
> ---
local [-Wshadow]
856 | enum mhi_pm_state new_state;
| ^
drivers/bus/mhi/core/main.c:837:19: note: shadowed declaration is here
837 |enum mhi_state new_state;
| ^
Signed-off-by: Manivannan Sadhasivam
---
Changes in v3
Add remoteproc support for Hexagon modem found on the Qualcomm SDX55
platform.
Signed-off-by: Manivannan Sadhasivam
---
drivers/remoteproc/qcom_q6v5_pas.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc
Enable the Qualcomm Q6V5_PAS (Peripheral Authentication Service)
remoteproc driver to manage the modem co-processor in SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b
Not all platforms are able to allocate CMA size of 256MB. One such
platform is SDX55. Hence, use the standard 64MB size for CMA.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/configs
Enable the Qualcomm GLINK SMEM driver to support GLINK protocol over
shared memory.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 5955aeb0646e
Enable interconnect driver for SDX55 platform to manage the interconnect
providers.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 695612829503
Enable CPUFreq and CPUFreq DT drivers to carry out CPU Frequency scaling
duties on platforms like SDX55.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs
Enable A7 PLL driver and APCS clock driver on SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 0b9da27f923a..02f6185f31a6 100644
Enable Qualcomm APCS IPC mailbox driver for IPC communication between
application processor and other masters in platforms like SDX55.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b
Hi Bjorn,
This series updates the qcom_defconfig by enabling the drivers required
for the SDX55 platform.
Please consider merging!
Thanks,
Mani
Manivannan Sadhasivam (7):
ARM: configs: qcom_defconfig: Enable APCS IPC mailbox driver
ARM: configs: qcom_defconfig: Enable SDX55 A7 PLL and APCS
Add modem support to SDX55 using the PAS remoteproc driver.
Signed-off-by: Manivannan Sadhasivam
---
.../boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 5 +++
arch/arm/boot/dts/qcom-sdx55.dtsi | 33 +++
2 files changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts
Add devicetree binding for SDX55 remoteproc.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc
Thundercomm T55 is the development platform based on the Qualcomm SDX55
chipset. This basic support includes support for debug serial, NAND
flash, BAM DMA, USB and regulators support.
https://www.thundercomm.com/app_en/product/1593506006365532
Signed-off-by: Manivannan Sadhasivam
---
arch/arm
Add devicetree binding for Thundercomm T55 Dev kit based on SDX55.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm
Telit FN980 TLB is the development platform based on the Qualcomm SDX55
chipset. This basic support includes support for debug serial, NAND
flash, BAM DMA, USB and regulators support.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/Makefile| 3 +-
.../boot/dts
Add devicetree binding for Telit FN980 TLB board based on SDX55.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm
Use the common "nand-controller" node name for NAND controller node to
fix the `make dtbs_check` validation for Qcom platforms.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +-
2 files changed, 2 insert
Add interconnect nodes for the providers in SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 33 +++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot/dts/qcom-sdx55.dtsi
Add SCM node to enable SCM functionality on SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot/dts/qcom-sdx55.dtsi
index 4ca871735025
Add devicetree compatible for SCM present in SDX55 platform.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings
Add a simple-mfd representing IMEM on SDX55 and define the PIL
relocation info region, so that post mortem tools will be able to locate
the loaded remoteproc.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff
Add SMP2P nodes for the SDX55 platform to communicate with the modem.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot/dts/qcom-sdx55
Add CPUFreq support to SDX55 platform using the cpufreq-dt driver.
There is no dedicated hardware block available on this platform to
carry on the CPUFreq duties. Hence, it is accomplished using the CPU
clock and regulators tied together by the operating points table.
Signed-off-by: Manivannan
The APCS block on SDX55 acts as a mailbox controller and also provides
clock output for the Cortex A7 CPU.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi
b/arch/arm/boot
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