On Wed, 26 Aug 2020 12:16:45 +0100,
Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Retrieve the PCI device from the msi descriptor instead of doing so at the
> call sites.
>
> Signed-off-by: Thomas Gleixner
> Acked-by: Bjorn Helgaas
Acked-by: Marc Zyngier
msi_prepare);
>
> -void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
> -{
> - arg->desc = desc;
> - arg->hwirq = pci_msi_domain_calc_hwirq(desc);
> -}
> -EXPORT_SYMBOL_GPL(pci_msi_set_desc);
I think that at this stage, pci_msi_domain_calc_hwirq() can be made
100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -1544,7 +1544,7 @@ int irq_chip_compose_msi_msg(struct irq_data *data,
struct msi_msg *msg)
struct irq_data *pos = NULL;
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
- for (; data; data = data->parent_data)
+ for (; data && !pos; data = data->parent_data)
#endif
if (data->chip && data->chip->irq_compose_msi_msg)
pos = data;
Though the for loop in a #ifdef in admittedly an acquired taste...
Reviewed-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
irqs(struct irq_dom
> }
>
> /**
> + * __msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain
> associated tp @dev
Spurious __.
> + * @domain: The domain to managing the interrupts
> + * @dev: Pointer to device struct of the device for which the interrupts
> + * are free
> + */
> +void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
> +{
> + struct msi_domain_info *info = domain->host_data;
> + struct msi_domain_ops *ops = info->ops;
Same thing?
> +
> + return ops->domain_free_irqs(domain, dev);
> +}
> +
> +/**
> * msi_get_domain_info - Get the MSI interrupt domain info for @domain
> * @domain: The interrupt domain to retrieve data from
> *
Otherwise looks good to me:
Reviewed-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
On Wed, 26 Aug 2020 17:37:30 +0100,
Marc Zyngier wrote:
>
> Hi Valentin,
>
> On 2020-08-26 12:16, Valentin Schneider wrote:
> > Hi Marc,
> >
> > Many thanks for picking this up!
> > Below's the only comment I have, the rest LGTM.
> >
> > O
Hi Valentin,
On 2020-08-26 12:16, Valentin Schneider wrote:
Hi Marc,
Many thanks for picking this up!
Below's the only comment I have, the rest LGTM.
On 24/08/20 11:23, Marc Zyngier wrote:
Signed-off-by: Marc Zyngier
---
drivers/bus/fsl-mc/fsl-mc-msi.c | 2 ++
1 file changed, 2 inser
that the mapping was indeed correct and bail out if not.
Cc: sta...@vger.kernel.org
Signed-off-by: Marc Zyngier
---
* From v1:
- Dropped the input.c changes, and turned hid_map_usage() into
the validation primitive.
- Handle mapping failures in hidinput_configure_usage() and
mt_touch_inp
Hi Dmitry,
On 2020-08-24 20:51, Dmitry Torokhov wrote:
Hi Marc,
On Mon, Aug 17, 2020 at 12:26:59PM +0100, Marc Zyngier wrote:
When calling into input_set_capability(), the passed event code is
blindly used to set a bit in a number of bitmaps, without checking
whether this actually fits the
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: 7828a3ef8646fb2e69ed45616c8453a037ca7867
Gitweb:
https://git.kernel.org/tip/7828a3ef8646fb2e69ed45616c8453a037ca7867
Author:Marc Zyngier
AuthorDate:Thu, 06 Aug 2020 10:57:45 +01:00
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: a150dac5a8fb711fdc378c23f44bee4546f04246
Gitweb:
https://git.kernel.org/tip/a150dac5a8fb711fdc378c23f44bee4546f04246
Author:Marc Zyngier
AuthorDate:Tue, 25 Aug 2020 10:38:39 +01:00
arm64: dts: k3-j721e: ti-sci-inta/intr: Update to latest bindings
arm64: dts: k3-am65: ti-sci-inta/intr: Update to latest bindings
arm64: dts: k3-am65: Update the RM resource types
Marc Zyngier (2):
irqchip: Fix probing deferal when using IRQCHIP_PLATFORM_DRIVER helpers
irq
e IRQ line into the root
interrupt controller (i.e. the component actually fireing the
Acked-by: Marc Zyngier
M.
--
Jazz is not dead. It just smells funny...
infrastructure just for KVM on arm, instead just remove the conditional
reschedule.
Cc: # v4.14 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
---
virt/kvm/arm/mmu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kv
infrastructure just for KVM on arm, instead just remove the conditional
reschedule.
Cc: # v4.4 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
---
arch/arm/kvm/mmu.c | 8
1 file changed, 8 deletions(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/ar
infrastructure just for KVM on arm, instead just remove the conditional
reschedule.
Cc: # v4.9 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
---
arch/arm/kvm/mmu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/ar
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-mvebu-sei.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-mvebu-sei.c b/drivers/irqchip/irq-mvebu-sei.c
index 18832ccc8ff8..4fc258649785 100644
--- a/drivers/irqchip/irq-mvebu-sei.c
+++ b/drivers/irqchip/irq-mvebu
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 95f097448f97..2808545a963e 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq
h all the stacked interrupt controllers that
can pile on a GIC to use the hierarchy-based retrigger helper. This
includes the bus-specific irqchips, such as PCI, FSL-MC, and the funky
platform-MSI.
Marc Zyngier (7):
irqchip/git-v3-its: Implement irq_retrigger callback for
device-triggered LPIs
irq_chip.irq_retrigger() for the GIC chips by setting the GIC
pending bit of the relevant IRQ. After being called by check_irq_resend(),
this will eventually trigger a *new* interrupt which we will handle as usual.
Signed-off-by: Valentin Schneider
Signed-off-by: Marc Zyngier
Link:
https://lore.kernel.org
Signed-off-by: Marc Zyngier
---
drivers/bus/fsl-mc/fsl-mc-msi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/bus/fsl-mc/fsl-mc-msi.c b/drivers/bus/fsl-mc/fsl-mc-msi.c
index 8edadf05cbb7..5306ba7dea3e 100644
--- a/drivers/bus/fsl-mc/fsl-mc-msi.c
+++ b/drivers/bus/fsl-mc/fsl-mc
Signed-off-by: Marc Zyngier
---
drivers/base/platform-msi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/base/platform-msi.c b/drivers/base/platform-msi.c
index c4a17e5edf8b..0a043936b259 100644
--- a/drivers/base/platform-msi.c
+++ b/drivers/base/platform-msi.c
@@ -101,6 +101,8
Schneider
Signed-off-by: Marc Zyngier
Link:
https://lore.kernel.org/r/20200730170321.31228-3-valentin.schnei...@arm.com
---
drivers/irqchip/irq-gic-v3.c | 5 -
drivers/irqchip/irq-gic.c| 6 +-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-mbigen.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index ff7627b57772..8af35225b46d 100644
--- a/drivers/irqchip/irq-mbigen.c
+++ b/drivers/irqchip/irq-mbigen.c
@@ -142,6
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-mvebu-icu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
index 91adf771f185..02f4cc899824 100644
--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu
Signed-off-by: Marc Zyngier
---
drivers/pci/msi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 30ae4ffda5c1..c4d31ce2d951 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -1446,6 +1446,8 @@ static void pci_msi_domain_update_chip_ops
Hi Steven,
On Wed, 19 Aug 2020 09:54:40 +0100,
Steven Price wrote:
>
> On 18/08/2020 15:41, Marc Zyngier wrote:
> > On 2020-08-17 09:41, Keqian Zhu wrote:
> >> Hi all,
> >>
> >> This patch series picks up the LPT pvtime feature originall
Hi Enric,
On 2020-08-21 10:20, Enric Balletbo i Serra wrote:
Hi Marc,
On 20/8/20 16:53, Marc Zyngier wrote:
On 2020-08-20 09:07, Saravana Kannan wrote:
On Thu, Aug 20, 2020 at 12:56 AM Marc Zyngier wrote:
On 2020-08-19 19:51, Saravana Kannan wrote:
> On Wed, Aug 19, 2020 at 9:52 AM Fr
On 2020-08-20 09:07, Saravana Kannan wrote:
On Thu, Aug 20, 2020 at 12:56 AM Marc Zyngier wrote:
On 2020-08-19 19:51, Saravana Kannan wrote:
> On Wed, Aug 19, 2020 at 9:52 AM Frank Wunderlich
> wrote:
>>
>> hi,
>>
>> does the fix you've linked to my revert
On 2020-08-20 13:36, Daniel Palmer wrote:
Hi Mark-PK, Marc
I'm not sure this will be the final version but I'm going to try to
integrate this with my current MStar/SigmaStar tree over the weekend
and then I guess I can give this a tested-by?
That'd be good.
Assuming this version or the next
On 2020-08-19 19:06, Paul Cercueil wrote:
All the wakeup sources we possibly want will go through the interrupt
controller, so the parent IRQ must not be masked during suspend, or
there won't be any way to wake up the system.
Signed-off-by: Paul Cercueil
Do you have a Fixes: tag? Does it need
On 2020-08-19 19:51, Saravana Kannan wrote:
On Wed, Aug 19, 2020 at 9:52 AM Frank Wunderlich
wrote:
hi,
does the fix you've linked to my revert [1] not work in your case?
[1] https://patchwork.kernel.org/patch/11718481/
Thanks for pointing it out Frank. Also, might want to avoid top
postin
On 2020-08-19 15:55, Mark-PK Tsai wrote:
From: Marc Zyngier
On 2020-08-19 14:31, Mark-PK Tsai wrote:
From: Marc Zyngier
> +
> +static int mst_intc_domain_alloc(struct irq_domain *domain, unsigned
> int virq,
> + unsigned int nr_irqs, void *data)
>
On 2020-08-19 14:31, Mark-PK Tsai wrote:
From: Marc Zyngier
> +
> +static int mst_intc_domain_alloc(struct irq_domain *domain, unsigned
> int virq,
> + unsigned int nr_irqs, void *data)
> +{
> + int i;
> + irq_hw_number_t hwirq;
> + struct
t;,
A warning will hopefully nudge the user into updating their
DT to a fixed version if they can, but the incentive is
obviously pretty small.
Fixes: 2f96593ecc37 ("of_address: Add bus type match for pci ranges parser")
Suggested-by: Rob Herring
Signed-off-by: Marc Zyngier
---
drive
On 2020-08-19 03:39, qiuguorui1 wrote:
In the previous code, when the eoi handle of the exti clears the
pending
bit of the current interrupt, it will first read the values of fpr and
rpr, then logically OR the corresponding bit of the interrupt number,
and finally write back to fpr and rpr.
We
On 2020-08-19 04:42, Mark-PK Tsai wrote:
Add MStar interrupt controller support using hierarchy irq
domain.
Signed-off-by: Mark-PK Tsai
---
drivers/irqchip/Kconfig| 7 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-mst-intc.c | 195 +
3
On Tue, 18 Aug 2020 18:42:41 +0100,
Cristian Ciocaltea wrote:
>
> Hi Marc,
>
> Thanks for your quick and detailed review!
>
> On Mon, Aug 17, 2020 at 02:52:06PM +0100, Marc Zyngier wrote:
> > On 2020-08-16 12:33, Cristian Ciocaltea wrote:
> > > This contr
On 2020-08-18 18:48, Saravana Kannan wrote:
On Tue, Aug 18, 2020 at 10:34 AM Marc Zyngier wrote:
[...]
OK. So how about something like this?
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 590493e04b01..a7a6ee599b14 100644
--- a/drivers/of/address.c
+++ b/drivers/of
On 2020-08-18 15:23, Rob Herring wrote:
On Tue, Aug 18, 2020 at 1:35 AM Marc Zyngier wrote:
On 2020-08-17 17:12, Rob Herring wrote:
> On Sun, Aug 16, 2020 at 4:40 AM Marc Zyngier wrote:
>>
>> On Sun, 16 Aug 2020 00:22:28 +0100,
>> Bjorn Helgaas wrote:
>> >
>
arm64: dts: k3-j721e: ti-sci-inta/intr: Update to latest bindings
arm64: dts: k3-am65: ti-sci-inta/intr: Update to latest bindings
arm64: dts: k3-am65: Update the RM resource types
Marc Zyngier (1):
irqchip: Fix probing deferal when using IRQCHIP_PLATFORM_DRIVER helpers
.../bin
On 2020-08-17 09:41, Keqian Zhu wrote:
Hi all,
This patch series picks up the LPT pvtime feature originally developed
by Steven Price: https://patchwork.kernel.org/cover/10726499/
Backgroud:
There is demand for cross-platform migration, which means we have to
solve different CPU features and a
On Tue, 11 Aug 2020 11:27:23 +0100, Will Deacon wrote:
> While stress-testing my arm64 stage-2 page-table rewrite [1], I ran into
> a sleeping while atomic BUG() during OOM that I can reproduce with
> mainline.
>
> The problem is that the arm64 page-table code periodically calls
> cond_resched_loc
On 2020-08-18 11:16, Will Deacon wrote:
On Tue, Aug 18, 2020 at 08:31:08AM +0200, Paolo Bonzini wrote:
On 11/08/20 12:27, Will Deacon wrote:
> Will Deacon (2):
> KVM: Pass MMU notifier range flags to kvm_unmap_hva_range()
> KVM: arm64: Only reschedule if MMU_NOTIFIER_RANGE_BLOCKABLE is not s
On 2020-08-17 17:12, Rob Herring wrote:
On Sun, Aug 16, 2020 at 4:40 AM Marc Zyngier wrote:
On Sun, 16 Aug 2020 00:22:28 +0100,
Bjorn Helgaas wrote:
>
> On Sat, Aug 15, 2020 at 01:51:11PM +0100, Marc Zyngier wrote:
> > Recent changes to the DT PCI bus parsing made it mandatory fo
On 2020-08-17 15:57, Frank Wunderlich wrote:
From: Frank Wunderlich
This reverts commit f97dbf48ca43009e8b8bcdf07f47fc9f06149b36 which
breaks bootup of arm/arm64 devices like bananapi-r2/mt7623 and
bananapi-r64/mt7622
Signed-off-by: Frank Wunderlich
---
drivers/irqchip/irq-mtk-sysirq.c | 4 +
On 2020-08-16 12:33, Cristian Ciocaltea wrote:
This controller appears on Actions Semi Owl family SoC's S500, S700 and
S900 and provides support for 3 external interrupt controllers through
Is that really 3 interrupt controllers? Or merely 3 interrupt lines?
dedicated SIRQ pins.
Each line ca
, then virtual counter trigger an event for
every
two cycles.
Signed-off-by: Marc Zyngier
I have never given you this tag, you are making it up. Please read
Documentation/process/submitting-patches.rst to understand what
tag you can put by yourself.
At best, put "Suggested-by" tag,
On 2020-08-17 13:24, Keqian Zhu wrote:
In commit 0ea415390cd3 (clocksource/arm_arch_timer: Use
arch_timer_read_counter
to access stable counters), we separate stable and normal count reader.
Actually
the stable reader can correctly lead us to normal reader if we has no
workaround.
Resulting i
On 2020-08-17 11:20, Guillaume Tucker wrote:
Please see the bisection report below about a boot failure.
Reports aren't automatically sent to the public while we're
trialing new bisection features on kernelci.org but this one
looks valid.
The log doesn't appear to be showing anything from the k
On 2020-08-17 11:11, Enric Balletbo i Serra wrote:
Hi Guillaume et all,
On 17/8/20 12:02, Guillaume Tucker wrote:
Hi,
Please see the bisection report below about a driver probe
regression with rockchip-pcie.
Reports aren't automatically sent to the public while we're
trialing new bisection fe
On 2020-08-17 13:03, yezengruan wrote:
On 2020/8/17 10:03, Sergey Senozhatsky wrote:
On (20/07/21 13:17), Sergey Senozhatsky wrote:
Hello,
RFC
We noticed that in a number of cases when we wake_up_process()
on arm64 guest we end up enqueuing that task on a preempted VCPU. The
g the raw event code, sanitize it to the actual bitmap
size and output a warning to let the user know.
While we're at it, sanitize the hid_usage structure if the type isn't
known, conveniently placing a NULL pointer as the bitmap in order to
catch unexpected uses.
Cc: sta...@vger.kerne
a...@vger.kernel.org
Signed-off-by: Marc Zyngier
---
drivers/input/input.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/input/input.c b/drivers/input/input.c
index 3cfd2c18eebd..1e77cf47aa44 100644
--- a/drivers/input/input.c
+++ b/drivers/input
top bits of the event code (all capability bitmaps are
conveniently sized as power of twos), and spitting out a warning for
further debugging.
Marc Zyngier (2):
Input; Sanitize event code before modifying bitmaps
HID: core; Sanitize event code and type before mapping input
drivers/input
On 2020-08-17 04:37, Keqian Zhu wrote:
ARM64 PV-time ST is configured by userspace through vCPU attribute,
and KVM_DEV_TYPE_ARM_PV_TIME is unused.
Signed-off-by: Keqian Zhu
---
include/uapi/linux/kvm.h | 2 --
tools/include/uapi/linux/kvm.h | 2 --
2 files changed, 4 deletions(-)
diff -
On Sun, 16 Aug 2020 00:22:28 +0100,
Bjorn Helgaas wrote:
>
> On Sat, Aug 15, 2020 at 01:51:11PM +0100, Marc Zyngier wrote:
> > Recent changes to the DT PCI bus parsing made it mandatory for
> > device tree nodes describing a PCI controller to have the
> > 'device_t
be the controller anymore.
Add the missing property makes the PCIe node compliant. While we
are at it, drop the pointless linux,pci-domain property, which only
makes sense when there are multiple host bridges.
Signed-off-by: Marc Zyngier
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
1
eployed at this stage are pretty slim, so the above
hack is in for the long run.
Marc Zyngier (2):
PCI: rockchip: Work around missing device_type property in DT
arm64: dts: rockchip: Fix PCIe DT properties
arch/arm64/boot/dts/rockchip/rk3399.dtsi| 2 +-
drivers/pci/controller/pcie-rockc
boot time. A warning will hopefully nudge the
user into updating their DT to a fixed version if they can, but
the insentive is obviously pretty small.
Fixes: 2f96593ecc37 ("of_address: Add bus type match for pci ranges parser")
Suggested-by: Roh Herring
Signed-off-by: Marc Zyngier
---
d
On 2020-08-14 23:51, Rob Herring wrote:
On Fri, Aug 14, 2020 at 12:21 PM Marc Zyngier wrote:
Hi all,
On 2020-07-28 16:36, Jiaxun Yang wrote:
> So the parser can be used to parse range property of ISA bus.
>
> As they're all using PCI-like method of range property, there is no
On 2020-08-13 09:08, Thomas Gleixner wrote:
Yunfeng Ye writes:
[...]
You are looking at the wrong file. /proc/irq/$IRQ/smp_affinity* is the
possible mask. If you want to know to which CPU an interrupt is affine
then look at /proc/irq/$IRQ/effective_affinity*
If effective_affinity* is not sh
e following hack, which solves the issue for
me. Definitely not my finest hour, but I really need this box
to keep going. I will post a patch fixing the DT separately.
Thanks,
M.
From ceef5fd9c4d2005eb577505c68868ebe527c098f Mon Sep 17 00:00:00 2001
From: Marc Zyngier
Date: Fri, 14 A
On 2020-08-14 05:34, Sai Prakash Ranjan wrote:
On 2020-08-13 23:29, Marc Zyngier wrote:
[...]
We'd need to disable the late onlining of CPUs that would change
the mitigation state, and this is... ugly.
Ugh, yes indeed and here I was thinking that these things are
straightforward :(
On 2020-08-14 00:17, Kees Cook wrote:
The return code for attempting to execute a directory has always been
EACCES. Adjust the S_ISDIR exec test to reflect the old errno instead
of the general EISDIR for other kinds of "open" attempts on
directories.
Reported-by: Marc Zyngier
L
On 2020-08-13 13:33, Sai Prakash Ranjan wrote:
On 2020-08-13 16:09, Marc Zyngier wrote:
On 2020-08-13 10:40, Will Deacon wrote:
On Thu, Aug 13, 2020 at 02:49:37PM +0530, Sai Prakash Ranjan wrote:
On 2020-08-13 14:33, Will Deacon wrote:
> On Thu, Aug 13, 2020 at 01:48:34PM +0530, Sai Prak
On Fri, 5 Jun 2020 09:00:12 -0700
Kees Cook wrote:
Hi Kees,
> The execve(2)/uselib(2) syscalls have always rejected non-regular
> files. Recently, it was noticed that a deadlock was introduced when trying
> to execute pipes, as the S_ISREG() test was happening too late. This was
> fixed in comm
On 2020-08-13 10:40, Will Deacon wrote:
On Thu, Aug 13, 2020 at 02:49:37PM +0530, Sai Prakash Ranjan wrote:
On 2020-08-13 14:33, Will Deacon wrote:
> On Thu, Aug 13, 2020 at 01:48:34PM +0530, Sai Prakash Ranjan wrote:
> > KRYO4XX gold/big CPU cores are based on Cortex-A76 which has CSV2
> > bits
On 2020-08-13 07:03, Jason Liu wrote:
-Original Message-
From: Marc Zyngier
Sent: Thursday, August 6, 2020 8:26 PM
To: Jason Liu
Cc: Sudeep Holla ; catalin.mari...@arm.com;
w...@kernel.org; sas...@kernel.org; linux-kernel@vger.kernel.org;
linux-arm-ker...@lists.infradead.org
Subject
Hi Sumit,
On 2020-08-11 14:15, Sumit Garg wrote:
Hi Marc,
On Thu, 25 Jun 2020 at 01:28, Marc Zyngier wrote:
For as long as SMP ARM has existed, IPIs have been handled as
something special. The arch code and the interrupt controller exchange
a couple of hooks (one to generate an IPI, another
dw-apb-ictl.o
obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
obj-$(CONFIG_OMPIC)+= irq-ompic.o
Acked-by: Marc Zyngier
M.
--
Jazz is not dead. It just smells funny...
On 2020-08-06 21:09, John Stultz wrote:
On Thu, Aug 6, 2020 at 12:59 PM Marc Zyngier wrote:
OK, thanks for confirming. It would have been good if these patches
had seen a bit more testing.
Yes, again, my apologies for that!
I would say this should be the job of the patch author, before
On 2020-08-06 19:05, Saravana Kannan wrote:
On Thu, Aug 6, 2020 at 5:12 AM Marc Zyngier wrote:
On 2020-08-06 02:24, John Stultz wrote:
[...]
>> + if (par_np == np)
>> + par_np = NULL;
>> +
>> + /*
>> + * If there's a parent interrupt contro
On 2020-08-06 11:05, Jason Liu wrote:
-Original Message-
From: Marc Zyngier
[...]
> No, this patch is not papering over a much deeper issue in the driver.
> This is just to make things better for the ARM64 kexec.
Yes, I'm sure it is... However:
request_irq()
clock off
On 2020-08-06 15:58, Daniel Palmer wrote:
Hi Mark-PK,
On Thu, 6 Aug 2020 at 23:08, Mark-PK Tsai
wrote:
> Do you know if it would be possible to confirm if they are
> the
> same thing? MediaTek bought MStar a few years ago so it seems likely
> but I have no hard information.
>
Yes, it's for t
Hi Kun,
On 2020-08-06 03:26, yangerkun wrote:
Hi,
Not familiar with kvm. And I have a question about this patch. Maybe
backport this patch 3204be4109ad("KVM: arm64: Make vcpu_cp1x() work on
Big Endian hosts") without 52f6c4f02164 ("KVM: arm64: Change 32-bit
handling of VM system registers") see
On 2020-08-06 11:03, Daniel Palmer wrote:
Hi Marc,
On Thu, 6 Aug 2020 at 01:26, Marc Zyngier wrote:
> +struct msc313_intc {
> + struct irq_domain *domain;
> + void __iomem *base;
> + struct irq_chip irqchip;
Why do you need to embed the irq_chip on a per-cont
On 2020-08-06 02:24, John Stultz wrote:
On Wed, Aug 5, 2020 at 1:19 PM Saravana Kannan
wrote:
On Wed, Aug 5, 2020 at 12:44 AM John Stultz
wrote:
> On Fri, Jul 17, 2020 at 5:06 PM Saravana Kannan wrote:
> >
> > Switch the driver to use the helper macros. In addition to reducing the
> > number
[+ Mark-PK Tsai]
Hi Daniel,
On 2020-08-05 12:00, Daniel Palmer wrote:
Add a driver for the two peripheral interrupt controllers
in MStar MSC313 and other MStar/Sigmastar Armv7 SoCs.
Supports both the "IRQ" and "FIQ" controllers that
forward interrupts from the various IP blocks inside the
SoC
On 2020-08-05 10:54, Greg Kroah-Hartman wrote:
On Tue, Aug 04, 2020 at 10:23:06PM +0100, Marc Zyngier wrote:
On 2020-08-04 19:33, Linus Torvalds wrote:
> On Tue, Aug 4, 2020 at 1:21 AM Greg Kroah-Hartman
> wrote:
> >
> > So Linus's tree is also broken here.
>
> No,
On 2020-08-05 07:31, Jason Liu wrote:
-Original Message-
From: Sudeep Holla
Sent: Tuesday, August 4, 2020 7:39 PM
To: Marc Zyngier
Cc: Jason Liu ; catalin.mari...@arm.com;
w...@kernel.org; linux-kernel@vger.kernel.org; Sudeep Holla
; linux-arm-ker...@lists.infradead.org
Subject: Re
On 2020-08-04 19:33, Linus Torvalds wrote:
On Tue, Aug 4, 2020 at 1:21 AM Greg Kroah-Hartman
wrote:
So Linus's tree is also broken here.
No, there's 835d1c3a9879 ("arm64: Drop unnecessary include from
asm/smp.h") upstream.
My bet is that Greg ended up with this patch backported to
5.7, but
On 2020-08-04 16:40, Alex Bennée wrote:
Marc Zyngier writes:
On 2020-08-04 15:44, Alex Bennée wrote:
Marc Zyngier writes:
On 2020-08-04 13:44, Alex Bennée wrote:
The VIRTIO_PCI support is an idealised PCI bus, we don't need a
bunch
of bloat for real world hardware for a VirtIO
On 2020-08-04 15:44, Alex Bennée wrote:
Marc Zyngier writes:
On 2020-08-04 13:44, Alex Bennée wrote:
The VIRTIO_PCI support is an idealised PCI bus, we don't need a bunch
of bloat for real world hardware for a VirtIO guest.
Who says this guest will only have virtio devices?
This is
On 2020-08-04 13:44, Alex Bennée wrote:
The VIRTIO_PCI support is an idealised PCI bus, we don't need a bunch
of bloat for real world hardware for a VirtIO guest.
Who says this guest will only have virtio devices?
Or even, virtio devices without bugs? Given that said device can
come from any V
On 2020-08-04 09:56, Jason Liu wrote:
No need to do the irq_chip->irq_mask() if it already masked.
BTW, unconditionally do the irq_chip->irq_mask() will also bring issues
when the irq_chip in the runtime PM suspend. Accessing registers of the
irq_chip will bring in the exceptions. For example on
On 2020-08-03 16:03, Mark-PK Tsai wrote:
From: Marc Zyngier
On 2020-08-03 07:22, Mark-PK Tsai wrote:
> Add mt58xx interrupt controller support using hierarchy irq
> domain.
>
> Signed-off-by: Mark-PK Tsai
> ---
> drivers/irqchip/Kconfig | 7 ++
> drivers/irqch
On 2020-08-03 12:48, Valentin Schneider wrote:
On 03/08/20 12:38, Vladimir Oltean wrote:
On Mon, Aug 03, 2020 at 10:51:32AM +0100, Robin Murphy wrote:
Having glanced across another thread that mentions IRQ accounting
recently[1], I wonder if the underlying bug here might have something
do to
irqchip/bcm7120-l2: Set controller as wake-up source
irqchip/brcmstb-l2: Set controller as wake-up source
Kamal Dasu (1):
irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatible
Linus Walleij (2):
irqchip/vic: Drop cascaded intialization call
irqchip/vic: Cut down the external
On 2020-08-03 07:22, Mark-PK Tsai wrote:
Add mt58xx interrupt controller support using hierarchy irq
domain.
Signed-off-by: Mark-PK Tsai
---
drivers/irqchip/Kconfig | 7 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-mt58xx.c | 196 +++
3 fi
On 2020-07-31 09:08, Marc Zyngier wrote:
Hi Valentin,
On 2020-07-31 01:08, Valentin Schneider wrote:
Hi Marc,
On 30/07/20 19:10, Marc Zyngier wrote:
[...]
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index e2b4cae88bce..a91ce1e73bd2 100644
--- a/drivers/irqchip/irq
Hi Valentin,
On 2020-07-31 01:08, Valentin Schneider wrote:
Hi Marc,
On 30/07/20 19:10, Marc Zyngier wrote:
[...]
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index e2b4cae88bce..a91ce1e73bd2 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
Hi Valentin,
On 2020-07-30 18:03, Valentin Schneider wrote:
The GIC irqchips can now use a HW resend when a retrigger is invoked by
check_irq_resend(). However, should the HW resend fail,
check_irq_resend()
will still attempt to trigger a SW resend, which is still a bad idea
for
the GICs.
Pr
On Thu, 30 Jul 2020 11:44:41 +0200, Alexander Graf wrote:
> Commit c726200dd106d ("KVM: arm/arm64: Allow reporting non-ISV data aborts
> to userspace") introduced a mechanism to deflect MMIO traffic the kernel
> can not handle to user space. For that, it introduced a new exit reason.
>
> However,
On Thu, 30 Jul 2020 14:25:19 +0100, David Brazdil wrote:
> Some compilers may put a subset of generated functions into '.text.*'
> ELF sections and the linker may leverage this division to optimize ELF
> layout. Unfortunately, the recently introduced HYPCOPY command assumes
> that all executable co
On Wed, 29 Jul 2020 23:58:49 +0800, Wei Yongjun wrote:
> Gcc report warning as follows:
>
> drivers/irqchip/irq-imx-intmux.c:316:29: warning:
> variable 'irqchip_data' set but not used [-Wunused-but-set-variable]
> 316 | struct intmux_irqchip_data irqchip_data;
> |
h this one first then apply Linus' one on top of it to be long
term proof, and backport only the first one. Linus ?
So for what it's worth, this patch fixes the arm64 compilation problem
for me:
Tested-by: Marc Zyngier
I had come up with a different fix, only tou
On 2020-07-29 16:58, Wei Yongjun wrote:
Gcc report warning as follows:
drivers/irqchip/irq-imx-intmux.c:316:29: warning:
variable 'irqchip_data' set but not used [-Wunused-but-set-variable]
316 | struct intmux_irqchip_data irqchip_data;
| ^~~~
irqda
On 2020-07-28 10:18, Grzegorz Jaszczyk wrote:
From: Suman Anna
The PRUSS INTC has a fixed number of output interrupt lines that are
connected to a number of processors or other PRUSS instances or other
devices (like DMA) on the SoC. The output interrupt lines 2 through 9
are usually connected t
On Tue, 21 Jul 2020 10:44:43 +0100, David Brazdil wrote:
> There is currently no way to disable nVHE ASLR, e.g. for debugging, so the
> first patch in this series makes it conditional on RANDOMIZE_BASE, same as
> KASLR. Note that the 'nokaslr' command line flag has no effect here.
>
> Second patch
On 2020-07-17 10:21, Keqian Zhu wrote:
ARM virtual counter supports event stream. It can only trigger an event
when the trigger bit of CNTVCT_EL0 changes from 0 to 1 (or from 1 to
0),
so the actual period of event stream is 2 ^ (cntkctl_evnti + 1). For
example, when the trigger bit is 0, then i
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