The following commit has been merged into the irq/core branch of tip:
Commit-ID: 5ebf353af22c89d18964bb3b877a95200dfe07b9
Gitweb:
https://git.kernel.org/tip/5ebf353af22c89d18964bb3b877a95200dfe07b9
Author:Marc Zyngier
AuthorDate:Tue, 23 Jun 2020 21:15:00 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: c3330399931be38ce459e82bf7dea140338ae43f
Gitweb:
https://git.kernel.org/tip/c3330399931be38ce459e82bf7dea140338ae43f
Author:Marc Zyngier
AuthorDate:Mon, 14 Sep 2020 17:21:16 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 56afcd3dbd1995c526bfbd920cebde6158b22c4a
Gitweb:
https://git.kernel.org/tip/56afcd3dbd1995c526bfbd920cebde6158b22c4a
Author:Marc Zyngier
AuthorDate:Tue, 23 Jun 2020 20:38:41 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 70a29c32cf7909e96a469ae71d88b2c0fbcbd767
Gitweb:
https://git.kernel.org/tip/70a29c32cf7909e96a469ae71d88b2c0fbcbd767
Author:Marc Zyngier
AuthorDate:Sat, 25 Apr 2020 15:11:20 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: c5e5ec033c4ab25c53f1fd217849e75deb0bf7bf
Gitweb:
https://git.kernel.org/tip/c5e5ec033c4ab25c53f1fd217849e75deb0bf7bf
Author:Marc Zyngier
AuthorDate:Tue, 19 May 2020 10:41:00 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 83cfac95c01817819c2a51f0931d798d851f8a08
Gitweb:
https://git.kernel.org/tip/83cfac95c01817819c2a51f0931d798d851f8a08
Author:Marc Zyngier
AuthorDate:Tue, 19 May 2020 14:58:13 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: d3afc7f12987581eb0d1215b518d719fb9d762da
Gitweb:
https://git.kernel.org/tip/d3afc7f12987581eb0d1215b518d719fb9d762da
Author:Marc Zyngier
AuthorDate:Sat, 25 Apr 2020 15:03:47 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: f02147dd02eb5fab31b55b73e7524f94b5f20324
Gitweb:
https://git.kernel.org/tip/f02147dd02eb5fab31b55b73e7524f94b5f20324
Author:Marc Zyngier
AuthorDate:Mon, 22 Jun 2020 21:23:36 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: cd1752d34ef33d68d82ef9dcc699b4eaa17c07fc
Gitweb:
https://git.kernel.org/tip/cd1752d34ef33d68d82ef9dcc699b4eaa17c07fc
Author:Marc Zyngier
AuthorDate:Wed, 26 Aug 2020 18:37:50 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 220387048d859896ccc362c0ebf9bc1e0fa62eb9
Gitweb:
https://git.kernel.org/tip/220387048d859896ccc362c0ebf9bc1e0fa62eb9
Author:Marc Zyngier
AuthorDate:Fri, 25 Sep 2020 16:22:00 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 64a267e9a41c5a91efdfa5bf55bd2509cb4f7170
Gitweb:
https://git.kernel.org/tip/64a267e9a41c5a91efdfa5bf55bd2509cb4f7170
Author:Marc Zyngier
AuthorDate:Sat, 25 Apr 2020 15:24:01 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 7ec46b519467852fc8eb83b6214ad568f8007846
Gitweb:
https://git.kernel.org/tip/7ec46b519467852fc8eb83b6214ad568f8007846
Author:Marc Zyngier
AuthorDate:Sat, 25 Apr 2020 15:24:01 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 5f774f5e12512b850a611aa99b4601d7eac50edb
Gitweb:
https://git.kernel.org/tip/5f774f5e12512b850a611aa99b4601d7eac50edb
Author:Marc Zyngier
AuthorDate:Fri, 31 Jul 2020 11:33:13 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 3567c6ca47546106d36d995790e4eb80e3f14632
Gitweb:
https://git.kernel.org/tip/3567c6ca47546106d36d995790e4eb80e3f14632
Author:Marc Zyngier
AuthorDate:Tue, 19 May 2020 09:42:46 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: a263881525310e10ecd46ae8e8531ac9e968b1b4
Gitweb:
https://git.kernel.org/tip/a263881525310e10ecd46ae8e8531ac9e968b1b4
Author:Marc Zyngier
AuthorDate:Sat, 20 Jun 2020 17:19:00 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: a2df12c5899e9bb181cb64385b04f2bc755780b6
Gitweb:
https://git.kernel.org/tip/a2df12c5899e9bb181cb64385b04f2bc755780b6
Author:Marc Zyngier
AuthorDate:Sat, 20 Jun 2020 20:02:18 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 8681cc33f817842df7ebe3c36558d97f5497a177
Gitweb:
https://git.kernel.org/tip/8681cc33f817842df7ebe3c36558d97f5497a177
Author:Marc Zyngier
AuthorDate:Sun, 04 Oct 2020 21:16:24 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: c351ab7bf2a565951172cadbdebe686137c3fd43
Gitweb:
https://git.kernel.org/tip/c351ab7bf2a565951172cadbdebe686137c3fd43
Author:Marc Zyngier
AuthorDate:Sun, 04 Oct 2020 18:27:04 +01:00
Committer
-htvec: Fix initial interrupt clearing
Krzysztof Kozlowski (1):
irqchip/ti-sci: Simplify with dev_err_probe()
Lad Prabhakar (1):
irqchip: Kconfig: Update description for RENESAS_IRQC config
Marc Zyngier (36):
genirq: Walk the irq_data hierarchy when resending an interrupt
On Sat, 10 Oct 2020 02:58:55 +0100,
Masayoshi Mizuma wrote:
[...]
> > +void ipi_nmi_setup(int cpu)
> > +{
> > + if (!ipi_desc)
> > + return;
>
> ipi_nmi_setup() may be called twice for CPU0:
>
> set_smp_ipi_range => set_smp_ipi_nmi => ipi_nmi_setup
> =>
On Thu, 08 Oct 2020 21:47:29 +0100,
Thomas Gleixner wrote:
>
> On Thu, Oct 08 2020 at 14:06, Marc Zyngier wrote:
> > On 2020-10-08 12:22, Thomas Gleixner wrote:
> > Here's what I have now, with the pmc driver calling
> > irq_domain_disconnect_hierarchy() at the right spo
On 2020-10-08 12:22, Thomas Gleixner wrote:
On Wed, Oct 07 2020 at 13:45, Marc Zyngier wrote:
+/**
+ * irq_domain_trim_hierarchy - Trim the uninitialized part of a irq
hierarchy
+ * @virq: IRQ number to trim where the hierarchy is to be trimmed
+ *
+ * Drop the partial irq_data hierarchy
On 2020-10-07 15:03, Andy Shevchenko wrote:
On Wed, Oct 7, 2020 at 4:20 PM Marc Zyngier wrote:
On 2020-10-07 14:10, Andy Shevchenko wrote:
> On Wed, Oct 7, 2020 at 3:09 PM Marc Zyngier wrote:
>> On 2020-10-07 13:02, Andy Shevchenko wrote:
>> > On Wed, Oct 7, 2020 at 12:4
On 2020-10-07 14:10, Andy Shevchenko wrote:
On Wed, Oct 7, 2020 at 3:09 PM Marc Zyngier wrote:
On 2020-10-07 13:02, Andy Shevchenko wrote:
> On Wed, Oct 7, 2020 at 12:49 PM Linus Walleij
> wrote:
>> On Mon, Oct 5, 2020 at 4:02 PM Marc Zyngier wrote:
>>
>> > The
Make the tegra186 GPIO driver resistent to variable depth
interrupt hierarchy, which we are about to introduce.
No functionnal change yet.
Signed-off-by: Marc Zyngier
---
drivers/gpio/gpio-tegra186.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers
Make the PMC driver resistent to variable depth interrupt hierarchy,
which we are about to introduce.
Signed-off-by: Marc Zyngier
---
drivers/soc/tegra/pmc.c | 36
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c b
irqchip patch to the bare minimal in order to
reduce the risk of merge conflicts
[1] https://lore.kernel.org/r/20201005111443.1390096-1-...@kernel.org
[2] https://lore.kernel.org/r/20201006101137.1393797-1-...@kernel.org
Marc Zyngier (4):
genirq/irqdomain: Allow partial trimming of irq_data
irst level that doesn't have a corresponding irqchip.
As this is never a valid option (we have the no_irq_chip chip
for the "do nothing" case), the hierarchy can be trimmed from
that level.
Signed-off-by: Marc Zyngier
---
kernel/irq/irqdomain.c | 58 +-
code remove them from the hierarchy.
Signed-off-by: Marc Zyngier
---
drivers/soc/tegra/pmc.c | 50 -
1 file changed, 50 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index b39536c68f45..2395c84ef83a 100644
--- a/drivers/soc
On 2020-10-07 09:53, Marc Zyngier wrote:
On 2020-10-07 09:05, Marc Zyngier wrote:
On 2020-10-06 21:39, Thomas Gleixner wrote:
[...]
This is butt ugly, really. Especially the use case where the tegra
PMC
domain removes itself from the hierarchy from .alloc()
I don't disagree at all
On 2020-10-07 13:02, Andy Shevchenko wrote:
On Wed, Oct 7, 2020 at 12:49 PM Linus Walleij
wrote:
On Mon, Oct 5, 2020 at 4:02 PM Marc Zyngier wrote:
> The pca953x driver never checks the result of irq_find_mapping(),
> which returns 0 when no mapping is found. When a spurious int
On 2020-10-07 09:05, Marc Zyngier wrote:
On 2020-10-06 21:39, Thomas Gleixner wrote:
On Tue, Oct 06 2020 at 11:11, Marc Zyngier wrote:
It appears that some HW is ugly enough that not all the interrupts
connected to a particular interrupt controller end up with the same
hierarchy repth (some
On 2020-10-06 21:39, Thomas Gleixner wrote:
On Tue, Oct 06 2020 at 11:11, Marc Zyngier wrote:
It appears that some HW is ugly enough that not all the interrupts
connected to a particular interrupt controller end up with the same
hierarchy repth (some of them are terminated early). This leaves
Hi Alex,
On Tue, 06 Oct 2020 16:05:20 +0100,
Alexandru Elisei wrote:
>
> From ARM DDI 0487F.b, page D9-2807:
>
> "Although the Statistical Profiling Extension acts as another observer in
> the system, for determining the Shareability domain of the DSB
> instructions, the writes of sample
On Mon, 28 Sep 2020 10:01:58 +0530, Maulik Shah wrote:
> Changes in v6:
> - Update commit message more descriptive in v5 patch 1
> - Symmetrically enable/disable wakeirqs during suspend/resume in v5 patch 3
> - Include Acked-by and Reviewed-by tags from v5 series
>
> Changes in v5:
> - Update
Make the tegra186 GPIO driver resistent to variable depth
interrupt hierarchy, which we are about to introduce.
No functionnal change yet.
Signed-off-by: Marc Zyngier
---
drivers/gpio/gpio-tegra186.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers
/irqchip-next.
* From v1:
- Moved the hierarchy trimming part to its own patch, living in
irqdomain.c
- Reduced the PMC irqchip patch to the bare minimal in order to
reduce the risk of merge conflicts
[1] https://lore.kernel.org/r/20201005111443.1390096-1-...@kernel.org
Marc Zyngier (4
deeper. This avoids having unnecessary
callbacks, overriding mappings, and otherwise keeps the hierarchy sane.
Signed-off-by: Marc Zyngier
---
drivers/soc/tegra/pmc.c | 53 -
1 file changed, 4 insertions(+), 49 deletions(-)
diff --git a/drivers/soc/tegra
y, exactly representing the HW. This can only be done from
the .alloc() callback, before mappings can be established.
Signed-off-by: Marc Zyngier
---
include/linux/irqdomain.h | 3 +++
kernel/irq/irqdomain.c| 56 +++
2 files changed, 54 insertions(+), 5
Make the PMC driver resistent to variable depth interrupt hierarchy,
which we are about to introduce.
Signed-off-by: Marc Zyngier
---
drivers/soc/tegra/pmc.c | 36
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c b
this particular case and warn on spurious interrupts.
Signed-off-by: Marc Zyngier
---
drivers/gpio/gpio-pca953x.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index fb61f2fc6ed7..c2d6121c48c9 100644
, but instead the external ones
provided by the GIC. KVM's virtual GIC now works with this change.
Signed-off-by: Marc Zyngier
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts
On 2020-10-05 12:33, Thierry Reding wrote:
On Mon, Oct 05, 2020 at 12:14:43PM +0100, Marc Zyngier wrote:
The Tegra PMC driver does ungodly things with the interrupt hierarchy,
repeatedly corrupting it by pulling hwirq numbers out of thin air,
overriding existing IRQ mappings and changing
On 2020-10-05 12:22, Thierry Reding wrote:
On Mon, Oct 05, 2020 at 12:14:40PM +0100, Marc Zyngier wrote:
Jon recently reported that one of the Tegra systems (Jetson TX2, aka
tegra186) stopped booting with the introduction of the "IPI as IRQs"
series. After a few weeks of head
On 2020-10-05 12:27, Thierry Reding wrote:
On Mon, Oct 05, 2020 at 12:14:42PM +0100, Marc Zyngier wrote:
Make the PMC driver resistent to variable depth interrupt hierarchy,
which we are about to introduce. The irq_chip structure is now
allocated statically, providing the indirection
Make the tegra186 GPIO driver resistent to variable depth
interrupt hierarchy, which we are about to introduce.
No functionnal change yet.
Signed-off-by: Marc Zyngier
---
drivers/gpio/gpio-tegra186.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers
Make the PMC driver resistent to variable depth interrupt hierarchy,
which we are about to introduce. The irq_chip structure is now
allocated statically, providing the indirection for the couple of
callbacks that are SoC-specific.
Signed-off-by: Marc Zyngier
---
drivers/soc/tegra/pmc.c | 65
, and not any deeper. This avoids
having unnecessary callbacks, overriding mappings, and otherwise
keeps the hierarchy sane.
Signed-off-by: Marc Zyngier
---
drivers/soc/tegra/pmc.c | 79 +++--
1 file changed, 29 insertions(+), 50 deletions(-)
diff --git
, tegra186 is back booting on -next.
I haven't tested any wake-up stuff, nor any other nvidia system (this
is the only one I have). If people agree to these changes, I can take
them via the irqchip tree so that they make it into the next merge
window.
M.
Marc Zyngier (3):
gpio: tegra186:
On Wed, 30 Sep 2020 14:18:01 +0100, Will Deacon wrote:
> Alex pointed out that we don't pass a level hint to the TLBI instruction
> when handling a stage-2 permission fault, even though the walker does
> at some point have the level information in its hands.
>
> Rework stage2_update_leaf_attrs()
On Wed, 30 Sep 2020 11:24:42 +0100, Will Deacon wrote:
> If a change in the MMU notifier sequence number forces user_mem_abort()
> to return early when attempting to handle a stage-2 fault, we return
> uninitialised stack to kvm_handle_guest_abort(), which could potentially
> result in the
On Fri, 2 Oct 2020 07:49:44 +0200, Mauro Carvalho Chehab wrote:
> There are some new warnings when building the documentation from
> yesterday's linux next. This small series fix them.
>
> - patch 1 documents two new kernel-doc parameters on a net core file.
> I used the commit log in order to
On Tue, 22 Sep 2020 21:49:00 +0100, David Brazdil wrote:
> Introduce '.hyp.data..percpu' as part of ongoing effort to make nVHE
> hyp code self-contained and independent of the rest of the kernel.
>
> Main benefits:
> * independent nVHE per-CPU data section that can be unmapped from host,
> *
Hi Niklas,
[+ Samuel]
On 2020-09-30 17:27, Niklas Söderlund wrote:
Hi Marc,
I'm afraid this commit breaks booting my rk3399 device.
I bisected the problem to this patch merged as [1]. I'm testing on a
Scarlet device and I'm using the unmodified upstream
rk3399-gru-scarlet-inx.dtb for my
On 2020-09-30 11:01, Peter Ujfalusi wrote:
On 30/09/2020 11.33, Marc Zyngier wrote:
On 2020-09-30 08:45, Peter Ujfalusi wrote:
The DMA (BCDMA/PKTDMA and their rings/flows) events are under the
INTA's
supervision as unmapped events in AM64.
What does "unmapped event" mean
On 2020-09-30 08:45, Peter Ujfalusi wrote:
The DMA (BCDMA/PKTDMA and their rings/flows) events are under the
INTA's
supervision as unmapped events in AM64.
What does "unmapped event" mean? An event that doesn't require a
mapping?
Or an internally generated event? Or a proxy event?
In
On 2020-09-29 19:02, Jon Hunter wrote:
On 29/09/2020 18:25, Marc Zyngier wrote:
On 2020-09-29 14:22, Jon Hunter wrote:
Hi Jisheng,
On 29/09/2020 11:48, Jisheng Zhang wrote:
Hi Jon,
On Fri, 25 Sep 2020 09:53:45 +0100 Jon Hunter wrote:
On 24/09/2020 12:05, Jisheng Zhang wrote:
Improve
On 2020-09-29 18:34, Will Deacon wrote:
On Tue, Sep 22, 2020 at 09:49:05PM +0100, David Brazdil wrote:
The hyp_adr/ldr_this_cpu helpers were introduced for use in hyp code
because they always needed to use TPIDR_EL2 for base, while
adr/ldr_this_cpu from kernel proper would select between
On 2020-09-24 12:06, Jisheng Zhang wrote:
We need to check alloc_page() succeed or not before continuing.
Signed-off-by: Jisheng Zhang
---
drivers/pci/controller/dwc/pcie-designware-host.c | 5 +
1 file changed, 5 insertions(+)
diff --git
On 2020-09-29 14:22, Jon Hunter wrote:
Hi Jisheng,
On 29/09/2020 11:48, Jisheng Zhang wrote:
Hi Jon,
On Fri, 25 Sep 2020 09:53:45 +0100 Jon Hunter wrote:
On 24/09/2020 12:05, Jisheng Zhang wrote:
Improve the msi code:
1. Add proper error handling.
2. Move dw_pcie_msi_init() from each
Hi,
[dropping these ARM people I never heard of...]
On 2020-09-29 12:32, Borislav Petkov wrote:
Hi,
how about we add RIP to decodecode output? See below.
I've added the couple of people to Cc who seem to use this thing. The
patch is dirty and needs cleaning still but I think it would be cool
On 2020-09-29 06:50, ito-yui...@fujitsu.com wrote:
Hi Marc
[...]
>> The patch has been tested on ThunderX.
Which ThunderX? TX2 (at least the incarnation I used in the past)
wasn't able
to correctly deal with priorities.
I tried it with ThunderX CN8890.
If you tell me steps to reproduce
for a non-existent vcpu by calling irq_work_sync()
on
the PMU destroy path.
Cc: Julien Thierry
Cc: Marc Zyngier
Cc: Will Deacon
Cc: Mark Rutland
Cc: Catalin Marinas
Cc: James Morse
Cc: Suzuki K Pouloze
Cc: k...@vger.kernel.org
Cc: kvm...@lists.cs.columbia.edu
Signed-off-by: Julien Thierry
On 2020-09-28 03:43, ito-yui...@fujitsu.com wrote:
Hi Marc, Sumit
I would appreciate if you have any advice on this patch.
I haven't had a chance to look into it, as I'm not even sure I'll
take the core series in the first place (there are outstanding
regressions I can't reproduce, let alone
Hi Sean,
On Wed, 23 Sep 2020 23:45:27 +0100,
Sean Christopherson wrote:
>
> This series introduces a concept we've discussed a few times in x86 land.
> The crux of the problem is that x86 has a few cases where KVM could
> theoretically encounter a software or hardware bug deep in a call stack
>
On Mon, 14 Sep 2020 23:27:16 +0300, Cristian Ciocaltea wrote:
> This patch series adds support for the external interrupt controller
> (SIRQ) found in the Actions Semi Owl family of SoC's (S500, S700 and
> S900). The controller handles up to 3 external interrupt lines through
> dedicated SIRQ
ell the yaml keep the "newline" character.
>2) add "..." to mark the end of the yaml file.
>3) Change the name list of maintainers to the author of
> "snps,dw-apb-ictl.txt"
>maintainers:
> - - Marc Zyngier
> + -
Hi Guillaume,
On Thu, 24 Sep 2020 10:00:09 +0100,
Guillaume Tucker wrote:
>
> Hi Marc,
>
> On 01/09/2020 15:43, Marc Zyngier wrote:
> > Let's switch the arm code to the core accounting, which already
> > does everything we need.
> >
> > Reviewed-by: Valenti
On 2020-09-18 16:41, Will Deacon wrote:
On Sat, Sep 19, 2020 at 12:35:48AM +0900, Sergey Senozhatsky wrote:
ipi_teardown() is used only when CONFIG_HOTPLUG_CPU is set.
Signed-off-by: Sergey Senozhatsky
---
arch/arm64/kernel/smp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
I
On Fri, 18 Sep 2020 20:33:18 +0800, YueHaibing wrote:
> If CONFIG_HOTPLUG_CPU is n, gcc warns:
>
> arch/arm64/kernel/smp.c:967:13: warning: ‘ipi_teardown’ defined but not used
> [-Wunused-function]
> static void ipi_teardown(int cpu)
> ^~~~
>
> Use #ifdef guard this.
On Wed, 16 Sep 2020 10:50:23 +0800, Liu Shixin wrote:
> Use DEFINE_SEQ_ATTRIBUTE macro to simplify the code.
Applied to next, thanks!
[1/1] KVM: arm64: vgic-debug: Convert to use DEFINE_SEQ_ATTRIBUTE macro
commit: cb62e0b5c8db778cd29e63c2f844f36caf6859ed
Cheers,
M.
--
Without
On Thu, 17 Sep 2020 09:47:49 +0800, Xiaofei Tan wrote:
> Fix following warnings caused by mismatch bewteen function parameters
> and comments.
> arch/arm64/kvm/mmu.c:128: warning: Function parameter or member 'mmu' not
> described in '__unmap_stage2_range'
> arch/arm64/kvm/mmu.c:128: warning:
On 2020-09-18 11:35, Sergey Senozhatsky wrote:
On (20/09/18 09:20), Marc Zyngier wrote:
On 2020-09-18 01:32, Sergey Senozhatsky wrote:
> On (20/09/17 12:53), Marc Zyngier wrote:
> > Feel free to add a *new* tracepoint instead.
>
> Wouldn't we want a whole bunch of new tracepoin
Hi James,
On Fri, 18 Sep 2020 10:58:45 +0100,
James Morse wrote:
>
> Hi Marc,
>
> (CC: +Jon)
>
> On 01/09/2020 15:43, Marc Zyngier wrote:
> > Change the way we deal with GIC SGIs by turning them into proper
> > IRQs, and calling into the arch code to register t
On 2020-09-17 19:24, Jon Hunter wrote:
On 17/09/2020 15:53, Jon Hunter wrote:
...
next-20200916 completely broken on ARM and ARM64. Please check
next-20200915 + the mentioned fix or just check
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/ipi-as-irq
OK, I
On 2020-09-18 01:32, Sergey Senozhatsky wrote:
On (20/09/17 12:53), Marc Zyngier wrote:
Feel free to add a *new* tracepoint instead.
Wouldn't we want a whole bunch of new tracepoints in this case?
Yes. I don't have a better solution as long as tracepoints are ABI.
Get someone to sign-off
On 2020-09-17 12:42, Leo Yan wrote:
On Thu, Sep 17, 2020 at 11:21:15AM +0100, Marc Zyngier wrote:
[...]
> > > +const char *vcpu_id_str = "id";
> >
> > On Arm64, ftrace tracepoint "kvm_entry" doesn't contain the field "id"
> > o
On 2020-09-17 12:10, Stephen Rothwell wrote:
Hi all,
Commits
e86085c6e2fb ("irqchip/irq-pruss-intc: Add support for ICSSG INTC on
K3 SoCs")
1c46bcaed207 ("irqchip/irq-pruss-intc: Implement irq_{get,
set}_irqchip_state ops")
7d1ca43a7c14 ("irqchip/irq-pruss-intc: Add logic for handling
On 2020-09-16 17:35, Grzegorz Jaszczyk wrote:
Hi All,
The following is a v7 version of the series [1-6] that adds an IRQChip
driver for the local interrupt controller present within a Programmable
Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
present on a
number of TI SoCs
On 2020-09-17 11:12, Leo Yan wrote:
Add Marc at this time, sorry for spamming.
On Thu, Sep 17, 2020 at 06:09:50PM +0800, Leo Yan wrote:
[ + Marc ]
On Thu, Sep 17, 2020 at 09:36:45AM +0900, Sergey Senozhatsky wrote:
[...]
> diff --git a/tools/perf/arch/arm64/util/kvm-stat.c
On 2020-09-17 04:46, Leizhen (ThunderTown) wrote:
On 2020/9/15 16:43, Zhen Lei wrote:
To avoid compilation error if an irqchip driver references the
function
set_handle_irq() but may not select GENERIC_IRQ_MULTI_HANDLER on some
systems.
Hi, Marc:
Do you agree with this method?
On 2020-09-17 10:13, Marek Szyprowski wrote:
[...]
Linus, what -next are you testing on? I am using next-20200916.
next-20200916 completely broken on ARM and ARM64. Please check
next-20200915 + the mentioned fix or just check
On 2020-09-17 09:49, Jon Hunter wrote:
On 17/09/2020 09:45, Marc Zyngier wrote:
On 2020-09-17 08:54, Jon Hunter wrote:
So far, I have only tested this patch on Tegra20. Let me try the
other
failing boards this morning and see if those still fail.
Tegra20 (if I remember well) is a dual A9
On 2020-09-17 08:54, Jon Hunter wrote:
On 17/09/2020 08:50, Marc Zyngier wrote:
Hi Linus,
On 2020-09-17 08:40, Linus Walleij wrote:
On Wed, Sep 16, 2020 at 5:11 PM Marc Zyngier wrote:
Can you try the patch below and let me know?
I tried this patch and now Ux500 WORKS. So this patch
Hi Linus,
On 2020-09-17 08:40, Linus Walleij wrote:
On Wed, Sep 16, 2020 at 5:11 PM Marc Zyngier wrote:
Can you try the patch below and let me know?
I tried this patch and now Ux500 WORKS. So this patch is definitely
something you should apply.
- if (is_frankengic
Hi Linus,
On 2020-09-16 15:03, Linus Walleij wrote:
On Tue, Sep 1, 2020 at 4:44 PM Marc Zyngier wrote:
Change the way we deal with GIC SGIs by turning them into proper
IRQs, and calling into the arch code to register the interrupt range
instead of a callback.
Reviewed-by: Valentin Schneider
On 2020-09-16 17:22, Marc Zyngier wrote:
On 2020-09-16 16:58, Jon Hunter wrote:
On 16/09/2020 16:55, Marc Zyngier wrote:
On 2020-09-16 16:46, Jon Hunter wrote:
On 16/09/2020 16:10, Marc Zyngier wrote:
Hi Jon,
+Linus, who is facing a similar issue.
On 2020-09-16 15:16, Jon Hunter wrote:
Hi
On 2020-09-16 16:58, Jon Hunter wrote:
On 16/09/2020 16:55, Marc Zyngier wrote:
On 2020-09-16 16:46, Jon Hunter wrote:
On 16/09/2020 16:10, Marc Zyngier wrote:
Hi Jon,
+Linus, who is facing a similar issue.
On 2020-09-16 15:16, Jon Hunter wrote:
Hi Marc,
On 14/09/2020 14:06, Marek
Hi Jon,
+Linus, who is facing a similar issue.
On 2020-09-16 15:16, Jon Hunter wrote:
Hi Marc,
On 14/09/2020 14:06, Marek Szyprowski wrote:
Hi Marc,
On 01.09.2020 16:43, Marc Zyngier wrote:
Change the way we deal with GIC SGIs by turning them into proper
IRQs, and calling into the arch
On 2020-09-16 16:46, Jon Hunter wrote:
On 16/09/2020 16:10, Marc Zyngier wrote:
Hi Jon,
+Linus, who is facing a similar issue.
On 2020-09-16 15:16, Jon Hunter wrote:
Hi Marc,
On 14/09/2020 14:06, Marek Szyprowski wrote:
Hi Marc,
On 01.09.2020 16:43, Marc Zyngier wrote:
Change the way we
On 2020-09-15 22:13, Rob Herring wrote:
On Sat, Sep 12, 2020 at 01:51:42PM +0100, Marc Zyngier wrote:
A recent attempt at converting a couple of interrupt controllers from
early probing to standard platform drivers have badly failed, as it
became evident that although an interrupt controller
On 2020-09-16 08:04, lushenming wrote:
Hi,
Our team just discussed this issue again and consulted our GIC hardware
design team. They think the RD can afford busy waiting. So we still
think
maybe 0 is better, at least for our hardware.
In addition, if not 0, as I said before, in our
Now that we have a static key identifying Samsung's unique creation,
let's replace the indirect call to compute the base addresses by
a simple test on the static key.
Faster, cheaper, negative diffstat.
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic.c | 48
these another spin on your boards? For
convenience, I've stashed them as part of [1].
Thanks,
M.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/ipi-as-irq
Marc Zyngier (2):
irqchip/gic: Handle non-standard SGI deactivation on Samsung's
Franken-GIC
: ac063232d4b0 ("irqchip/gic: Configure SGIs as standard interrupts")
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic.c | 49 +--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-g
Hi Xiaofei,
On 2020-09-15 14:18, Xiaofei Tan wrote:
Fix following warnings caused by mismatch bewteen function parameters
and comments.
arch/arm64/kvm/mmu.c:119: warning: Function parameter or member
'pudp'not described in 'stage2_dissolve_pud'
arch/arm64/kvm/mmu.c:119: warning: Excess function
On 2020-09-15 15:04, lushenming wrote:
Thanks for your quick response.
Okay, I agree that busy-waiting may add more overhead at the RD level.
But I think that the delay time can be adjusted. In our latest
hardware implementation, we optimize the search of the VPT, now even
the VPT full of
-by: tag.
---
v5->v6:
1) Address Marc Zyngier comments:
- Use unsigned types for variables used to compute masks/shifts (ch,
evt, host).
- Move part responsible for enabling global interrupt from
pruss_intc_map to pruss_intc_init.
- Improve coding style in pruss_intc_init with rega
On 2020-09-15 15:06, Marek Szyprowski wrote:
On 15.09.2020 15:39, Marc Zyngier wrote:
The GIC available on some of Samsung's A9-based platform is
thankfully one of a kind. On top of not presenting a banked
programing model (each CPU has its own base addresses for both
distributor and CPU
On 2020-09-15 09:35, Marek Szyprowski wrote:
Hi Marc,
On 15.09.2020 10:07, Marc Zyngier wrote:
On 2020-09-15 07:48, Marek Szyprowski wrote:
Both Exynos 4210 and 4412 use non-zero cpu-offset in GIC node in
device-tree: arch/arm/boot/dts/exynos{4210,4412}.dtsi, so I assume
that
the GIC
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