On Wed, Apr 7, 2021 at 6:27 AM Christian Hewitt
wrote:
>
> From: Hyeonki Hong
>
> Add GPIO line-name identifiers to the ODROID N2/N2+ common dtsi.
>
> Signed-off-by: Hyeonki Hong
> Signed-off-by: Christian Hewitt
> Reviewed-by: Neil Armstrong
Acked-by: Martin Blumenstingl
On Wed, Apr 7, 2021 at 6:27 AM Christian Hewitt
wrote:
>
> From: Hyeonki Hong
>
> Add the meson saradc node to the ODROID N2/N2+ common dtsi.
>
> Signed-off-by: Hyeonki Hong
> Signed-off-by: Christian Hewitt
Reviewed-by: Martin Blumenstingl
On Tue, Apr 13, 2021 at 1:45 AM Andrew Lunn wrote:
[...]
> > > and a few people have forked it and modified it for other DSA
> > > switches. At some point we might want to try to merge the forks back
> > > together so we have one tool to dump any switch.
> > actually I was wondering if there is
Hi Andrew,
On Mon, Apr 12, 2021 at 1:16 AM Andrew Lunn wrote:
>
> On Sun, Apr 11, 2021 at 10:55:11PM +0200, Martin Blumenstingl wrote:
> > Add support for .get_regs_len and .get_regs so it is easier to find out
> > about the state of the ports on the GSWIP hardware. For this w
of the auto polling mechanism). Other global and per-port
registers which are also considered useful are included as well.
Acked-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 83 ++
1 file changed, 83 insertions(+)
diff --git
Hi Sasha,
On Sun, Apr 11, 2021 at 6:48 PM Sasha Levin wrote:
>
> On Sun, Apr 11, 2021 at 12:23:42PM +0200, Martin Blumenstingl wrote:
> >Hello,
> >
> >This backports two patches (which could not be backported automatically
> >because the gswip_phylink_mac_link_up
by: Martin Blumenstingl
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller
Signed-off-by: Greg Kroah-Hartman
[ Updated after the upstream commit 3e9005be8 required some changes
for Linux 5.4 ]
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 19 -
_gswip: Let GSWIP automatically set the
xMII clock")
Cc: sta...@vger.kernel.org
Acked-by: Hauke Mehrtens
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller
Signed-off-by: Greg Kroah-Hartman
[ Move gswip_po
!
Martin
Martin Blumenstingl (2):
net: dsa: lantiq_gswip: Don't use PHY auto polling
net: dsa: lantiq_gswip: Configure all remaining GSWIP_MII_CFG bits
drivers/net/dsa/lantiq_gswip.c | 203 -
1 file changed, 175 insertions(+), 28 deletions(-)
--
2.31.1
On Fri, Apr 9, 2021 at 7:00 PM Mitali Borkar wrote:
>
> Looks good, will try this.
if you re-send this patch then please include our mailing list:
linux-amlo...@lists.infradead.org
Thank you!
Martin
Hello Vladimir,
On Fri, Apr 9, 2021 at 12:46 AM Vladimir Oltean wrote:
>
> On Thu, Apr 08, 2021 at 08:38:27PM +0200, Martin Blumenstingl wrote:
> > PHY auto polling on the GSWIP hardware can be used so link changes
> > (speed, link up/down, etc.) can be detected automat
Hi Lorenzo,
On Tue, Mar 23, 2021 at 12:36 PM Lorenzo Pieralisi
wrote:
>
> On Wed, Jan 06, 2021 at 02:55:40PM +0100, Martin Blumenstingl wrote:
> > The legacy PCI interrupt lines need to be enabled using PCIE_APP_IRNEN
> > bits 13 (INTA), 14 (INTB), 15 (INTC) and 16 (INTD). Th
to get a better overview of the GSWIP_MII_CFG register.
Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Cc: sta...@vger.kernel.org
Suggested-by: Hauke Mehrtens
Acked-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gs
: sta...@vger.kernel.org
Acked-by: Hauke Mehrtens
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 185 -
1 file changed, 159 insertions(+), 26 deletions(-)
diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/n
you!)
Best regards,
Martin
[0]
https://patchwork.kernel.org/project/netdevbpf/cover/20210406203508.476122-1-martin.blumensti...@googlemail.com/
Martin Blumenstingl (2):
net: dsa: lantiq_gswip: Don't use PHY auto polling
net: dsa: lantiq_gswip: Configure all remaining GSWIP_MII_CFG bi
On Wed, Apr 7, 2021 at 9:44 PM Andrew Lunn wrote:
>
> > For my own curiosity: is there a "recommended" way where to configure
> > link up/down, speed, duplex and flow control? currently I have the
> > logic in both, .phylink_mac_config and .phylink_mac_link_up.
>
> You probably want to read the
Hi Andrew,
On Wed, Apr 7, 2021 at 2:25 AM Andrew Lunn wrote:
[...]
> Having the MAC polling the PHY is pretty much always a bad idea.
>
> Reviewed-by: Andrew Lunn
thanks for reviewing this!
For my own curiosity: is there a "recommended" way where to configure
link up/down, speed, duplex and
Hello,
On Wed, Apr 7, 2021 at 6:47 PM Florian Fainelli wrote:
>
>
>
> On 4/6/2021 5:32 PM, Andrew Lunn wrote:
> >> case PHY_INTERFACE_MODE_RGMII:
> >> case PHY_INTERFACE_MODE_RGMII_ID:
> >> case PHY_INTERFACE_MODE_RGMII_RXID:
> >> case PHY_INTERFACE_MODE_RGMII_TXID:
> >>
;)
Cc: sta...@vger.kernel.org
Suggested-by: Hauke Mehrtens
Acked-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/lantiq_gswip.c b/drive
: sta...@vger.kernel.org
Acked-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 191 -
1 file changed, 165 insertions(+), 26 deletions(-)
diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c
[0]
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id=3e6fdeb28f4c331acbd27bdb0effc4befd4ef8e8
[1] https://github.com/openwrt/openwrt/pull/3085
Martin Blumenstingl (2):
net: dsa: lantiq_gswip: Don't use PHY auto polling
net: dsa: lantiq_gswip: Configure all remaining GSWIP_MI
On Tue, Mar 30, 2021 at 1:18 AM Christian Hewitt
wrote:
>
> From: Hyeonki Hong
>
> Add the meson saradc node to the ODROID N2/N2+ common dtsi.
in general I am fine with this as some SAR ADC channels seem to be on
the pin headers...
[...]
> + {
> + status = "okay";
> +};
...but a
On Tue, Mar 30, 2021 at 1:17 AM Christian Hewitt
wrote:
>
> Remove an extra tab from the ext_mdio node in the ODROID N2/N2+ common
> dtsi file.
>
> Signed-off-by: Christian Hewitt
Reviewed-by: Martin Blumenstingl
On Thu, Mar 25, 2021 at 4:25 PM Neil Armstrong wrote:
>
> The first UART controller in "Everything-Else" power domain, usually used
> for Bluetooth HCI has 128bytes FIFO depth.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
On Thu, Mar 25, 2021 at 4:25 PM Neil Armstrong wrote:
>
> Now the DT bindings has a property to get the FIFO size for a particular port,
> retrieve it and use to setup the FIFO interrupts threshold.
>
> Signed-off-by: Neil Armstrong
> Reviewed-by: Kevin Hilman
Reviewed-by: Martin Blumenstingl
Hi Florian,
On Thu, Mar 25, 2021 at 7:09 PM Florian Fainelli wrote:
[...]
> > It would be great to have this fix backported to Linux 5.4 and 5.10 to
> > get rid of one more blocker which prevents OpenWrt from switching to
> > this new in-tree driver.
>
> Given there is a Fixes: tag this should
(no RX or TX traffic could be seen). Most
likely this is due to an "invalid" xMII clock being selected either by
the bootloader or hardware-defaults.
Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Signed-off-by: Martin Blumenstingl
---
It wo
Hi Bjorn,
On Thu, Mar 18, 2021 at 3:55 AM Bjorn Andersson
wrote:
[...]
> > +examples:
> > + - |
> > +remoteproc@1c {
> > + compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
> > + reg = <0x1c 0x8>, <0x38 0x8>;
>
> I'm generally not in favor of mapping "individual"
Hi Bjorn,
On Thu, Mar 18, 2021 at 3:51 AM Bjorn Andersson
wrote:
>
> On Tue 29 Dec 19:27 CST 2020, Martin Blumenstingl wrote:
>
> > Amlogic Meson6, Meson8, Meson8b and Meson8m2 embed an ARC core in the
> > Always-On (AO) power-domain. This is typically used for waking up th
On Mon, Mar 15, 2021 at 9:37 AM Neil Armstrong wrote:
>
> Now the DT bindings has a property to get the FIFO size for a particular port,
> retrieve it and use to setup the FIFO interrupts threshold.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
pping of long lines in commit messages?
if so I think the line above is too long
> a different FIFO size from the other ports (64bytes).
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
one additional note below
> ---
> .../devicetree/bindings/serial/amlogic,meson-ua
..3000ps in 200ps steps on older SoCs which don't
support that).
Fixes: de94fc104d58ea ("net: stmmac: dwmac-meson8b: add support for the RGMII
RX delay on G12A")
Reported-by: Martijn van Deventer
Signed-off-by: Martin Blumenstingl
---
Many thanks to Martijn for this excel
Hi Mathieu,
thank you for taking the time to go through my patch!
On Wed, Jan 13, 2021 at 12:43 AM Mathieu Poirier
wrote:
[...]
> > + If unusre say N.
>
> s/unusre/unsure
godo catch, noted.
[...]
> > +#include
>
> Is it possible for this to go after platform_device.h?
I think so, not
(another late reply from me, sorry)
> +required:
> + - compatible
> + - reg
This is actually an older IP variant of what can be found in the Intel
LGM SoCs. The dt-bindings are currently being upstreamed for that newer
SoC in [0].
Based on "DOs and DON’Ts for designing and writing Devicetree
(again, sorry for seeing this patch late)
> +properties:
> + compatible:
> +items:
> + - enum:
> + - lantiq,ebu-xway
I think this compatible string is very generic and with that comes some
problems.
There is actually two different versions of this IP: one which has
support for
(sorry for only seeing this late)
[...]
> +maintainers:
> + - John Crispin
personally I think we should get at least John's Acked-by but I don't
know if there's any rule for adding a dt-binding for some other
maintainer
[...]
> +required:
> + - compatible
> + - reg
based on "DOs and DON’Ts
are
implemented:
- a dedicated driver for the EIU interrupt controller
- a driver for the MSI PIC (Programmable Interrupt Controller) found on
VRX200 and newer SoCs
- ..or any other driver which uses IRQCHIP_DECLARE
Signed-off-by: Martin Blumenstingl
---
arch/mips/lantiq/irq.c | 8 +++-
1
rors out.
>
> Add a short delay to let the phy get up and running. There isn't any
> documentation how much time is required, the value was chosen based on
> tests.
>
> Cc: # v5.7+
> Signed-off-by: Mathias Kresin
Acked-by: Martin Blumenstingl
Hi Linus,
On Tue, Jan 5, 2021 at 11:23 PM Linus Walleij wrote:
>
> On Mon, Dec 21, 2020 at 4:28 PM Martin Blumenstingl
> wrote:
> > On Wed, Oct 7, 2020 at 9:44 PM Martin Blumenstingl
> > wrote:
> > [...]
> > > > As noted on the earlie
ntel LGM
SoC")
Signed-off-by: Martin Blumenstingl
---
changes since v1:
- don't drop the check but actually move it after the mtd variable has
been initialized as suggested by Miquel Raynal
drivers/mtd/nand/raw/intel-nand-controller.c | 5 +++--
1 file changed, 3 insertions(+), 2 delet
d then use
these in PCIE_APP_IRN_INT.
Fixes: ed22aaaede44 ("PCI: dwc: intel: PCIe RC controller driver")
Signed-off-by: Martin Blumenstingl
---
drivers/pci/controller/dwc/pcie-intel-gw.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-i
configured but the phy-mode
incicates that the RX delay is not used.
Fixes: 9308c47640d515 ("net: stmmac: dwmac-meson8b: add support for the RX
delay configuration")
Reported-by: Andrew Lunn
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
d
nd 2ns. The new
SoCs have support for RGMII RX delays between 0ps and 3000ps in 200ps
steps.
Don't carry over the description for the "rx-internal-delay-ps" property
and inherit that from ethernet-controller.yaml instead.
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
in the future.
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b
gic,rx-delay-ns" property (yet).
Only include minimalistic logic to fall back to the old property,
without any special validation (for example if the old and new
property are given at the same time).
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
--
etdev mailing list, v2 fixes this
[0]
https://lore.kernel.org/netdev/CAFBinCATt4Hi9rigj52nMf3oygyFbnopZcsakGL=kywnsjy...@mail.gmail.com/
[1]
https://patchwork.kernel.org/project/linux-amlogic/list/?series=384279=%2A=both
[2]
https://patchwork.kernel.org/project/linux-amlogic/list/?series=384491=%
delay as well as configuring the
register accordingly on these platforms.
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 61 +++
1 file changed, 48 insertions(+), 13 deletions(-)
diff
Hi Neil,
On Mon, Jan 4, 2021 at 2:29 PM Neil Armstrong wrote:
>
> Hi,
>
> Sorry for the delay...
>
> On 31/12/2020 00:24, Martin Blumenstingl wrote:
> > Hi Neil and all interested people,
> >
> > in the past there were concerns about how some of the compone
Hi Jakub,
On Mon, Jan 4, 2021 at 10:52 PM Jakub Kicinski wrote:
>
> On Sun, 3 Jan 2021 03:12:21 +0100 Martin Blumenstingl wrote:
> > Hi Andrew,
> >
> > On Sun, Jan 3, 2021 at 3:09 AM Andrew Lunn wrote:
> > >
> > > On Sun, Jan 03, 2021 at 0
se patches as with this rate doubling the
"hdmi_pll_lvds_out" (which is a parent of this tree) is doubled as
well. That's why I am sending these patches because even with this
unknown part about rate doubling they will still be valid once that
unknown part has been figured out.
Martin Blumenstin
at this
"LVDS_CLK_EN" bit actually enables the input of the "hdmi_pll_lvds_out"
clock to the "vid_pll_in_sel" tree.
Add a gate definition for this bit (which will not be exported) so that
the kernel can manage all required bits to enable and disable the video
clocks.
this clock then it divides by 1 by default (only 5 and 6 are used at
runtime by the vendor kernel though)
- vid_pll_post_div is either 1 or 2
- vid_pll_final_div is either 1, 2 or 4
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/meson8b.c | 23 +++
1 file
. The only restriction for values greater than 50 is
that the resulting frequency must not exceed the 3.0GHz limit.
These values are taken from the endlessm 3.10 kernel which includes some
additional M/N combinations for some VESA and 75Hz display modes.
Signed-off-by: Martin Blumenstingl
---
drivers
MPLL1 is needed for audio output. Drop it from the vclk_in_sel parent
list so we only use the (mutable) vid_pll_final_div tree or one of the
(fixed) FCLK_DIV{3,4,5} clocks.
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/meson8b.c | 5 -
1 file changed, 4 insertions(+), 1 deletion
According to the public S805 datasheet the HDMI PLL VCO frequency has to
be between 1.2GHz and 3.0GHz. Add this range in our driver so we won't
get too low (which means the PLL won't lock) or too high.
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/meson8b.c | 5 +
1 file changed
Hi Miquel,
thank you for looking into this
On Mon, Jan 4, 2021 at 9:48 AM Miquel Raynal wrote:
[...]
> > nand_set_flash_node(_host->chip, dev->of_node);
> > - if (!mtd->name) {
> > - dev_err(ebu_host->dev, "NAND label property is mandatory\n");
> > - return
Hi Andrew,
On Sun, Jan 3, 2021 at 3:09 AM Andrew Lunn wrote:
>
> On Sun, Jan 03, 2021 at 02:25:43AM +0100, Martin Blumenstingl wrote:
> > Enable GSWIP_MII_CFG_EN also for internal PHYs to make traffic flow.
> > Without this the PHY link is detected properly and ethtool sta
;)
Cc: sta...@vger.kernel.org
Suggested-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c
index 09701c17f3f6..5d378c8026f0 100644
--- a/d
of the following ports: 0, 1, 5).
Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Cc: sta...@vger.kernel.org
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 23 ++-
1 file changed, 6 insertions(+), 17 deletions(-)
-porting them on top of
Linux 5.4.86 in OpenWrt.
Special thanks to Hauke for debugging and brainstorming this on IRC
with me!
Martin Blumenstingl (2):
net: dsa: lantiq_gswip: Enable GSWIP_MII_CFG_EN also for internal PHYs
net: dsa: lantiq_gswip: Fix GSWIP_MII_CFG(p) register access
drivers/net
for the
hint Rob
- dropped the explicit "select" statement from the dt-bindings in patch
#2 as suggested by Rob (thanks)
[0] https://github.com/xdarklight/zephyr-rtos/commits/amlogic_ao_em4-20201229
[1] https://patchwork.kernel.org/project/linux-amlogic/list/?series=40734
Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4
controller for always-on operations, typically used for managing system
suspend.
Signed-off-by: Martin Blumenstingl
---
.../remoteproc/amlogic,meson-mx-ao-arc.yaml | 87 +++
1 file changed, 87 insertions
, Meson8b and Meson8m2 the "secbus2" IO region is needed as
some bits need to be programmed there. Add this IO region for those
SoCs as well.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson.dtsi | 7 +++
arch/arm/boot/dts/meson8.dtsi | 21 +
arc
SECBUS2 registers.
Signed-off-by: Martin Blumenstingl
---
.../arm/amlogic/amlogic,meson-mx-secbus2.yaml | 42 +++
1 file changed, 42 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml
diff --git
a/Documentation/devicetree/bind
Amlogic Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4 core
typically used for managing system suspend. A section of the SoCs SRAM
is mapped as memory for this ARC core. Add new compatible strings for
the SRAM section for the ARC core memory.
Signed-off-by: Martin Blumenstingl
c_elf_load_rsc_table (rproc_ops.parse_fw) and
rproc_elf_find_loaded_rsc_table (rproc_ops.find_loaded_rsc_table).
Signed-off-by: Martin Blumenstingl
---
drivers/remoteproc/Kconfig | 11 ++
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/meson_mx_ao_arc.c | 240 ++
B 2.0 OTG port
> - 3x USB 3.0 ports
> - IR receiver
> - 1x micro SD card slot (internal)
> - USB SATA controller with 2x 3.5" drive bays
> - 1x Power on/off button
>
> Signed-off-by: Christian Hewitt
I don't know/have this board but also I don't see anything problematic so:
Acked-by: Martin Blumenstingl
On Wed, Dec 30, 2020 at 11:38 AM Christian Hewitt
wrote:
>
> The Shenzen AZW (Beelink) GS-King-X is based on the Amlogic W400 reference
> board with an S922X-H chip.
>
> Signed-off-by: Christian Hewitt
> Acked-by: Rob Herring
Reviewed-by: Martin Blumenstingl
Hi Linus,
On Mon, Dec 21, 2020 at 4:28 PM Martin Blumenstingl
wrote:
>
> Hi Linus,
>
> On Wed, Oct 7, 2020 at 9:44 PM Martin Blumenstingl
> wrote:
> [...]
> > > As noted on the earlier patches I think this should be folded into the
> > > existing XHCI USB d
Hi Neil and all interested people,
in the past there were concerns about how some of the components are
coupled in our Meson DRM driver(s).
With this discussion I would like to achieve four things:
1. understand the current issues that we have
2. come up with a TODO list of things that need to be
, Meson8b and Meson8m2 the "secbus2" IO region is needed as
some bits need to be programmed there. Add this IO region for those
SoCs as well.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson.dtsi | 7 +++
arch/arm/boot/dts/meson8.dtsi | 21 +
arc
EM4 to the Zephyr RTOS. The code can
be found here: [0] (the resulting zephyr.elf can then be loaded as
remote-processor firmware from Linux).
[0] https://github.com/xdarklight/zephyr-rtos/commits/amlogic_ao_em4-20201229
Martin Blumenstingl (5):
dt-bindings: sram: Add compatible strings
SECBUS2 registers.
Signed-off-by: Martin Blumenstingl
---
.../arm/amlogic/amlogic,meson-mx-secbus2.yaml | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml
diff --git
a/Documentation/devicetree/bind
Amlogic Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4 core
typically used for managing system suspend. A section of the SoCs SRAM
is mapped as memory for this ARC core. Add new compatible strings for
the SRAM section for the ARC core memory.
Signed-off-by: Martin Blumenstingl
c_elf_load_rsc_table (rproc_ops.parse_fw) and
rproc_elf_find_loaded_rsc_table (rproc_ops.find_loaded_rsc_table).
Signed-off-by: Martin Blumenstingl
---
drivers/remoteproc/Kconfig | 11 ++
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/meson_mx_ao_arc.c | 240 ++
Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4
controller for always-on operations, typically used for managing system
suspend.
Signed-off-by: Martin Blumenstingl
---
.../remoteproc/amlogic,meson-mx-ao-arc.yaml | 87 +++
1 file changed, 87 insertions
Hi Jakub,
On Mon, Dec 28, 2020 at 9:37 PM Jakub Kicinski wrote:
>
> On Thu, 24 Dec 2020 00:29:00 +0100 Martin Blumenstingl wrote:
> > Hello,
> >
> > with the help of Jianxin Pan (many thanks!) the meaning of the "new"
> > PRG_ETH1[19:16] register bits
Popagate the error code from meson_clk_pll_set_rate() when the PLL does
not lock with the new settings.
Fixes: 722825dcd54b2e ("clk: meson: migrate plls clocks to clk_regmap")
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/clk-pll.c | 5 +++--
1 file changed, 3 insert
The "rate" parameter in meson_clk_pll_set_rate() contains the new rate.
Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try
to switch from the new rate to the same ratte again.
Fixes: 7a29a869434e8b ("clk: meson: Add support for Meson clock controller")
S
on: pll: update driver for the g12a")
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/clk-pll.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 9404609b5ebf..5b932976483f 100644
--- a/drivers/clk/m
unrelated: if you know anything about that clock doubling then
please let me know!
Best regards,
Martin
Martin Blumenstingl (3):
clk: meson: clk-pll: fix initializing the old rate (fallback) for a
PLL
clk: meson: clk-pll: make "ret" a signed integer
clk: meson: clk-pll:
in the future.
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b
=kywnsjy...@mail.gmail.com/
[1] https://patchwork.kernel.org/project/linux-amlogic/list/?series=384279
[2]
https://patchwork.kernel.org/project/linux-amlogic/list/?series=384491=%2A=both
Martin Blumenstingl (5):
dt-bindings: net: dwmac-meson: use picoseconds for the RGMII RX delay
net: stm
nd 2ns. The new
SoCs have support for RGMII RX delays between 0ps and 3000ps in 200ps
steps.
Don't carry over the description for the "rx-internal-delay-ps" property
and inherit that from ethernet-controller.yaml instead.
Signed-off-by: Martin Blumenstingl
---
.../bindings/net/aml
configured but the phy-mode
incicates that the RX delay is not used.
Fixes: 9308c47640d515 ("net: stmmac: dwmac-meson8b: add support for the RX
delay configuration")
Reported-by: Andrew Lunn
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
d
gic,rx-delay-ns" property (yet).
Only include minimalistic logic to fall back to the old property,
without any special validation (for example if the old and new
property are given at the same time).
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
--
delay as well as configuring the
register accordingly on these platforms.
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 61 +++
1 file changed, 48 insertions(+), 13 deletions(-)
diff
Hi Pavel,
On Sun, Dec 20, 2020 at 12:13 AM Pavel Machek wrote:
>
> On Sat 2020-12-19 23:38:25, Martin Blumenstingl wrote:
> > Hi Pavel,
> >
> > On Sat, Dec 19, 2020 at 10:51 PM Pavel Machek wrote:
> > [...]
> > > I can't say I like this one:
> > &g
Hi Jerome,
these patches are two small cleanups for code we don't need anymore.
The first patch removes support for old .dtbs. I am not sure if the
"fallback" logic still works as I have not tried this in a long time.
Martin Blumenstingl (2):
clk: meson: meson8b: remove compatib
CLKID_UNUSED and CLKID_XTAL aren't valid clocks. Remove them since
there are no consumers of this anymore.
Signed-off-by: Martin Blumenstingl
---
include/dt-bindings/clock/meson8b-clkc.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/dt-bindings/clock/meson8b-clkc.h
b/include/dt
The XTAL clock is provided via .dts since Linux 5.6. Remove
compatibility code for .dtbs which are older than that.
The switch to the HHI syscon has been done with Linux 5.1. Also remove
any code needed to support .dtbs that have not switched to the HHI
syscon yet.
Signed-off-by: Martin
Hi Linus,
On Wed, Oct 7, 2020 at 9:44 PM Martin Blumenstingl
wrote:
[...]
> > As noted on the earlier patches I think this should be folded into the
> > existing XHCI USB driver in drivers/usb/host/xhci-pci.c or, if that
> > gets messy, as a separate bolt-on, something like
&g
y to keep the SoC temperature at or below 80°C
which is identical to the vendor kernel (with the exception of one GPU
pixel processor).
The number of GPU cores are not taken into account as this is not
supported.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson8.
y to keep the SoC temperature at or below 80°C
which is identical to the vendor kernel (with the exception of one CPU
frequency step from 1.488GHz to 1.536GHz).
The number of GPU cores are not taken into account as this is not
supported.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/mes
e "generic-adc-thermal" will not probe and not register a thermal
sensor.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 5f074f7aa1a2.
not probe.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson.dtsi | 5 +
arch/arm/boot/dts/meson8b-ec100.dts | 5 -
arch/arm/boot/dts/meson8b-mxq.dts | 5 -
arch/arm/boot/dts/meson8b-odroidc1.dts| 5 -
arch/arm/boot/dts/meson8m2-mxiii
of active GPU pixel processor cores. This is not
supported yet so we skip it.
Martin Blumenstingl (5):
ARM: dts: meson: move iio-hwmon for the SoC temperature to meson.dtsi
ARM: dts: meson: add the ADC thermal sensor to meson.dtsi
ARM: dts: meson8: add the thermal-zones with cooling configura
32-bit Amlogic Meson platforms are using a special ADC channel to read
the SoC temperature. Enable the "generic ADC thermal" driver so this
data can be used to cool the SoC for example by reduing the maximum CPU
and GPU frequencies temporarily.
Signed-off-by: Martin Blumenstingl
---
Hi Pavel,
On Sat, Dec 19, 2020 at 10:51 PM Pavel Machek wrote:
[...]
> I can't say I like this one:
>
>
> > clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
> > - clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
> > - clk_configs->m250_mux.mask =
conflict with the
audio driver on G12A boards. Once the common clock framework can handle
this situation this change can be reverted again.
Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b
/ GXBB DWMAC")
Reported-by: Thomas Graichen
Signed-off-by: Martin
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