DSI host registers it's bridge such that it is
> available for the upstream device to connect to.
>
> Signed-off-by: Matt Redfearn
>
> ---
>
> drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
>
It is not immediately obvious what the expected inputs to these fault
handlers is and how they calculate the number of unset bytes. Having
stared deeply at this in order to fix some corner cases, add some
comments to assist those who follow.
Signed-off-by: Matt Redfearn
---
Changes in v3
Fixes: 8c56208aff77 ("MIPS: lib: memset: Add MIPS R6 support")
Cc: sta...@vger.kernel.org
Signed-off-by: Matt Redfearn
---
Changes in v3:
New patch to fix fault handling during MIPSr6 version of setting
unaligned bytes.
Changes in v2: None
arch/mips/lib/memset.S | 3 ++-
1 file chan
Hi James,
On 21/05/18 17:14, James Hogan wrote:
On Tue, Apr 17, 2018 at 04:40:03PM +0100, Matt Redfearn wrote:
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 1cc306520a55..a06dabe99d4b 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -231,16 +231,25
Hi James,
On 16/05/18 19:05, James Hogan wrote:
On Fri, Apr 20, 2018 at 11:23:07AM +0100, Matt Redfearn wrote:
Previously when performance counters are per-core, rather than
per-thread, the number available were divided by 2 on detection, and the
counters used by each thread in a core were
Hi James,
On 16/05/18 18:59, James Hogan wrote:
On Fri, Apr 20, 2018 at 11:23:06AM +0100, Matt Redfearn wrote:
diff --git a/arch/mips/kernel/perf_event_mipsxx.c
b/arch/mips/kernel/perf_event_mipsxx.c
index 7e2b7d38a774..fe50986e83c6 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch
not work.
Fix this by removing this BMIPS5000 specific path and integrating it
with the generic one. Since BMIPS5000 uses specific extensions to the
perf control register, different fields must be set up to count the
relevant CPU.
Signed-off-by: Matt Redfearn
Tested-by: Florian Fainelli
---
Chan
On 29/03/18 10:49, Matt Redfearn wrote:
Several messages from the MIPS GIC driver include the text "GIC", "GIC
timer", etc, but the format is not standard. Add a pr_fmt of
"mips-gic-timer: " and reword the messages now that they will be
prefixed with the dri
Hi,
On 10/05/18 12:26, Michael Büsch wrote:
On Thu, 10 May 2018 13:20:01 +0200
Rafał Miłecki wrote:
On 10 May 2018 at 13:17, Michael Büsch wrote:
On Thu, 10 May 2018 13:14:01 +0200
Rafał Miłecki wrote:
From: Rafał Miłecki
SSB_PCICORE_HOSTMODE protects MIPS specific code that calls no
Hi Rafał,
On 10/05/18 11:41, Rafał Miłecki wrote:
On 7 May 2018 at 17:44, Larry Finger wrote:
Although commit 882164a4a928 ("ssb: Prevent build of PCI host features in
module") appeared to be harmless, it leads to complete failure of drivers
b43. and b43legacy, and likely affects b44 as well.
Hi Michael,
On 09/05/18 17:27, Michael Büsch wrote:
On Wed, 9 May 2018 13:55:43 +0100
Matt Redfearn wrote:
Hi Larry
On 07/05/18 16:44, Larry Finger wrote:
Matt,
Although commit 882164a4a928 ("ssb: Prevent build of PCI host features
in module") appeared to be harmless, it leads t
Hi Eric,
On 10/05/18 03:39, Eric W. Biederman wrote:
Matt Redfearn writes:
Hi Eric,
On 20/04/18 15:37, Eric W. Biederman wrote:
Filling in struct siginfo before calling force_sig_info a tedious and
error prone process, where once in a great while the wrong fields
are filled out, and
Hi Eric,
On 20/04/18 15:37, Eric W. Biederman wrote:
Filling in struct siginfo before calling force_sig_info a tedious and
error prone process, where once in a great while the wrong fields
are filled out, and siginfo has been inconsistently cleared.
Simplify this process by using the helper for
#x27;ve tested the above patch and it does work for MIPS
(preventing the PCICORE being built into the module).
Tested-by: Matt Redfearn
Thanks & sorry again for the breakage,
Matt
Thanks,
Larry
Hi Robert,
On 04/05/18 13:27, Robert Richter wrote:
On 04.05.18 12:03:12, Matt Redfearn wrote:
As said, oprofile version 0.9.x is still available for cpus that do
not support perf. What is the breakage?
The breakage I originally set out to fix was the MT support in perf.
https://www.linux
Hi Robert,
On 04/05/18 11:26, Robert Richter wrote:
On 04.05.18 10:54:32, Matt Redfearn wrote:
perf is available for MIPS and supports many more CPU types than oprofile.
oprofile userspace seemingly has been broken since 1.0.0 - removing oprofile
support from the MIPS kernel would not break it
Hi Robert,
On 04/05/18 10:30, Robert Richter wrote:
On 24.04.18 14:15:58, Matt Redfearn wrote:
On 24/04/18 14:05, James Hogan wrote:
On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote:
Since it appears that MIPS oprofile support is currently broken, core
oprofile is not getting
On 24/04/18 14:05, James Hogan wrote:
On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote:
Since it appears that MIPS oprofile support is currently broken, core
oprofile is not getting many updates and not as many architectures
implement support for it compared to perf, remove the
97.292878] [<805b24dc>] do_execve+0x38/0x44
[ 97.297669] [<80415a58>] syscall_common+0x34/0x58
[ 97.302924] Code: afb0003c 8e22d4e0 afa20034 <8c820008> 14400170
24030020 8f82000c 26460010 00a09825
Since it appears that MIPS oprofile support is currently broken, core
opro
3: warning: format '%lu' expects argument of
type 'long unsigned int', but argument 4 has type 'size_t' [-Wformat=]
Change the format specifier to %zu for the size_t argument.
Fixes: 4863cc758216 ("cifs: smbd: Avoid allocating iov on the stack")
Signe
On 20/04/18 23:51, Florian Fainelli wrote:
On 04/20/2018 03:23 AM, Matt Redfearn wrote:
This series addresses a few issues with how the MIPS performance
counters code supports the hardware multithreading MT ASE.
Firstly, implementations of the MT ASE may implement performance
counters
per
Hi Michal
On 23/04/18 10:18, Michal Simek wrote:
device->baud is always non zero value because it is checked already in
early_serial8250_setup() before init_port is called.
True, currently init_port is only called from the one location and so
the test is a little redundant, though I don't see
As long as the bootloader has
configured the uart divisor, earlycon should work as long as my patch
"serial: 8250_early: Only set divisor if valid clk & baud" is applied to
avoid a bad divisor getting calculated.
Tested-by: Matt Redfearn
Thanks,
Matt
---
drivers/tty/serial/e
know.
--
From: Matt Redfearn
commit c96eebf07692e53bf4dd5987510d8b550e793598 upstream.
The label .Llast_fixup\@ is jumped to on page fault within the final
byte set loop of memset (on < MIPSR6 architectures). For some reason, in
this fault handler, the v1 register is randomly set to a2 & ST
-by: Matt Redfearn
---
Changes in v3:
Use flag in cpu_data set by cpu_probe.c to indicate feature presence.
Changes in v2: None
arch/mips/include/asm/cpu-features.h | 7 +++
arch/mips/kernel/perf_event_mipsxx.c | 3 ---
arch/mips/oprofile/op_model_mipsxx.c | 2 --
3 files changed, 7
not work.
Fix this by removing this BMIPS5000 specific path and integrating it
with the generic one. Since BMIPS5000 uses specific extensions to the
perf control register, different fields must be set up to count the
relevant CPU.
Signed-off-by: Matt Redfearn
---
Changes in v3: None
Changes in
just set the counter to count the relevant
VPE.
Signed-off-by: Matt Redfearn
---
Changes in v3: None
Changes in v2:
Since BMIPS5000 does not implement per TC counters, we can remove the
check on cpu_has_mipsmt_pertccounters.
arch/mips/kernel/perf_event_mipsxx.c | 18 --
1
tions:u
branches:u
0.005179533 seconds time elapsed
Performance counter stats for './test_prog':
30002 instructions:u
1 branches:u
0.005179467 seconds time elapsed
Signed-off-by: Matt Redfearn
---
Chang
8 perf
stat -e instructions:u,branches:u ./test_prog
Performance counter stats for './test_prog':
30002 instructions:u
10000 branches:u
Signed-off-by: Matt Redfearn
---
Changes in v3: None
Changes in v2:
Fix mipsxx_pmu_enable_event for !#ifde
this by replacing smp_processor_id() with
cpu_vpe_id(¤t_cpu_data), in the vpe_id() macro, and pass vpe_id()
to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also
be removed since they no longer apply.
Signed-off-by: Matt Redfearn
---
Changes in v3: None
Changes in v2: Non
CPUs known to implement this
bit and the MT ASE, specifically, the 34K, 1004K and interAptiv.
Once the presence of the per-tc counter is indicated in cpu_data, tests
for it can be updated to use this flag.
Suggested-by: James Hogan
Signed-off-by: Matt Redfearn
---
Changes in v3:
New patch to
BMIPS5000 does not implement per TC counters, we can remove the
check on cpu_has_mipsmt_pertccounters.
New patch to fix BMIPS5000 system mode perf.
Matt Redfearn (7):
MIPS: Probe for MIPS MT perf counters per TC
MIPS: perf: More robustly probe for the presence of per-tc counters
MIPS: perf
Hi James,
On 18/04/18 00:09, James Hogan wrote:
On Wed, Apr 11, 2018 at 08:50:18AM +0100, Matt Redfearn wrote:
diff --git a/arch/mips/boot/compressed/Makefile
b/arch/mips/boot/compressed/Makefile
index adce180f3ee4..e03f522c33ac 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips
It is not immediately obvious what the expected inputs to these fault
handlers is and how they calculate the number of unset bytes. Having
stared deeply at this in order to fix some corner cases, add some
comments to addist those who follow.
Signed-off-by: Matt Redfearn
---
Changes in v2:
- Add
ention for all instructions in a branch delay slot. This
effectively reverts the above commit, plus other locations introduced
with MIPSR6 support.
Signed-off-by: Matt Redfearn
---
Changes in v2:
- Rebase delay slot indentation on v3 of "MIPS: memset.S: Fix return of
__clear_user from Lpartia
The micromips implementation of bzero additionally clobbers registers t7
& t8. Specify this in the clobbers list when invoking bzero.
Reported-by: James Hogan
Fixes: 26c5e07d1478 ("MIPS: microMIPS: Optimise 'memset' core library
function.")
Cc: sta...@vger.kernel
ld not be set is already contained in
a2, the andi placing a value in v1 is not necessary and actively
harmful in clobbering v1.
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Cc: sta...@vger.kernel.org
Reported-by: James Hogan
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arc
6.12-rc2")
Cc: sta...@vger.kernel.org
Suggested-by: James Hogan
Signed-off-by: Matt Redfearn
---
Changes in v3:
- Just fix the issue at hand
Changes in v2:
- Use James Hogan's suggestion of replacing t1 with a0 to get the
correct remainder count.
arch/mips/lib/memset.S | 2 +-
1 fil
The micromips implementation of bzero additionally clobbers registers t7
& t8. Specify this in the clobbers list when invoking bzero.
Reported-by: James Hogan
Fixes: 26c5e07d1478 ("MIPS: microMIPS: Optimise 'memset' core library
function.")
Cc: sta...@vger.kernel
ention for all instructions in a branch delay slot. This
effectively reverts the above commit, plus other locations introduced
with MIPSR6 support.
Signed-off-by: Matt Redfearn
---
arch/mips/lib/memset.S | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --
ld not be set is already contained in
a2, the andi placing a value in v1 is not necessary and actively
harmful in clobbering v1.
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Cc: sta...@vger.kernel.org
Reported-by: James Hogan
Signed-off-by: Matt Redfearn
---
arch/mips/lib/memset.S | 2 +-
Ci40 (MIPS32) and Cavium Octeon II (MIPS64).
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Cc: sta...@vger.kernel.org
Suggested-by: James Hogan
Signed-off-by: Matt Redfearn
---
Changes in v2:
- Use James Hogan's suggestion of replacing t1 with a0 to get the
correct remain
Hi James,
On 16/04/18 23:13, James Hogan wrote:
On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote:
The __clear_user function is defined to return the number of bytes that
could not be cleared. From the underlying memset / bzero implementation
this means setting register a2 to that
Hi James,
On 16/04/18 21:22, James Hogan wrote:
On Thu, Mar 29, 2018 at 10:28:23AM +0100, Matt Redfearn wrote:
@@ -260,6 +260,11 @@
jr ra
andiv1, a2, STORMASK
This patch looks good, well spotted!
But whats that v1 write about? Any ideas? Seems to go
bridge
arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@1400:
missing bus-range for PCI bridge
Signed-off-by: Matt Redfearn
---
arch/mips/boot/dts/img/boston.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boot/dts/img/boston.dts
b/arch/mips/boot/dts/img
not work.
Fix this by removing this BMIPS5000 specific path and integrating it
with the generic one. Since BMIPS5000 uses specific extensions to the
perf control register, different fields must be set up to count the
relevant CPU.
Signed-off-by: Matt Redfearn
---
Changes in v2:
New patch to
just set the counter to count the relevant
VPE.
Signed-off-by: Matt Redfearn
---
Changes in v2:
Since BMIPS5000 does not implement per TC counters, we can remove the
check on cpu_has_mipsmt_pertccounters.
arch/mips/kernel/perf_event_mipsxx.c | 18 --
1 file changed, 4 inser
tions:u
branches:u
0.005179533 seconds time elapsed
Performance counter stats for './test_prog':
30002 instructions:u
1 branches:u
0.005179467 seconds time elapsed
Signed-off-by: Matt Redfearn
---
Changes in v2:
- Fix
8 perf
stat -e instructions:u,branches:u ./test_prog
Performance counter stats for './test_prog':
30002 instructions:u
10000 branches:u
Signed-off-by: Matt Redfearn
---
Changes in v2:
Fix mipsxx_pmu_enable_event for !#ifdef CONFIG_MIPS_MT_SMP
ar
this by replacing smp_processor_id() with
cpu_vpe_id(¤t_cpu_data), in the vpe_id() macro, and pass vpe_id()
to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also
be removed since they no longer apply.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arc
. A definition of this bit is
added in mipsregs.h for MIPS Technologies. No other implementations
support this feature.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arch/mips/include/asm/mipsregs.h | 5 +
arch/mips/kernel/perf_event_mipsxx.c | 29
CONFIG_MIPS_PERF_SHARED_TC_COUNTERS build
- re-use cpuc variable in mipsxx_pmu_alloc_counter,
mipsxx_pmu_free_counter rather than having sibling_ version.
Since BMIPS5000 does not implement per TC counters, we can remove the
check on cpu_has_mipsmt_pertccounters.
New patch to fix BMIPS5000 system mode perf.
Matt Redfearn (6
tines from lib/.
Signed-off-by: Antony Pavlov
[Matt Redfearn] Use GENERIC_LIB_* named Kconfig entries
Signed-off-by: Matt Redfearn
Cc: Palmer Dabbelt
Cc: Matt Redfearn
Cc: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
Changes in v6: None
Cha
additional CFLAGS are apparently unnecessary - remove them as well.
Signed-off-by: Matt Redfearn
---
Changes in v6:
New patch to fix vmlinuz which requires ashldi3 so must be switched
to come from $(srctree)/lib before the arch/mips/ version is deleted.
This version has been build tested with every
When these are included into arch Kconfig files, maintaining
alphabetical ordering of the selects means these get split up. To allow
for keeping things tidier and alphabetical, rename the selects to
GENERIC_LIB_*
Signed-off-by: Matt Redfearn
Reviewed-by: Palmer Dabbelt
---
Changes in v6: None
From: Palmer Dabbelt
As part of the MIPS conversion to use the generic GCC library routines,
Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2(). This
patch rectifies the problem.
CC: Matt Redfearn
CC: Antony Pavlov
Signed-off-by: Palmer Dabbelt
Reviewed-by: Matt Red
them.
Signed-off-by: Matt Redfearn
Thanks,
Matt
On 04/04/18 10:18, Matt Redfearn wrote:
Since commit "MIPS: use generic GCC library routines from lib/", MIPS
now uses the generic lib/ashldi3.c, but bswapsi.c still comes from
arch/mips/lib. The rules for including these into vmlinuz n
s, and the extra-y rule to clean them.
Signed-off-by: Matt Redfearn
---
arch/mips/boot/compressed/.gitignore | 2 --
arch/mips/boot/compressed/Makefile | 8
2 files changed, 4 insertions(+), 6 deletions(-)
delete mode 100644 arch/mips/boot/compressed/.gitignore
diff --git a/arch
Hi Palmer,
On 29/03/18 22:59, Palmer Dabbelt wrote:
On Thu, 29 Mar 2018 03:41:21 PDT (-0700), matt.redfe...@mips.com wrote:
From: Palmer Dabbelt
As part of the MIPS conversion to use the generic GCC library routines,
Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2().
The vpe_id() macro is now used only in mipsxx_pmu_enable_event when
CONFIG_CPU_BMIPS5000 is defined. Fold the one used definition of the
macro into it's usage and remove the now unused definitions.
Signed-off-by: Matt Redfearn
---
arch/mips/kernel/perf_event_mipsxx.c | 18
tions:u
branches:u
0.005179533 seconds time elapsed
Performance counter stats for './test_prog':
30002 instructions:u
1 branches:u
0.005179467 seconds time elapsed
Signed-off-by: Matt Redfearn
---
arch/mips/ker
8 perf
stat -e instructions:u,branches:u ./test_prog
Performance counter stats for './test_prog':
30002 instructions:u
10000 branches:u
Signed-off-by: Matt Redfearn
---
arch/mips/kernel/perf_event_mipsxx.c | 69 +++
this by replacing smp_processor_id() with
cpu_vpe_id(¤t_cpu_data), in the vpe_id() macro, and pass vpe_id()
to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also
be removed since they no longer apply.
Signed-off-by: Matt Redfearn
---
arch/mips/kernel/perf_event_
flagging their presence. In the case of MIPS
and BMIPS5000 implementations, this bit is Config7.PTC. A definition of
this bit is added in mipsregs.h for both MIPS Technologies
implementations and BMIPS5000.
Signed-off-by: Matt Redfearn
---
The test of Config7.PTC was previously enabled when
MIPS Creator CI40 (2C2T MIPS InterAptiv with per-TC
counters, though for the purposes of testing the per-TC availability was
hardcoded to allow testing both paths).
Series applies to v4.16-rc7
Matt Redfearn (5):
MIPS: perf: More robustly probe for the presence of per-tc counters
MIPS: perf:
tines from lib/.
Signed-off-by: Antony Pavlov
[Matt Redfearn] Use GENERIC_LIB_* named Kconfig entries
Signed-off-by: Matt Redfearn
Cc: Palmer Dabbelt
Cc: Matt Redfearn
Cc: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
Changes in v5:
Actua
When these are included into arch Kconfig files, maintaining
alphabetical ordering of the selects means these get split up. To allow
for keeping things tidier and alphabetical, rename the selects to
GENERIC_LIB_*
Signed-off-by: Matt Redfearn
Reviewed-by: Palmer Dabbelt
---
Changes in v5: None
From: Palmer Dabbelt
As part of the MIPS conversion to use the generic GCC library routines,
Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2(). This
patch rectifies the problem.
CC: Matt Redfearn
CC: Antony Pavlov
Signed-off-by: Palmer Dabbelt
Reviewed-by: Matt Red
On 03/04/18 09:53, James Hogan wrote:
On Thu, Mar 29, 2018 at 11:41:23AM +0100, Matt Redfearn wrote:
This commit removes several generic GCC library routines from
arch/mips/lib/ in favour of similar routines from lib/.
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index
org
Signed-off-by: Matt Redfearn
---
arch/mips/lib/memset.S | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 90bcdf1224ee..3257dca58cad 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -161,
When these are included into arch Kconfig files, maintaining
alphabetical ordering of the selects means these get split up. To allow
for keeping things tidier and alphabetical, rename the selects to
GENERIC_LIB_*
Signed-off-by: Matt Redfearn
Reviewed-by: Palmer Dabbelt
---
Changes in v4
tines from lib/.
Signed-off-by: Antony Pavlov
[Matt Redfearn] Use GENERIC_LIB_* named Kconfig entries
Signed-off-by: Matt Redfearn
Cc: Palmer Dabbelt
Cc: Matt Redfearn
Cc: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
Changes in v4:
Rework
From: Palmer Dabbelt
As part of the MIPS conversion to use the generic GCC library routines,
Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2(). This
patch rectifies the problem.
CC: Matt Redfearn
CC: Antony Pavlov
Signed-off-by: Palmer Dabbelt
Reviewed-by: Matt Red
Several messages from the MIPS GIC driver include the text "GIC", "GIC
timer", etc, but the format is not standard. Add a pr_fmt of
"mips-gic-timer: " and reword the messages now that they will be
prefixed with the driver name.
Signed-off-by: Matt Redfearn
---
Chan
sets a2 to the number of
bytes that could not be cleared (as defined by __clear_user).
Reported-by: Chuanhua Lei
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Cc: sta...@vger.kernel.org
Signed-off-by: Matt Redfearn
---
arch/mips/lib/memset.S | 7 ++-
1 file changed, 6 insertions(+),
first iteration. Without
the second patch, j = 4..63 returns garbage.
Applies on v4.16-rc7
Tested on MIPS creator ci40 (MIPS32) and Cavium Octeon II (MIPS64).
Matt Redfearn (2):
MIPS: memset.S: EVA & fault support for small_memset
MIPS: memset.S: Fix return of __clear_user from Lpartial_fix
etup could give it a spin. My test
I've tested this patch fixes static function graph tracing on the
following platforms:
QEMU (MIPS32r2 P5600)
Creator Ci40 (MIPS32r2 InterAptiv)
Cavium Octeon II (MIPS64r2)
MIPS Boston FPGA with I6400 (MIPS64r6)
So
Tested-by: Matt Redfearn
device runs
Hi Neil,
On 21/03/18 03:00, NeilBrown wrote:
On Tue, Mar 20 2018, Matt Redfearn wrote:
Hi Neil,
On 20/03/18 08:22, NeilBrown wrote:
Further testing showed that the original version of this
patch wasn't 100% reliable. Very occasionally the read
of SYSC_REG_CHIP_NAME0 returns ga
uot;)
Signed-off-by: NeilBrown
Looks good to me
Reviewed-by: Matt Redfearn
---
arch/mips/ralink/mt7621.c | 42 ++
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index 1b274742077d..
Hi Neil,
On 20/03/18 08:22, NeilBrown wrote:
Further testing showed that the original version of this
patch wasn't 100% reliable. Very occasionally the read
of SYSC_REG_CHIP_NAME0 returns garbage. Repeating the
read seems to be reliable, but it hasn't happened enough
for me to be completely
Remove the need to check that __mips_isa_rev is defined by using the
newly added MIPS_ISA_REV.
Signed-off-by: Matt Redfearn
---
arch/mips/vdso/elf.S | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/mips/vdso/elf.S b/arch/mips/vdso/elf.S
index be37bbb1f061
Remove the need to check that __mips_isa_rev is defined by using the
newly added MIPS_ISA_REV.
Signed-off-by: Matt Redfearn
---
arch/mips/net/bpf_jit_asm.S | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/mips/net/bpf_jit_asm.S b/arch/mips/net/bpf_jit_asm.S
Remove the need to check that __mips_isa_rev is defined by using the
newly added MIPS_ISA_REV.
Signed-off-by: Matt Redfearn
---
arch/mips/include/asm/cpu-features.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h
b/arch/mips
compilers builtin if provided, or 0,
which satisfies all current usages.
Suggested-by: Paul Burton
Signed-off-by: Matt Redfearn
---
arch/mips/include/asm/isa-rev.h | 24
1 file changed, 24 insertions(+)
create mode 100644 arch/mips/include/asm/isa-rev.h
diff --git a/arch
__mips_isa_rev are then replaced with the new
define, removing the check that it is defined.
Applies on v4.16-rc1
Matt Redfearn (4):
MIPS: Introduce isa-rev.h to define MIPS_ISA_REV
MIPS: cpu-features.h: Replace __mips_isa_rev with MIPS_ISA_REV
MIPS: BPF: Replace __mips_isa_rev with MIPS_ISA_REV
ge is higher, the minimum and
maximum latencies of handling IPIs on another core are both reduced.
Signed-off-by: Matt Redfearn
---
The logic of mips_smp_send_ipi_mask / mips_smp_send_ipi_single is
reversed here. Neither the CPU nor GIC IRQ driver implements a function
to raise an interrupt on mul
In preparation for allowing selection of a single IPI / CPU, group
affected code together to minimise ifdeffery.
Signed-off-by: Matt Redfearn
---
arch/mips/kernel/smp.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel
greater numbers of IPI
functions to be delivered without using up additional per CPU
interrupts. For example this mechanism may be extended to address the
potential for deadlock in arch_trigger_cpumask_backtrace recently
pointed out by Huacai Chen.
Matt Redfearn (2):
MIPS: SMP: Group
ted-by: Ed Blake
Signed-off-by: Matt Redfearn
series-cc: Ed Blake
---
Changes in v3:
Remove #if defined(CONFIG_PM_SLEEP) around cps_pm_power_notifier which
results in build error if CONFIG_PM_SLEEP is not defined. I believed
that the pm_notifier() registration would harmlessly compile out
ned-off-by: Matt Redfearn
---
Changes in v2:
Fixed CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK -> CPC_Cx_STAT_CONF_EJTAG_PROBE -
thanks kbuild test robot!
arch/mips/kernel/pm-cps.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/mips/kernel/pm-cps.c b/arc
ned-off-by: Matt Redfearn
---
arch/mips/kernel/pm-cps.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 421e06dfee72..2e0f4bad72b9 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cp
On 07/02/18 10:41, Marc Zyngier wrote:
On 07/02/18 09:44, Matt Redfearn wrote:
Hi Marc,
On 07/02/18 09:41, Marc Zyngier wrote:
On 05/02/18 16:45, Matt Redfearn wrote:
Commit 7778c4b27cbe ("irqchip: mips-gic: Use pcpu_masks to avoid reading
GIC_SH_MASK*") removed the read of th
Hi Serge,
On 02/02/18 03:54, Serge Semin wrote:
Memblock allocator can be successfully used from now for early
memory management
Signed-off-by: Serge Semin
---
arch/mips/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3
P27, but the change looks sensible to me.
Reviewed-by: Matt Redfearn
Signed-off-by: Serge Semin
---
arch/mips/sgi-ip27/ip27-memory.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c
index 59133d0a
kernel/addrspace_offset
memory regions.
I don't have a NUMA Loongson to test with, but on a non-NUMA Loongson3
machine, tested as a part of the whole series, this works and looks good
to me.
Reviewed-by: Matt Redfearn
Thanks,
Matt
Signed-off-by: Serge Semin
---
arch/mips/loong
Hi Serge,
On 02/02/18 03:54, Serge Semin wrote:
It is useful to have the kernel virtual memory layout printed
at boot time so to have the full information about the booted
kernel. In some cases it might be unsafe to have virtual
addresses freely visible in logs, so the %pK format is used if
one
Hi Serge,
On 02/02/18 03:54, Serge Semin wrote:
CMA reserves it areas in the memblock allocator. Since we aren't
using bootmem anymore, the reservations copying should be discarded.
Signed-off-by: Serge Semin
Looks good to me
Reviewed-by: Matt Redfearn
Thanks,
Matt
---
arch
sting at this point in the boot sequence should be safe since all
critical areas are now reserved and a minimum of allocations have been
done."
Otherwise, looks good to me.
Reviewed-by: Matt Redfearn
Thanks,
Matt
Signed-off-by: Serge Semin
---
arch/mips/kernel/setup.c | 2 ++
1 fi
Hi Serge,
On 02/02/18 03:54, Serge Semin wrote:
When all the main reservations are done the memblock regions
can be dynamically resized. Additionally it would be useful to have
memblock regions dumped on debug at this point.
Signed-off-by: Serge Semin
Looks good to me.
Reviewed-by: Matt
Hi Serge,
On 02/02/18 03:54, Serge Semin wrote:
If sparsemem is activated all sections with present pages must
be accordingly marked after memblock is fully initialized.
Signed-off-by: Serge Semin
---
arch/mips/kernel/setup.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/mi
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