On 12-10-15 14:38, Michal Simek wrote:
Hi Mike,
On 10/12/2015 02:22 PM, Mike Looijmans wrote:
On 12-10-15 13:16, Michal Simek wrote:
+static int zynq_fpga_ops_write(struct fpga_manager *mgr,
+const char *buf, size_t count)
+{
+ struct zynq_fpga_priv *priv
t reason.
Using the "bin" format in the driver keeps it simple and singular. Userspace
tools can add whatever wrappers and headers they feel appropriate to it, these
checks don't belong in the driver since they will be application specific. For
example, some users would want to verify that
t reason.
Using the "bin" format in the driver keeps it simple and singular. Userspace
tools can add whatever wrappers and headers they feel appropriate to it, these
checks don't belong in the driver since they will be application specific. For
example, some users would want to verify that
On 12-10-15 14:38, Michal Simek wrote:
Hi Mike,
On 10/12/2015 02:22 PM, Mike Looijmans wrote:
On 12-10-15 13:16, Michal Simek wrote:
+static int zynq_fpga_ops_write(struct fpga_manager *mgr,
+const char *buf, size_t count)
+{
+ struct zynq_fpga_priv *priv
On 02-10-15 01:34, Stephen Boyd wrote:
On 09/17, Mike Looijmans wrote:
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscilator capable of generating clock signals ranging from 100kHz
s/oscilator/oscillator
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans
---
v3: After review from Stephen Boyd
Removed "
On 02-10-15 01:34, Stephen Boyd wrote:
On 09/17, Mike Looijmans wrote:
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscilator capable of generating clock signals ranging from 100kHz
s/oscilator/oscillator
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans <mike.looijm...@topic.nl>
---
v3: After revie
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscilator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans
---
v2: Fix e-mail address list (using old maintainer list
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscilator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans
---
.../devicetree/bindings/clock/silabs,si514.txt
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscilator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans <mike.looijm...@topic.nl>
---
.../devicetree/bi
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscilator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans <mike.looijm...@topic.nl>
---
v2: Fix e-mail addres
from user space, and the impact on performance is quite impressive.
On 05-08-15 08:54, Mike Looijmans wrote:
USB network adapters support Jumbo frames. The only thing blocking
that feature is the code in the gadget driver that disposes of
packets larger than 1518 bytes, and the limit on the ioctl
from user space, and the impact on performance is quite impressive.
On 05-08-15 08:54, Mike Looijmans wrote:
USB network adapters support Jumbo frames. The only thing blocking
that feature is the code in the gadget driver that disposes of
packets larger than 1518 bytes, and the limit on the ioctl
ping...
More than a week has passed, haven't seen any response though. Any comments?
On 05-08-15 08:54, Mike Looijmans wrote:
USB network adapters support Jumbo frames. The only thing blocking
that feature is the code in the gadget driver that disposes of
packets larger than 1518 bytes
ping...
More than a week has passed, haven't seen any response though. Any comments?
On 05-08-15 08:54, Mike Looijmans wrote:
USB network adapters support Jumbo frames. The only thing blocking
that feature is the code in the gadget driver that disposes of
packets larger than 1518 bytes
Group names should be smc0_nand_grp and smc0_nor_grp, otherwise you'll
get errors like this if you try to pinmux them via the devicetree:
zynq-pinctrl 700.pinctrl: invalid group "smc0_nand_grp" for function "smc0_nand"
Probably a typo while creating these tables.
Signed-of
Group names should be smc0_nand_grp and smc0_nor_grp, otherwise you'll
get errors like this if you try to pinmux them via the devicetree:
zynq-pinctrl 700.pinctrl: invalid group smc0_nand_grp for function smc0_nand
Probably a typo while creating these tables.
Signed-off-by: Mike Looijmans
Header claims GPL v2, so make the MODULE_LICENSE reflect that properly.
Signed-off-by: Mike Looijmans
---
drivers/gpu/drm/i2c/adv7511.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i2c/adv7511.c b/drivers/gpu/drm/i2c/adv7511.c
index 2aaa3c8..73a4ee6 100644
Header claims GPL v2, so make the MODULE_LICENSE reflect that properly.
Signed-off-by: Mike Looijmans
---
drivers/media/i2c/adv7511.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/i2c/adv7511.c b/drivers/media/i2c/adv7511.c
index 95bcd40..497ee00 100644
Header claims GPL v2, so make the MODULE_LICENSE reflect that properly.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/media/i2c/adv7511.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/i2c/adv7511.c b/drivers/media/i2c/adv7511.c
index
Header claims GPL v2, so make the MODULE_LICENSE reflect that properly.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/gpu/drm/i2c/adv7511.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i2c/adv7511.c b/drivers/gpu/drm/i2c/adv7511.c
index
MTU=15000, PC-to-gadget: 239 Mbps, Gadget-to-PC: 361 Mbps
On boards with slower CPUs the performance improvement will be
relatively much larger, e.g. an OMAP-L138 increased from 40 to
220 Mbps using a similar patch on an 2.6.37 kernel.
Signed-off-by: Mike Looijmans
---
drivers/usb/gadget
MTU=15000, PC-to-gadget: 239 Mbps, Gadget-to-PC: 361 Mbps
On boards with slower CPUs the performance improvement will be
relatively much larger, e.g. an OMAP-L138 increased from 40 to
220 Mbps using a similar patch on an 2.6.37 kernel.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
On 27-07-15 12:28, Kalle Valo wrote:
Mike Looijmans writes:
Fixes commit eae79b4f3e82ca63a53478a161b190a0d38fe526 ("rsi: fix memory leak
in rsi_load_ta_instructions()") which stopped the driver from functioning.
You can abbreviate the commit id:
Fixes commit eae79b4f3e82 ("
ation fails.
Tested on a Topic Miami-Florida board which contains the rsi SDIO chip.
Also added the same kfree() call to the USB glue driver. This was not
tested on actual hardware though, as I only have the SDIO version.
Fixes: eae79b4f3e82 ("rsi: fix memory leak in rsi_load_ta_instructions()")
Miami-Florida board which contains the rsi SDIO chip.
Also added the same kfree() call to the USB glue driver. This was not
tested on actual hardware though, as I only have the SDIO version.
Fixes: eae79b4f3e82 (rsi: fix memory leak in rsi_load_ta_instructions())
Signed-off-by: Mike Looijmans
On 27-07-15 12:28, Kalle Valo wrote:
Mike Looijmans mike.looijm...@topic.nl writes:
Fixes commit eae79b4f3e82ca63a53478a161b190a0d38fe526 (rsi: fix memory leak
in rsi_load_ta_instructions()) which stopped the driver from functioning.
You can abbreviate the commit id:
Fixes commit
ted on a Topic Miami-Florida board which contains the rsi SDIO chip.
Also added the same kfree() call to the USB glue driver. This was not
tested on actual hardware though, as I only have the SDIO version.
Signed-off-by: Mike Looijmans
Cc: sta...@vger.kernel.org
---
drivers/net/wireless/rsi/rs
-Florida board which contains the rsi SDIO chip.
Also added the same kfree() call to the USB glue driver. This was not
tested on actual hardware though, as I only have the SDIO version.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
Cc: sta...@vger.kernel.org
---
drivers/net/wireless/rsi
, or
in combination with additional devices on other controllers.
Kind regards,
Mike Looijmans
System Expert
TOPIC Embedded Products
Eindhovenseweg 32-C, NL-5683 KH Best
Postbus 440, NL-5680 AK Best
Telefoon: +31 (0) 499 33 69 79
Telefax: +31 (0) 499 33 69 70
E-mail: mike.looijm...@topicproducts.com
, or
in combination with additional devices on other controllers.
Kind regards,
Mike Looijmans
System Expert
TOPIC Embedded Products
Eindhovenseweg 32-C, NL-5683 KH Best
Postbus 440, NL-5680 AK Best
Telefoon: +31 (0) 499 33 69 79
Telefax: +31 (0) 499 33 69 70
E-mail: mike.looijm...@topicproducts.com
On 02-07-15 11:39, David Laight wrote:
From: Peter Chen
Sent: 30 June 2015 03:06
On Fri, Jun 26, 2015 at 03:47:03PM +0200, Mike Looijmans wrote:
The datasheet for the 334x PHY mentions that a reset can be performed:
"... by bringing the pin low for a minimum of 1 microsecond and
then
On 02-07-15 11:39, David Laight wrote:
From: Peter Chen
Sent: 30 June 2015 03:06
On Fri, Jun 26, 2015 at 03:47:03PM +0200, Mike Looijmans wrote:
The datasheet for the 334x PHY mentions that a reset can be performed:
... by bringing the pin low for a minimum of 1 microsecond and
then high
on mainline.
Signed-off-by: Mike Looijmans
---
drivers/power/ltc2941-battery-gauge.c | 54 ++-
1 file changed, 8 insertions(+), 46 deletions(-)
diff --git a/drivers/power/ltc2941-battery-gauge.c
b/drivers/power/ltc2941-battery-gauge.c
index daeb086..4adf2ba
on mainline.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/power/ltc2941-battery-gauge.c | 54 ++-
1 file changed, 8 insertions(+), 46 deletions(-)
diff --git a/drivers/power/ltc2941-battery-gauge.c
b/drivers/power/ltc2941-battery-gauge.c
index
r)
> are not the same mtd layer,I found that it's hard to do.
> But for new structure spi controller(such as
> driver/mtd/spi-nor/fsl-quadspi.c) is very reasonable.and
> it can be easy to set spi controller and spi nor into quad mode at the same
> time.
I'm sorry, but I didn'
On 30-06-15 17:42, Graham Moore wrote:
On 06/30/2015 06:17 AM, Mike Looijmans wrote:
Micron QUAD mode expects command, address and data on 4 lanes instead of just
one for command (extended SPI mode). This requires the controller to be in a
special mode, so check first if the controller could
sets QUAD mode for most Micron chips without asking the controller
whether it's possible to do so, and without telling the controller that a
different mode is required, so it couldn't work.
Signed-off-by: Mike Looijmans
---
drivers/mtd/spi-nor/spi-nor.c | 2 ++
1 file changed, 2 insertions(+)
it can be easy to set spi controller and spi nor into quad mode at the same
time.
I'm sorry, but I didn't understand what you meant here.
Kind regards,
Mike Looijmans
System Expert
TOPIC Embedded Products
Eindhovenseweg 32-C, NL-5683 KH Best
Postbus 440, NL-5680 AK Best
Telefoon: +31 (0) 499
On 30-06-15 17:42, Graham Moore wrote:
On 06/30/2015 06:17 AM, Mike Looijmans wrote:
Micron QUAD mode expects command, address and data on 4 lanes instead of just
one for command (extended SPI mode). This requires the controller to be in a
special mode, so check first if the controller could
mode for most Micron chips without asking the controller
whether it's possible to do so, and without telling the controller that a
different mode is required, so it couldn't work.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/mtd/spi-nor/spi-nor.c | 2 ++
1 file changed, 2
ated while already
being supplied from the host PC.
Signed-off-by: Mike Looijmans
---
drivers/usb/chipidea/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index c865abe..4c6cf48 100644
--- a/drivers/usb/chipidea/core.c
+++ b/d
t the
chip will assert the DIR output. 1ms seems like a safe time to wait
for that to happen, so no change there.
Signed-off-by: Mike Looijmans
---
drivers/usb/chipidea/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/co
will assert the DIR output. 1ms seems like a safe time to wait
for that to happen, so no change there.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/usb/chipidea/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb
already
being supplied from the host PC.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/usb/chipidea/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index c865abe..4c6cf48 100644
--- a/drivers/usb/chipidea/core.c
Ping!
Just curious, any further feedback or comment after Arnd Bergmann's ack?
It fixes a bug that took quite some time to discover and analyze, we should
save other people going through that same trouble.
On 07-05-15 14:54, Mike Looijmans wrote:
When dma-coherent transfers are enabled
Ping!
Just curious, any further feedback or comment after Arnd Bergmann's ack?
It fixes a bug that took quite some time to discover and analyze, we should
save other people going through that same trouble.
On 07-05-15 14:54, Mike Looijmans wrote:
When dma-coherent transfers are enabled
and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans
---
v2: Coding style check
Add devicetree binding documentation
v3: Remove clk-private.h and processed
On 02-06-15 09:50, Paul Bolle wrote:
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(>dev, "%s(%u) %#x %#x\n&qu
On 02-06-15 09:50, Paul Bolle wrote:
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(>dev, "%s(%u) %#x %#x\n&qu
On 02-06-15 09:50, Paul Bolle wrote:
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(i2c-dev, %s(%u) %#x %#x\n, __func__
On 02-06-15 09:50, Paul Bolle wrote:
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(i2c-dev, %s(%u) %#x %#x\n, __func__
and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
v2: Coding style check
Add devicetree binding documentation
v3: Remove clk
and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans
---
v2: Coding style check
Add devicetree binding documentation
v3: Remove clk-private.h and processed
and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
v2: Coding style check
Add devicetree binding documentation
v3: Remove clk
On 28-05-15 23:48, Michael Turquette wrote:
Hi Mike,
Quoting Mike Looijmans (2014-12-03 23:26:15)
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports
On 28-05-15 23:48, Michael Turquette wrote:
Hi Mike,
Quoting Mike Looijmans (2014-12-03 23:26:15)
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports
Hello,
I was wondering what happened to this patch? Should I resubmit?
Mike.
On 04-12-14 08:26, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only
Hello,
I was wondering what happened to this patch? Should I resubmit?
Mike.
On 04-12-14 08:26, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only
ory is just confusing. Replace the word "consistent" in the
descriptions into "coherent" to be clear about this. Most hardware
will offer "coherent" memory, so the logical choice here is to adapt
the description to match reality.
Signed-off-by: Mike Looijmans
---
Docume
consistent in the
descriptions into coherent to be clear about this. Most hardware
will offer coherent memory, so the logical choice here is to adapt
the description to match reality.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
Documentation/DMA-API.txt | 27
this patch, the mapped memory is cacheable and the
transfer speed is again 600MB/s (limited by the FPGA) when
the data is in the L2 cache, while data integrity is being
maintained.
The patch has no effect on non-coherent DMA.
Signed-off-by: Mike Looijmans
---
v2: Mistakenly sent the wrong patch whic
Oops, "arch/arm/boot/dts/topic-dyplo.dtsi" should not have been in there. Will
send a v2 patch to correct that.
On 07-05-15 14:00, Mike Looijmans wrote:
When dma-coherent transfers are enabled, the mmap call must
not change the pg_prot flags in the vma struct.
Split the ar
this patch, the mapped memory is cacheable and the
transfer speed is again 600MB/s (limited by the FPGA) when
the data is in the L2 cache, while data integrity is being
maintained.
The patch has no effect on non-coherent DMA.
Signed-off-by: Mike Looijmans
---
arch/arm/boot/dts/topic-dyplo.dtsi | 1 +
a
this patch, the mapped memory is cacheable and the
transfer speed is again 600MB/s (limited by the FPGA) when
the data is in the L2 cache, while data integrity is being
maintained.
The patch has no effect on non-coherent DMA.
Signed-off-by: Mike Looijmans
---
v2: Mistakenly sent the wrong patch whic
Oops, arch/arm/boot/dts/topic-dyplo.dtsi should not have been in there. Will
send a v2 patch to correct that.
On 07-05-15 14:00, Mike Looijmans wrote:
When dma-coherent transfers are enabled, the mmap call must
not change the pg_prot flags in the vma struct.
Split the arm_dma_mmap
, the mapped memory is cacheable and the
transfer speed is again 600MB/s (limited by the FPGA) when
the data is in the L2 cache, while data integrity is being
maintained.
The patch has no effect on non-coherent DMA.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
v2: Mistakenly sent the wrong patch
, the mapped memory is cacheable and the
transfer speed is again 600MB/s (limited by the FPGA) when
the data is in the L2 cache, while data integrity is being
maintained.
The patch has no effect on non-coherent DMA.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
arch/arm/boot/dts/topic-dyplo.dtsi
, the mapped memory is cacheable and the
transfer speed is again 600MB/s (limited by the FPGA) when
the data is in the L2 cache, while data integrity is being
maintained.
The patch has no effect on non-coherent DMA.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
v2: Mistakenly sent the wrong patch
On 12-01-15 04:04, Mike Turquette wrote:
On Thu, Jan 8, 2015 at 11:01 PM, Mike Looijmans wrote:
Just a ping to inform if you've had had time to look at this?
Its in the queue for review this week. A lot to catch up on after the
holidays. Thanks for the ping.
Just another ping, you haven't
On 12-01-15 04:04, Mike Turquette wrote:
On Thu, Jan 8, 2015 at 11:01 PM, Mike Looijmans mike.looijm...@topic.nl wrote:
Just a ping to inform if you've had had time to look at this?
Its in the queue for review this week. A lot to catch up on after the
holidays. Thanks for the ping.
Just
e spi_nor_ids, so
replace them with the correct names for these chips.
This repairs the disappearance of NOR flash on the Miami boards since 3.18.
Signed-off-by: Mike Looijmans
---
drivers/mtd/devices/m25p80.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/
with the correct names for these chips.
This repairs the disappearance of NOR flash on the Miami boards since 3.18.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/mtd/devices/m25p80.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c
The driver reported 30% less than actually measured. This turned out to
be caused by a simple typo in the formula to calculate the LSB quantity.
Signed-off-by: Mike Looijmans
---
drivers/power/ltc2941-battery-gauge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
On 22-01-15 03:24, Sebastian Reichel wrote:
Hi,
On Tue, Oct 28, 2014 at 08:05:12AM +0100, Mike Looijmans wrote:
Both the LTC2941 and LTC2943 measure battery capacity.
The LTC2943 is compatible with the LTC2941, it adds voltage and
temperature monitoring, and uses a slightly different
On 22-01-15 03:24, Sebastian Reichel wrote:
Hi,
On Tue, Oct 28, 2014 at 08:05:12AM +0100, Mike Looijmans wrote:
Both the LTC2941 and LTC2943 measure battery capacity.
The LTC2943 is compatible with the LTC2941, it adds voltage and
temperature monitoring, and uses a slightly different
The driver reported 30% less than actually measured. This turned out to
be caused by a simple typo in the formula to calculate the LSB quantity.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/power/ltc2941-battery-gauge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
ether a timeout must also cause a reset.
Signed-off-by: Mike Looijmans
---
v4: Fix 'return' with a value, in function returning void
.../devicetree/bindings/watchdog/gpio-wdt.txt |5 +++
drivers/watchdog/gpio_wdt.c| 37 +++-
2 files changed,
cause a reset.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
v4: Fix 'return' with a value, in function returning void
.../devicetree/bindings/watchdog/gpio-wdt.txt |5 +++
drivers/watchdog/gpio_wdt.c| 37 +++-
2 files changed, 34
Just a ping to inform if you've had had time to look at this?
Mike.
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only
Just a ping to inform if you've had had time to look at this?
Mike.
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only
On 12/09/2014 07:48 PM, Mark Brown wrote:
On Tue, Dec 09, 2014 at 07:12:30PM +0100, Mike Looijmans wrote:
On 12/09/2014 05:14 PM, Mark Brown wrote:
If a regulator depends on another regulator that happens to be called
later, the kernel always prints a message like this:
reg-fixed-voltage
On 12/09/2014 07:48 PM, Mark Brown wrote:
On Tue, Dec 09, 2014 at 07:12:30PM +0100, Mike Looijmans wrote:
On 12/09/2014 05:14 PM, Mark Brown wrote:
If a regulator depends on another regulator that happens to be called
later, the kernel always prints a message like this:
reg-fixed-voltage
ed, the driver calls clk_round_rate
for two frequencies. If the results are equal, or if the call returns
an error, the driver assumes the clock is fixed.
Signed-off-by: Mike Looijmans
---
v3: Only enable clock once in hw_params which may be called multiple times.
sound/soc/ad
Is this v3 patch okay or are you waiting for additional changes?
Kind regards,
Mike.
On 11/21/2014 10:40 AM, Mike Looijmans wrote:
On some chips, like the TPS386000, the trigger cannot be disabled
and the CPU must keep toggling the line at all times. Add a switch
"always_running&quo
On 12/10/2014 10:34 AM, Lars-Peter Clausen wrote:
On 12/05/2014 01:37 PM, Mike Looijmans wrote:
If the master clock supports programmable rates, program it to generate
the desired frequency. Only apply constraints when the clock is fixed.
This allows proper clock generation for both 44100
On 12/10/2014 10:34 AM, Lars-Peter Clausen wrote:
On 12/05/2014 01:37 PM, Mike Looijmans wrote:
If the master clock supports programmable rates, program it to generate
the desired frequency. Only apply constraints when the clock is fixed.
This allows proper clock generation for both 44100
Is this v3 patch okay or are you waiting for additional changes?
Kind regards,
Mike.
On 11/21/2014 10:40 AM, Mike Looijmans wrote:
On some chips, like the TPS386000, the trigger cannot be disabled
and the CPU must keep toggling the line at all times. Add a switch
always_running to keep
for two frequencies. If the results are equal, or if the call returns
an error, the driver assumes the clock is fixed.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
v3: Only enable clock once in hw_params which may be called multiple times.
sound/soc/adi/axi-spdif.c | 62
are errors.
--
Mike Looijmans
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Please read the FAQ at http://www.tux.org/lkml/
the message to debug level.
This fixes a storm of error messages at boot when a board has a power
regulator on an I2C bus which powers GPIO controlled regulators for
example.
Signed-off-by: Mike Looijmans
---
drivers/regulator/core.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
If the regulator cannot be registered because its supplier is not
available yet, don't write an error. There is no need to alert the
user of probe deferrals.
This fixes a storm of error messages at boot when a GPIO controlled
regulator is supplied by an I2C controlled supply.
Signed-off-by: Mike
Just a ping to ask for attention. Anyone care to review, comment or otherwise
provide some feedback?
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five
Just a ping to ask for attention. Anyone care to review, comment or otherwise
provide some feedback?
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five
If the regulator cannot be registered because its supplier is not
available yet, don't write an error. There is no need to alert the
user of probe deferrals.
This fixes a storm of error messages at boot when a GPIO controlled
regulator is supplied by an I2C controlled supply.
Signed-off-by: Mike
the message to debug level.
This fixes a storm of error messages at boot when a board has a power
regulator on an I2C bus which powers GPIO controlled regulators for
example.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/regulator/core.c |2 +-
1 file changed, 1 insertion(+), 1
are errors.
--
Mike Looijmans
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
cies. If the results are equal, or if the call returns
an error, the driver assumes the clock is fixed.
Signed-off-by: Mike Looijmans
---
v2: Fix fixed clock detection as discussed.
sound/soc/adi/axi-spdif.c | 60 -
1 file changed, 38 insertions(+), 2
are equal, or if the call returns
an error, the driver assumes the clock is fixed.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
v2: Fix fixed clock detection as discussed.
sound/soc/adi/axi-spdif.c | 60 -
1 file changed, 38 insertions(+), 22
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