Re: Fw: [PATCH] ia64: race flushing icache in do_no_page path

cache flushing operations. It just happens to be doing it with a bad race condition for ia64. -- Mike Stroyan <[EMAIL PROTECTED]> - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info a

Re: [BUGFIX][PATCH] DO flush icache before set_pte() on ia64.

/mprotect.c | 10 +- > mm/rmap.c |1 - > 9 files changed, 43 insertions(+), 32 deletions(-) You don't seem to have removed the lazy_mmu_prot_update() calls from mm/hugetlb.c. Will that build with HUGETLBFS configured? -- Mike Stroy

Re: Fw: [PATCH] ia64: race flushing icache in do_no_page path

n caches at all levels of cache. That handles the update of L1 icache lines during a st,fc.i,sync.i,srlz.i sequence. I see these details in section 6.1.1 of "Intel® Itanium® 2 Processor Reference Manual". But I haven't found them in a general Itanium Architecture reference. -

Re: Fw: [PATCH] ia64: race flushing icache in do_no_page path

hile (0) lazy_mmu_prot_update() is supposed to get icache flushes done when they need to be. And it is supposed to avoid unneeded flushes when the icache is known to be clean for a page. -- Mike Stroyan, [EMAIL PROTECTED] - To unsubscribe from this list: send the line "unsubscribe linu

[PATCH] ia64: race flushing icache in do_no_page path

suspect that the non-NFS case is working because direct DMA into the new page is making the instruction cache coherent. Any file system that uses a non-DMA copy into the text page could show the same problem. Signed-off-by: Mike Stroyan <[EMAIL PROTECTED]> diff --git a/mm/memory.c b/mm/me