Use a sequence for enabling hardware control of the SATA PLL
that works both when using the SATA lane with SATA and when
using it with XUSB.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
Andrew: yes, it does :)
Peter: Feel free to squash if that works for you.
drivers/clk/tegra/clk
Hey Tejun,
the prerequisites for this series have now been acked and it would be
nice to have it for 3.17. Could you take a look at it?
Thanks,
Mikko
On 26/06/14 14:18, Mikko Perttunen wrote:
FWIW, from IRC, the series
Tested-by: Steev Klimaszewski st...@gentoo.org
On 24/06/14 22:35
On 08/07/14 16:08, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jun 09, 2014 at 09:49:24PM +0300, Mikko Perttunen wrote:
On 06/09/2014 09:33 PM, Stephen Warren wrote:
On 06/06/2014 12:27 AM, Mikko Perttunen wrote:
The only compile-time dependencies here should
Thanks, I'll fix these.
On 08/07/14 16:22, Tejun Heo wrote:
(cc'ing Hans)
Hans, can you please review this patch?
On Wed, Jun 18, 2014 at 05:23:25PM +0300, Mikko Perttunen wrote:
+#define SATA_CONFIGURATION_0 0x180
+#defineSATA_CONFIGURATION_EN_FPCI
On 04/07/14 11:43, Wei Ni wrote:
On 06/27/2014 04:11 PM, Mikko Perttunen wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
the four thermal zones with hardware-tracked trip points.
diff
On 04/07/14 11:43, Wei Ni wrote:
On 06/27/2014 04:11 PM, Mikko Perttunen wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
the four thermal zones with hardware-tracked trip points.
diff
On 01/07/14 21:15, Stephen Warren wrote:
The thermal core only supports a fixed number of trip points for each
driver and the core informs the driver of any changes to those, so
drivers using the core framework can already have hardware trip points,
but just a fixed number of them.
The way
On 01/07/14 21:26, Stephen Warren wrote:
Ah, so there's some manufacturing calibration process that sets some
fuse value, and the HW uses a combination of that fuse value, and some
parameters of the manufacturing process as represented by the
SENSOR_CONFIG2 register, to apply the calibration?
On 01/07/14 21:26, Stephen Warren wrote:
Ah, so there's some manufacturing calibration process that sets some
fuse value, and the HW uses a combination of that fuse value, and some
parameters of the manufacturing process as represented by the
SENSOR_CONFIG2 register, to apply the calibration?
On 01/07/14 21:15, Stephen Warren wrote:
The thermal core only supports a fixed number of trip points for each
driver and the core informs the driver of any changes to those, so
drivers using the core framework can already have hardware trip points,
but just a fixed number of them.
The way
Inline.
On 01/07/14 00:23, Stephen Warren wrote:
On 06/27/2014 02:11 AM, Mikko Perttunen wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
the four thermal zones with hardware-tracked trip
Inline.
On 30/06/14 23:48, Stephen Warren wrote:
On 06/27/2014 02:11 AM, Mikko Perttunen wrote:
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones it exports.
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot
Inline.
On 01/07/14 00:08, Stephen Warren wrote:
On 06/27/2014 02:11 AM, Mikko Perttunen wrote:
This adds support for hardware-tracked trip points to the device tree
thermal sensor framework.
The framework supports an arbitrary number of trip points. Whenever
the current temperature
Inline.
On 01/07/14 00:08, Stephen Warren wrote:
On 06/27/2014 02:11 AM, Mikko Perttunen wrote:
This adds support for hardware-tracked trip points to the device tree
thermal sensor framework.
The framework supports an arbitrary number of trip points. Whenever
the current temperature
Inline.
On 30/06/14 23:48, Stephen Warren wrote:
On 06/27/2014 02:11 AM, Mikko Perttunen wrote:
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones it exports.
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot
Inline.
On 01/07/14 00:23, Stephen Warren wrote:
On 06/27/2014 02:11 AM, Mikko Perttunen wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
the four thermal zones with hardware-tracked trip
-tracked trip point support. While the
hardware supports four tracked trip points, only one is used.
Mikko Perttunen (6):
thermal: of: Add support for hardware-tracked trip points
of: Add bindings for nvidia,tegra124-soctherm
ARM: tegra: Add thermal trip points for Jetson TK1
ARM: tegra: Add
This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.
Signed-off-by: Mikko Perttunen
---
.../devicetree/bindings/thermal/tegra-soctherm.txt | 32 ++
include/dt-bindings/thermal/tegra124-soctherm.h| 15 ++
2 files changed, 47
-by: Mikko Perttunen
---
drivers/thermal/of-thermal.c | 97 ++--
include/linux/thermal.h | 3 +-
2 files changed, 95 insertions(+), 5 deletions(-)
diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c
index 04b1be7..bfccea5 100644
This adds the two clocks, soctherm and tsensor, to the T124 initialization
table.
They are required for soctherm-based thermal sensing.
Signed-off-by: Mikko Perttunen
---
Peter, one more zero for TSENSOR, please :)
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 32 +++
1
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
the four thermal zones with hardware-tracked trip points.
Signed-off-by: Mikko Perttunen
---
drivers/thermal/Kconfig | 7 +
drivers
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones it exports.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 48 +
1 file changed, 48 insertions(+)
diff --git
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones it exports.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
arch/arm/boot/dts/tegra124.dtsi | 48 +
1 file changed, 48
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
the four thermal zones with hardware-tracked trip points.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
drivers/thermal/Kconfig
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 32
This adds the two clocks, soctherm and tsensor, to the T124 initialization
table.
They are required for soctherm-based thermal sensing.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
Peter, one more zero for TSENSOR, please :)
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2
-by: Mikko Perttunen mperttu...@nvidia.com
---
drivers/thermal/of-thermal.c | 97 ++--
include/linux/thermal.h | 3 +-
2 files changed, 95 insertions(+), 5 deletions(-)
diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c
index 04b1be7
-tracked trip point support. While the
hardware supports four tracked trip points, only one is used.
Mikko Perttunen (6):
thermal: of: Add support for hardware-tracked trip points
of: Add bindings for nvidia,tegra124-soctherm
ARM: tegra: Add thermal trip points for Jetson TK1
ARM: tegra: Add
This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
.../devicetree/bindings/thermal/tegra-soctherm.txt | 32 ++
include/dt-bindings/thermal/tegra124-soctherm.h| 15 ++
2
FWIW, from IRC, the series
> Tested-by: Steev Klimaszewski
On 24/06/14 22:35, Stephen Warren wrote:
On 06/18/2014 08:23 AM, Mikko Perttunen wrote:
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
At a quick gla
FWIW, from IRC, the series
Tested-by: Steev Klimaszewski st...@gentoo.org
On 24/06/14 22:35, Stephen Warren wrote:
On 06/18/2014 08:23 AM, Mikko Perttunen wrote:
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra114 and Tegra124. The thermal reset only works when the thermal
sensors are calibrated, so a soctherm driver is also required.
Signed-off-by: Mikko Perttunen
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones it exports.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 47 +
1 file changed, 47 insertions(+)
diff --git
This adds the two clocks, soctherm and tsensor, to the T124 initialization
table.
They are required for soctherm-based thermal sensing.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. Only polling-based thermal
sensing and overheating reset are supported for now.
Signed-off-by: Mikko Perttunen
---
drivers/thermal/Kconfig | 6 +
drivers/thermal
ler
shutdown. Should there be a new trip level for an uncontrolled shutdown?
Any thoughts would be appreciated.
Thanks,
Mikko Perttunen
Mikko Perttunen (5):
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree
ARM
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
there be a new trip level for an uncontrolled shutdown?
Any thoughts would be appreciated.
Thanks,
Mikko Perttunen
Mikko Perttunen (5):
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree
ARM: tegra: Add thermal
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. Only polling-based thermal
sensing and overheating reset are supported for now.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
drivers/thermal/Kconfig | 6
This adds the two clocks, soctherm and tsensor, to the T124 initialization
table.
They are required for soctherm-based thermal sensing.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra114 and Tegra124. The thermal reset only works when the thermal
sensors are calibrated, so a soctherm driver is also required.
Signed-off-by: Mikko Perttunen
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones it exports.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
arch/arm/boot/dts/tegra124.dtsi | 47 +
1 file changed, 47
Hi,
This series adds support for the onboard AHCI-compliant Serial ATA
controller found on Tegra124 systems-on-chip. The series depends on
Thierry's XUSB pinctrl driver.
A branch containing the series is located at
git://github.com/cyndis/linux.git
branch ahci-rel-v2.
Mikko Perttunen
This patch adds device tree binding documentation for the SATA
controller found on NVIDIA Tegra SoCs.
Signed-off-by: Mikko Perttunen
---
v2:
- added target-5v-supply and target-12v-supply
- changed wording to be similar with other Tegra drivers
.../devicetree/bindings/ata/tegra-sata.txt
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen
Acked-by: Stephen Warren
---
drivers/clk/tegra/clk-pll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c b
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
Signed-off-by: Mikko Perttunen
---
v2:
- added clock-names property
- changed 0 -> GIC_SPI
arch/arm/boot/dts/tegra124.dtsi | 25 +
1 f
.
Signed-off-by: Mikko Perttunen
---
v2:
- added target-v5-supply and target-12v-supply
- made sata power not always-on
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm
This adds ATA, SATA_AHCI and AHCI_TEGRA support to tegra_defconfig
so that the SATA support will be automatically enabled.
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/tegra_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm
This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization
table. The clocks are needed for working SATA support.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen
---
v2:
- removed redundant of_match_device
- fixed fuse offsets
- added newlines to dev_err calls
- get 5v/12v supplies
- mask calibration fuse
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
v2:
- removed redundant of_match_device
- fixed fuse offsets
- added newlines to dev_err calls
- get 5v/12v supplies
This adds ATA, SATA_AHCI and AHCI_TEGRA support to tegra_defconfig
so that the SATA support will be automatically enabled.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
arch/arm/configs/tegra_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs
This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization
table. The clocks are needed for working SATA support.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra
.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
v2:
- added target-v5-supply and target-12v-supply
- made sata power not always-on
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
v2:
- added clock-names property
- changed 0 - GIC_SPI
arch/arm/boot/dts/tegra124.dtsi | 25
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Acked-by: Stephen Warren swar...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 8
1 file changed, 8 insertions(+)
diff
This patch adds device tree binding documentation for the SATA
controller found on NVIDIA Tegra SoCs.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
v2:
- added target-5v-supply and target-12v-supply
- changed wording to be similar with other Tegra drivers
.../devicetree/bindings/ata
Hi,
This series adds support for the onboard AHCI-compliant Serial ATA
controller found on Tegra124 systems-on-chip. The series depends on
Thierry's XUSB pinctrl driver.
A branch containing the series is located at
git://github.com/cyndis/linux.git
branch ahci-rel-v2.
Mikko Perttunen
On 06/17/2014 08:04 PM, Bartlomiej Zolnierkiewicz wrote:
Hi,
On Tuesday, June 17, 2014 10:10:23 AM Stephen Warren wrote:
On 06/17/2014 06:14 AM, Bartlomiej Zolnierkiewicz wrote:
[...]
+static struct platform_driver tegra_ahci_driver = {
+ .probe = tegra_ahci_probe,
+ .remove =
On 06/17/2014 07:15 PM, Stephen Warren wrote:
On 06/17/2014 06:16 AM, Tomeu Vizoso wrote:
On 06/16/2014 10:02 PM, Stephen Warren wrote:
On 06/16/2014 07:35 AM, Tomeu Vizoso wrote:
This binding looks quite anaemic vs.
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt; I
I'll try removing use of all libahci_platform stuff except
ahci_platform_init_host for v2.
On 17/06/14 15:13, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jun 16, 2014 at 04:01:02PM -0600, Stephen Warren wrote:
On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
This symbol needs
be
returned even when a PHY is needed.
This patch modifies the -ENOSYS case to check if a "phys"
device tree node exists. If it exists, then clearly the PHY
subsystem is mistakenly disabled and the driver cannot work,
ahci_platform_get_resources will fail and propagate the error.
Signed-off
be
returned even when a PHY is needed.
This patch modifies the -ENOSYS case to check if a phys
device tree node exists. If it exists, then clearly the PHY
subsystem is mistakenly disabled and the driver cannot work,
ahci_platform_get_resources will fail and propagate the error.
Signed-off-by: Mikko
I'll try removing use of all libahci_platform stuff except
ahci_platform_init_host for v2.
On 17/06/14 15:13, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jun 16, 2014 at 04:01:02PM -0600, Stephen Warren wrote:
On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
This symbol needs
On 06/17/2014 07:15 PM, Stephen Warren wrote:
On 06/17/2014 06:16 AM, Tomeu Vizoso wrote:
On 06/16/2014 10:02 PM, Stephen Warren wrote:
On 06/16/2014 07:35 AM, Tomeu Vizoso wrote:
This binding looks quite anaemic vs.
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt; I
On 06/17/2014 08:04 PM, Bartlomiej Zolnierkiewicz wrote:
Hi,
On Tuesday, June 17, 2014 10:10:23 AM Stephen Warren wrote:
On 06/17/2014 06:14 AM, Bartlomiej Zolnierkiewicz wrote:
[...]
+static struct platform_driver tegra_ahci_driver = {
+ .probe = tegra_ahci_probe,
+ .remove =
The tegra-cpufreq driver is only for Tegra20, an upcoming driver for
Tegra124 will be separate, so this is not needed.
Thanks,
- Mikko
On 06/16/2014 04:35 PM, Tomeu Vizoso wrote:
Instead of setting a direct correlation to the CPU frequency. This allows
for other devices to influence the final
It should be mentioned that calling clk_set_rate on the EMC clock
currently does absolutely nothing (except probably returning an error).
The rate switching sequence is not implemented (nor is the clock tree
entirely correct. For example, the kernel thinks that PLL_M is disabled).
Another
It should be mentioned that calling clk_set_rate on the EMC clock
currently does absolutely nothing (except probably returning an error).
The rate switching sequence is not implemented (nor is the clock tree
entirely correct. For example, the kernel thinks that PLL_M is disabled).
Another
The tegra-cpufreq driver is only for Tegra20, an upcoming driver for
Tegra124 will be separate, so this is not needed.
Thanks,
- Mikko
On 06/16/2014 04:35 PM, Tomeu Vizoso wrote:
Instead of setting a direct correlation to the CPU frequency. This allows
for other devices to influence the final
On 05/06/14 16:09, Peter De Schrijver wrote:
...
+int tegra_fuse_readl(u32 offset, u32 *val)
+{
+ if (!fuse_readl)
+ return -ENXIO;
+
+ *val = fuse_readl(offset);
+
+ return 0;
+}
+
-EPROBE_DEFER would be a better error value, so that drivers can work
even if
On 05/06/14 16:09, Peter De Schrijver wrote:
...
+int tegra_fuse_readl(u32 offset, u32 *val)
+{
+ if (!fuse_readl)
+ return -ENXIO;
+
+ *val = fuse_readl(offset);
+
+ return 0;
+}
+
-EPROBE_DEFER would be a better error value, so that drivers can work
even if
On 06/09/2014 09:33 PM, Stephen Warren wrote:
On 06/06/2014 12:27 AM, Mikko Perttunen wrote:
The only compile-time dependencies here should be that:
- patch 8 of 9 which contains the actual driver depends on patch 6 of 9
(though only when building as a module) and the efuse series
- patch 2
On 06/09/2014 09:33 PM, Stephen Warren wrote:
On 06/06/2014 12:27 AM, Mikko Perttunen wrote:
The only compile-time dependencies here should be that:
- patch 8 of 9 which contains the actual driver depends on patch 6 of 9
(though only when building as a module) and the efuse series
- patch 2
be
returned even when a PHY is needed.
This patch modifies the -ENOSYS case to check if a "phys"
device tree node exists. If it exists, then clearly the PHY
subsystem is mistakenly disabled and the driver cannot work,
ahci_platform_get_resources will fail and propagate the error.
Signed-off
Yes, that might be the easiest. If you go that way, you should probably
also add an #include for the XUSB binding include file.
- Mikko
On 06/06/14 10:11, Thierry Reding wrote:
* PGP Signed by an unknown key
On Fri, Jun 06, 2014 at 09:27:07AM +0300, Mikko Perttunen wrote:
The only compile
submitted xusb series, the node isn't actually
named, though. I will fix this in v2)
- Mikko
On 05/06/14 20:29, Stephen Warren wrote:
On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
Hi,
This series adds support for the onboard AHCI-compliant Serial ATA
controller found on Tegra124 syste
series, the node isn't actually
named, though. I will fix this in v2)
- Mikko
On 05/06/14 20:29, Stephen Warren wrote:
On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
Hi,
This series adds support for the onboard AHCI-compliant Serial ATA
controller found on Tegra124 systems-on-chip
Yes, that might be the easiest. If you go that way, you should probably
also add an #include for the XUSB binding include file.
- Mikko
On 06/06/14 10:11, Thierry Reding wrote:
* PGP Signed by an unknown key
On Fri, Jun 06, 2014 at 09:27:07AM +0300, Mikko Perttunen wrote:
The only compile
be
returned even when a PHY is needed.
This patch modifies the -ENOSYS case to check if a phys
device tree node exists. If it exists, then clearly the PHY
subsystem is mistakenly disabled and the driver cannot work,
ahci_platform_get_resources will fail and propagate the error.
Signed-off-by: Mikko
Thanks, will remove.
- Mikko
On 05/06/14 15:18, Rob Herring wrote:
On Wed, Jun 4, 2014 at 6:32 AM, Mikko Perttunen wrote:
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen
Thanks, will remove.
- Mikko
On 05/06/14 15:18, Rob Herring wrote:
On Wed, Jun 4, 2014 at 6:32 AM, Mikko Perttunen mperttu...@nvidia.com wrote:
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko
This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization
table. The clocks are needed for working SATA support.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
Signed-off-by: Mikko Perttunen
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/tegra124.dtsi | 24
1 file changed, 24 insertions(+)
diff
The Tegra AHCI device requires four clocks, so increase the maximum
amount of handled clocks from three to four.
Signed-off-by: Mikko Perttunen
---
drivers/ata/ahci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 05882e4
This patch adds device tree binding documentation for the SATA
controller found on NVIDIA Tegra SoCs.
Signed-off-by: Mikko Perttunen
Cc: devicet...@vger.kernel.org
---
.../devicetree/bindings/ata/tegra-sata.txt | 29 ++
1 file changed, 29 insertions(+)
create mode
.
Signed-off-by: Mikko Perttunen
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 36 +++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 38d3087
is located at
git://github.com/cyndis/linux.git
branch ahci-rel.
Mikko Perttunen (9):
of: Add NVIDIA Tegra SATA controller binding
ARM: tegra: Add SATA controller to Tegra124 device tree
ARM: tegra: Add SATA and SATA power to Jetson TK1 device tree
clk: tegra: Enable hardware control
This symbol needs to be exported to power on rails without using
tegra_powergate_sequence_power_up. tegra_powergate_sequence_power_up
cannot be used in situations where the driver wants to handle clocking
by itself.
Signed-off-by: Mikko Perttunen
---
arch/arm/mach-tegra/powergate.c | 1 +
1
This adds ATA, SATA_AHCI and AHCI_TEGRA support to tegra_defconfig
so that the SATA support will be automatically enabled.
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/tegra_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen
---
drivers/ata/Kconfig | 9 ++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_tegra.c | 386
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-pll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers
This symbol needs to be exported to power on rails without using
tegra_powergate_sequence_power_up. tegra_powergate_sequence_power_up
cannot be used in situations where the driver wants to handle clocking
by itself.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
arch/arm/mach-tegra
This adds ATA, SATA_AHCI and AHCI_TEGRA support to tegra_defconfig
so that the SATA support will be automatically enabled.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
arch/arm/configs/tegra_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
drivers/ata/Kconfig | 9 ++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_tegra.c | 386
is located at
git://github.com/cyndis/linux.git
branch ahci-rel.
Mikko Perttunen (9):
of: Add NVIDIA Tegra SATA controller binding
ARM: tegra: Add SATA controller to Tegra124 device tree
ARM: tegra: Add SATA and SATA power to Jetson TK1 device tree
clk: tegra: Enable hardware control
.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 36 +++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
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