[PATCH v3 7/7] arm64: tegra: Add device tree for the Tegra194 P2972-0000 board

Add device tree files for the Tegra194 P2972- development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/Makefile| 1 + arch/arm64/boot/dts/nvidia/te

[PATCH v3 3/7] soc/tegra: pmc: Add Tegra194 compatibility string

The Tegra194 PMC is mostly compatible with Tegra186, including in all currently supported features. As such, add a new compatibility string but point to the existing Tegra186 SoC data for now. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/soc/tegra/pmc.c | 1 +

[PATCH v3 3/7] soc/tegra: pmc: Add Tegra194 compatibility string

The Tegra194 PMC is mostly compatible with Tegra186, including in all currently supported features. As such, add a new compatibility string but point to the existing Tegra186 SoC data for now. Signed-off-by: Mikko Perttunen --- drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff

[PATCH v3 7/7] arm64: tegra: Add device tree for the Tegra194 P2972-0000 board

Add device tree files for the Tegra194 P2972- development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/Makefile| 1 + arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248

Re: [PATCH v2 6/7] arm64: tegra: Add Tegra194 chip device tree

On 10.02.2018 00:54, Rob Herring wrote: On Tue, Feb 06, 2018 at 09:22:36AM +0200, Mikko Perttunen wrote: ... index ..dcc6eea52684 --- /dev/null +++ b/include/dt-bindings/clock/tegra194-clock.h @@ -0,0 +1,664 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018

Re: [PATCH v2 6/7] arm64: tegra: Add Tegra194 chip device tree

On 10.02.2018 00:54, Rob Herring wrote: On Tue, Feb 06, 2018 at 09:22:36AM +0200, Mikko Perttunen wrote: ... index ..dcc6eea52684 --- /dev/null +++ b/include/dt-bindings/clock/tegra194-clock.h @@ -0,0 +1,664 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018

Re: [PATCH v2 6/7] arm64: tegra: Add Tegra194 chip device tree

On 07.02.2018 12:21, Marc Zyngier wrote: Hi Mikko, On 06/02/18 07:22, Mikko Perttunen wrote: Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UA

Re: [PATCH v2 6/7] arm64: tegra: Add Tegra194 chip device tree

On 07.02.2018 12:21, Marc Zyngier wrote: Hi Mikko, On 06/02/18 07:22, Mikko Perttunen wrote: Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UA

Re: [PATCH v2 4/7] dt-bindings: tegra: Add missing chips and NVIDIA boards

On 02/10/2018 12:49 AM, Rob Herring wrote: On Tue, Feb 06, 2018 at 09:22:34AM +0200, Mikko Perttunen wrote: Add compatibility strings for supported but undocumented Tegra chips (Tegra114/124/132/210/186/194) and reference boards. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.

Re: [PATCH v2 4/7] dt-bindings: tegra: Add missing chips and NVIDIA boards

On 02/10/2018 12:49 AM, Rob Herring wrote: On Tue, Feb 06, 2018 at 09:22:34AM +0200, Mikko Perttunen wrote: Add compatibility strings for supported but undocumented Tegra chips (Tegra114/124/132/210/186/194) and reference boards. Signed-off-by: Mikko Perttunen --- Notes: v2: - add

[PATCH v2 6/7] arm64: tegra: Add Tegra194 chip device tree

Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UART console. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvid

[PATCH v2 6/7] arm64: tegra: Add Tegra194 chip device tree

Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UART console. Signed-off-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/tegra194.dtsi

[PATCH v2 1/7] firmware: tegra: Simplify channel management

channel are supported, and channels are not required to be placed contiguously in memory. The same configuration also works on T186 so we end up with less code. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/firmware/tegra/bpmp.c

[PATCH v2 5/7] dt-bindings: tegra: Add documentation for nvidia,tegra194-pmc

The Tegra194 power management controller has one additional register aperture to be specified in the device tree node. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> Reviewed-by: Rob Herring <r...@kernel.org> --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186

[PATCH v2 1/7] firmware: tegra: Simplify channel management

channel are supported, and channels are not required to be placed contiguously in memory. The same configuration also works on T186 so we end up with less code. Signed-off-by: Mikko Perttunen --- drivers/firmware/tegra/bpmp.c | 142 +++--- include/soc/tegra

[PATCH v2 5/7] dt-bindings: tegra: Add documentation for nvidia,tegra194-pmc

The Tegra194 power management controller has one additional register aperture to be specified in the device tree node. Signed-off-by: Mikko Perttunen Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++ 1 file changed, 2 insertions(+) diff

[PATCH v2 0/7] Initial support for NVIDIA Tegra194

e required in the BPMP driver to support the new channel layout in Tegra194. The series has been tested on Tegra186 (Jetson TX2) and Tegra194 (P2972). Cheers, Mikko Mikko Perttunen (7): firmware: tegra: Simplify channel management soc/tegra: Add Tegra194 SoC configuration option soc/tegra: pmc: Ad

[PATCH v2 4/7] dt-bindings: tegra: Add missing chips and NVIDIA boards

Add compatibility strings for supported but undocumented Tegra chips (Tegra114/124/132/210/186/194) and reference boards. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- Notes: v2: - add patch Documentation/devicetree/bindings/arm/tegra.txt | 16

[PATCH v2 7/7] arm64: tegra: Add device tree for the Tegra194 P2972-0000 board

Add device tree files for the Tegra194 P2972- development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/Makefile| 1 + arch/arm64/boot/dts/nvidia/te

[PATCH v2 0/7] Initial support for NVIDIA Tegra194

e required in the BPMP driver to support the new channel layout in Tegra194. The series has been tested on Tegra186 (Jetson TX2) and Tegra194 (P2972). Cheers, Mikko Mikko Perttunen (7): firmware: tegra: Simplify channel management soc/tegra: Add Tegra194 SoC configuration option soc/tegra: pmc: Ad

[PATCH v2 4/7] dt-bindings: tegra: Add missing chips and NVIDIA boards

Add compatibility strings for supported but undocumented Tegra chips (Tegra114/124/132/210/186/194) and reference boards. Signed-off-by: Mikko Perttunen --- Notes: v2: - add patch Documentation/devicetree/bindings/arm/tegra.txt | 16 1 file changed, 16 insertions

[PATCH v2 7/7] arm64: tegra: Add device tree for the Tegra194 P2972-0000 board

Add device tree files for the Tegra194 P2972- development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/Makefile| 1 + arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248

[PATCH v2 3/7] soc/tegra: pmc: Add Tegra194 compatibility string

The Tegra194 PMC is mostly compatible with Tegra186, including in all currently supported features. As such, add a new compatibility string but point to the existing Tegra186 SoC data for now. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/soc/tegra/pmc.c | 1 +

[PATCH v2 3/7] soc/tegra: pmc: Add Tegra194 compatibility string

The Tegra194 PMC is mostly compatible with Tegra186, including in all currently supported features. As such, add a new compatibility string but point to the existing Tegra186 SoC data for now. Signed-off-by: Mikko Perttunen --- drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff

[PATCH v2 2/7] soc/tegra: Add Tegra194 SoC configuration option

Add the configuration option to enable support for the Tegra194 system-on-chip, and enable it by default in the arm64 defconfig. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/configs/defconfig | 1 + drivers/soc/tegra/Kconfig| 10 ++ 2 files chang

[PATCH v2 2/7] soc/tegra: Add Tegra194 SoC configuration option

Add the configuration option to enable support for the Tegra194 system-on-chip, and enable it by default in the arm64 defconfig. Signed-off-by: Mikko Perttunen --- arch/arm64/configs/defconfig | 1 + drivers/soc/tegra/Kconfig| 10 ++ 2 files changed, 11 insertions(+) diff --git

Re: [PATCH] firmware: tegra: adjust tested variable

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 01/27/2018 04:28 PM, Julia Lawall wrote: Check the variable that was most recently initialized. The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // @@ expression x, y, f, g, e, m; statement S1

Re: [PATCH] firmware: tegra: adjust tested variable

Reviewed-by: Mikko Perttunen On 01/27/2018 04:28 PM, Julia Lawall wrote: Check the variable that was most recently initialized. The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // @@ expression x, y, f, g, e, m; statement S1,S2,S3,S4; @@ x = f

Re: [PATCH-next] drm/tegra: gem: Use PTR_ERR_OR_ZERO

This nas been NAK'd before as harder to read than the current way. Thanks, Mikko On 01/23/2018 10:29 PM, Christopher Díaz Riveros wrote: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR This issue was detected by using the Coccinelle software. Signed-off-by: Christopher Díaz Riveros

Re: [PATCH-next] drm/tegra: gem: Use PTR_ERR_OR_ZERO

This nas been NAK'd before as harder to read than the current way. Thanks, Mikko On 01/23/2018 10:29 PM, Christopher Díaz Riveros wrote: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR This issue was detected by using the Coccinelle software. Signed-off-by: Christopher Díaz Riveros

Re: [Nouveau] [RFC 0/4] Implement full clockgating for Kepler1 and 2

On 01/16/2018 12:06 AM, Lyude Paul wrote: It's here! After a lot of investigation, rewrites, and traces, I present the patch series to implement all known levels of clockgating for Kepler1 and Kepler2 GPUs. Starting with Fermi GPUs (this is probably present on earlier GPUs as well, but with a

Re: [Nouveau] [RFC 0/4] Implement full clockgating for Kepler1 and 2

On 01/16/2018 12:06 AM, Lyude Paul wrote: It's here! After a lot of investigation, rewrites, and traces, I present the patch series to implement all known levels of clockgating for Kepler1 and Kepler2 GPUs. Starting with Fermi GPUs (this is probably present on earlier GPUs as well, but with a

Re: [PATCH 5/6] arm64: tegra: Add Tegra194 chip device tree

On 11.01.2018 23:56, Rob Herring wrote: On Mon, Jan 08, 2018 at 06:54:37AM +0200, Mikko Perttunen wrote: Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to bo

Re: [PATCH 5/6] arm64: tegra: Add Tegra194 chip device tree

On 11.01.2018 23:56, Rob Herring wrote: On Mon, Jan 08, 2018 at 06:54:37AM +0200, Mikko Perttunen wrote: Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to bo

[PATCH 0/6] Initial support for NVIDIA Tegra194

e required in the BPMP driver to support the new channel layout in Tegra194. The series has been tested on Tegra186 (Jetson TX2) and Tegra194 (P2972). Cheers, Mikko Mikko Perttunen (6): firmware: tegra: Simplify channel management soc/tegra: Add Tegra194 SoC configuration option soc/tegra: pmc: Ad

[PATCH 0/6] Initial support for NVIDIA Tegra194

e required in the BPMP driver to support the new channel layout in Tegra194. The series has been tested on Tegra186 (Jetson TX2) and Tegra194 (P2972). Cheers, Mikko Mikko Perttunen (6): firmware: tegra: Simplify channel management soc/tegra: Add Tegra194 SoC configuration option soc/tegra: pmc: Ad

[PATCH 4/6] dt-bindings: tegra: Add documentation for nvidia,tegra194-pmc

The Tegra194 power management controller has one additional register aperture to be specified in the device tree node. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++ 1 file changed, 2 insertions(+)

[PATCH 4/6] dt-bindings: tegra: Add documentation for nvidia,tegra194-pmc

The Tegra194 power management controller has one additional register aperture to be specified in the device tree node. Signed-off-by: Mikko Perttunen --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation

[PATCH 3/6] soc/tegra: pmc: Add Tegra194 compatibility string

The Tegra194 PMC is mostly compatible with Tegra186, including in all currently supported features. As such, add a new compatibility string but point to the existing Tegra186 SoC data for now. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/soc/tegra/pmc.c | 1 +

[PATCH 3/6] soc/tegra: pmc: Add Tegra194 compatibility string

The Tegra194 PMC is mostly compatible with Tegra186, including in all currently supported features. As such, add a new compatibility string but point to the existing Tegra186 SoC data for now. Signed-off-by: Mikko Perttunen --- drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff

[PATCH 6/6] arm64: tegra: Add device tree for the Tegra194 P2972-0000 board

Add device tree files for the Tegra194 P2972- development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/Makefile| 1 + arch/arm64/boot/dts/nvidia/te

[PATCH 6/6] arm64: tegra: Add device tree for the Tegra194 P2972-0000 board

Add device tree files for the Tegra194 P2972- development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/Makefile| 1 + arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 246

[PATCH 2/6] soc/tegra: Add Tegra194 SoC configuration option

Add the configuration option to enable support for the Tegra194 system-on-chip, and enable it by default in the arm64 defconfig. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/configs/defconfig | 1 + drivers/soc/tegra/Kconfig| 10 ++ 2 files chang

[PATCH 1/6] firmware: tegra: Simplify channel management

channel are supported, and channels are not required to be placed contiguously in memory. The same configuration also works on T186 so we end up with less code. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/firmware/tegra/bpmp.c

[PATCH 2/6] soc/tegra: Add Tegra194 SoC configuration option

Add the configuration option to enable support for the Tegra194 system-on-chip, and enable it by default in the arm64 defconfig. Signed-off-by: Mikko Perttunen --- arch/arm64/configs/defconfig | 1 + drivers/soc/tegra/Kconfig| 10 ++ 2 files changed, 11 insertions(+) diff --git

[PATCH 1/6] firmware: tegra: Simplify channel management

channel are supported, and channels are not required to be placed contiguously in memory. The same configuration also works on T186 so we end up with less code. Signed-off-by: Mikko Perttunen --- drivers/firmware/tegra/bpmp.c | 142 +++--- include/soc/tegra

[PATCH 5/6] arm64: tegra: Add Tegra194 chip device tree

Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UART console. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvid

[PATCH 5/6] arm64: tegra: Add Tegra194 chip device tree

Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UART console. Signed-off-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/tegra194.dt

Re: [PATCH 01/33] clk_ops: change round_rate() to return unsigned long

FWIW, we had this problem some years ago with the Tegra CPU clock - then it was determined that a simpler solution was to have the determine_rate callback support unsigned long rates - so clock drivers that need to return rates higher than 2^31 can instead implement the determine_rate

Re: [PATCH 01/33] clk_ops: change round_rate() to return unsigned long

FWIW, we had this problem some years ago with the Tegra CPU clock - then it was determined that a simpler solution was to have the determine_rate callback support unsigned long rates - so clock drivers that need to return rates higher than 2^31 can instead implement the determine_rate

Re: [PATCH 04/10] gpu: host1x: Lock classes during job submission

On 07.11.2017 23:23, Dmitry Osipenko wrote: On 07.11.2017 15:28, Mikko Perttunen wrote: On 05.11.2017 18:46, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: ... +static int mlock_id_for_class(unsigned int class) +{ +#if HOST1X_HW >= 6 +switch (class) +{ +c

Re: [PATCH 04/10] gpu: host1x: Lock classes during job submission

On 07.11.2017 23:23, Dmitry Osipenko wrote: On 07.11.2017 15:28, Mikko Perttunen wrote: On 05.11.2017 18:46, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: ... +static int mlock_id_for_class(unsigned int class) +{ +#if HOST1X_HW >= 6 +switch (class) +{ +c

Re: [PATCH] staging: nvec: Fix usleep_range is preferred over udelay

On 11/29/2017 06:00 PM, Joshua Abraham wrote: Signed-off-by: Joshua Abraham This patch fixes the issue: CHECK: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt --- drivers/staging/nvec/nvec.c | 2 +- 1 file changed, 1 insertion(+),

Re: [PATCH] staging: nvec: Fix usleep_range is preferred over udelay

On 11/29/2017 06:00 PM, Joshua Abraham wrote: Signed-off-by: Joshua Abraham This patch fixes the issue: CHECK: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt --- drivers/staging/nvec/nvec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 29.11.2017 14:18, Dmitry Osipenko wrote: On 29.11.2017 12:10, Mikko Perttunen wrote: On 12.11.2017 13:23, Dmitry Osipenko wrote: On 11.11.2017 00:15, Dmitry Osipenko wrote: On 07.11.2017 18:29, Dmitry Osipenko wrote: On 07.11.2017 16:11, Mikko Perttunen wrote: On 05.11.2017 19:14, Dmitry

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 29.11.2017 14:18, Dmitry Osipenko wrote: On 29.11.2017 12:10, Mikko Perttunen wrote: On 12.11.2017 13:23, Dmitry Osipenko wrote: On 11.11.2017 00:15, Dmitry Osipenko wrote: On 07.11.2017 18:29, Dmitry Osipenko wrote: On 07.11.2017 16:11, Mikko Perttunen wrote: On 05.11.2017 19:14, Dmitry

Re: [PATCH] drm/tegra: gem: Use PTR_ERR_OR_ZERO()

On 29.11.2017 00:18, Vasyl Gomonovych wrote: Fix ptr_ret.cocci warnings: drivers/gpu/drm/tegra/gem.c:420:1-3: WARNING: PTR_ERR_OR_ZERO can be used Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Generated by: scripts/coccinelle/api/ptr_ret.cocci Signed-off-by: Vasyl Gomonovych

Re: [PATCH] drm/tegra: gem: Use PTR_ERR_OR_ZERO()

On 29.11.2017 00:18, Vasyl Gomonovych wrote: Fix ptr_ret.cocci warnings: drivers/gpu/drm/tegra/gem.c:420:1-3: WARNING: PTR_ERR_OR_ZERO can be used Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Generated by: scripts/coccinelle/api/ptr_ret.cocci Signed-off-by: Vasyl Gomonovych ---

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 12.11.2017 13:23, Dmitry Osipenko wrote: On 11.11.2017 00:15, Dmitry Osipenko wrote: On 07.11.2017 18:29, Dmitry Osipenko wrote: On 07.11.2017 16:11, Mikko Perttunen wrote: On 05.11.2017 19:14, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: Add an option

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 12.11.2017 13:23, Dmitry Osipenko wrote: On 11.11.2017 00:15, Dmitry Osipenko wrote: On 07.11.2017 18:29, Dmitry Osipenko wrote: On 07.11.2017 16:11, Mikko Perttunen wrote: On 05.11.2017 19:14, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: Add an option

Re: [PATCH 06/10] drm/tegra: Deliver job completion callback to client

On 16.11.2017 18:40, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: To allow client drivers to free resources when jobs have completed, deliver job completion callbacks to them. This requires adding reference counting to context objects, as job completion can happen after

Re: [PATCH 06/10] drm/tegra: Deliver job completion callback to client

On 16.11.2017 18:40, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: To allow client drivers to free resources when jobs have completed, deliver job completion callbacks to them. This requires adding reference counting to context objects, as job completion can happen after

Re: [tegra186]: emmc resume failing after booting from snapshot image

The upstream kernel currently has no core rail suspend support (LP0/SC7) on Tegras - in general the downstream kernel (used e.g. in L4T) is the reference that has the most functionality on Tegra. IIRC the MMC subsystem and Tegra MMC driver between upstream and downstream are currently quite

Re: [tegra186]: emmc resume failing after booting from snapshot image

The upstream kernel currently has no core rail suspend support (LP0/SC7) on Tegras - in general the downstream kernel (used e.g. in L4T) is the reference that has the most functionality on Tegra. IIRC the MMC subsystem and Tegra MMC driver between upstream and downstream are currently quite

[PATCH 1/2] arm64: defconfig: Enable CONFIG_ARM_TEGRA186_CPUFREQ

Enable Tegra186 CPU frequency scaling support by default. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6356c6da34ea..427110

[PATCH 2/2] arm64: defconfig: Enable CONFIG_TEGRA_BPMP_THERMAL

Enable Tegra BPMP thermal sensor support by default, built as a module. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 427110

[PATCH 1/2] arm64: defconfig: Enable CONFIG_ARM_TEGRA186_CPUFREQ

Enable Tegra186 CPU frequency scaling support by default. Signed-off-by: Mikko Perttunen --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6356c6da34ea..42711031a72d 100644 --- a/arch/arm64

[PATCH 2/2] arm64: defconfig: Enable CONFIG_TEGRA_BPMP_THERMAL

Enable Tegra BPMP thermal sensor support by default, built as a module. Signed-off-by: Mikko Perttunen --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 42711031a72d..d0f05da8baf9 100644

Re: [PATCH] soc/tegra: pmc: fix child-node lookup

as of_find_node_by_name() drops a reference to its first argument. Fixes: 3568df3d31d6 ("soc: tegra: Add thermal reset (thermtrip) support to PMC") Cc: stable <sta...@vger.kernel.org> # 4.0 Cc: Mikko Perttunen <mperttu...@nvidia.com> Signed-off-by: Johan Hovold <jo...@kernel.org>

Re: [PATCH] soc/tegra: pmc: fix child-node lookup

as of_find_node_by_name() drops a reference to its first argument. Fixes: 3568df3d31d6 ("soc: tegra: Add thermal reset (thermtrip) support to PMC") Cc: stable # 4.0 Cc: Mikko Perttunen Signed-off-by: Johan Hovold --- drivers/soc/tegra/pmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletio

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 05.11.2017 19:14, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: Add an option to host1x_channel_request to interruptibly wait for a free channel. This allows IOCTLs that acquire a channel to block the userspace. Wouldn't it be more optimal to request channel and block

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 05.11.2017 19:14, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: Add an option to host1x_channel_request to interruptibly wait for a free channel. This allows IOCTLs that acquire a channel to block the userspace. Wouldn't it be more optimal to request channel and block

Re: [PATCH 08/10] drm/tegra: Implement dynamic channel allocation model

On 05.11.2017 19:43, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: In the traditional channel allocation model, a single hardware channel was allocated for each client. This is simple from an implementation perspective but prevents use of hardware scheduling. This patch

Re: [PATCH 08/10] drm/tegra: Implement dynamic channel allocation model

On 05.11.2017 19:43, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: In the traditional channel allocation model, a single hardware channel was allocated for each client. This is simple from an implementation perspective but prevents use of hardware scheduling. This patch

Re: [PATCH 04/10] gpu: host1x: Lock classes during job submission

On 05.11.2017 18:46, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: >> ... +static int mlock_id_for_class(unsigned int class) +{ +#if HOST1X_HW >= 6 + switch (class) + { + case HOST1X_CLASS_HOST1X: + return 0; + case HOST1X_

Re: [PATCH 04/10] gpu: host1x: Lock classes during job submission

On 05.11.2017 18:46, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: >> ... +static int mlock_id_for_class(unsigned int class) +{ +#if HOST1X_HW >= 6 + switch (class) + { + case HOST1X_CLASS_HOST1X: + return 0; + case HOST1X_

[PATCH 06/10] drm/tegra: Deliver job completion callback to client

for contexts. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 27 --- drivers/gpu/drm/tegra/drm.h | 4 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra

[PATCH 01/10] gpu: host1x: Parameterize channel aperture size

The size of a single channel's aperture is different on Tegra186 vs. previous chips. Parameterize the value using a new define in the register definition headers. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/hw/channel_hw.c | 3 +-- drivers/gpu/hos

[PATCH 06/10] drm/tegra: Deliver job completion callback to client

for contexts. Signed-off-by: Mikko Perttunen --- drivers/gpu/drm/tegra/drm.c | 27 --- drivers/gpu/drm/tegra/drm.h | 4 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 2cdd054520bf

[PATCH 01/10] gpu: host1x: Parameterize channel aperture size

The size of a single channel's aperture is different on Tegra186 vs. previous chips. Parameterize the value using a new define in the register definition headers. Signed-off-by: Mikko Perttunen --- drivers/gpu/host1x/hw/channel_hw.c | 3 +-- drivers/gpu/host1x/hw/hw_host1x01_channel.h

[PATCH 05/10] gpu: host1x: Add job done callback

Allow job submitters to set a callback to be called when the job has completed. The jobs are stored and the callbacks called outside the CDMA lock area to allow the callbacks to do CDMA-requiring operations like freeing channels. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- d

[PATCH 05/10] gpu: host1x: Add job done callback

Allow job submitters to set a callback to be called when the job has completed. The jobs are stored and the callbacks called outside the CDMA lock area to allow the callbacks to do CDMA-requiring operations like freeing channels. Signed-off-by: Mikko Perttunen --- drivers/gpu/host1x/cdma.c | 44

[PATCH 04/10] gpu: host1x: Lock classes during job submission

. This patch implements locking on all platforms from Tegra20 to Tegra186. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/cdma.c | 1 + drivers/gpu/host1x/cdma.h | 1 + drivers/gpu/host1x/hw/cdma_hw.c

[PATCH 04/10] gpu: host1x: Lock classes during job submission

. This patch implements locking on all platforms from Tegra20 to Tegra186. Signed-off-by: Mikko Perttunen --- drivers/gpu/host1x/cdma.c | 1 + drivers/gpu/host1x/cdma.h | 1 + drivers/gpu/host1x/hw/cdma_hw.c| 122

[PATCH 07/10] drm/tegra: Make syncpoints be per-context

As a preparation for each context potentially being able to have a separate hardware channel, and thus requiring a separate syncpoint, move syncpoints to be stored inside each context instead of global client data. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm

[PATCH 07/10] drm/tegra: Make syncpoints be per-context

As a preparation for each context potentially being able to have a separate hardware channel, and thus requiring a separate syncpoint, move syncpoints to be stored inside each context instead of global client data. Signed-off-by: Mikko Perttunen --- drivers/gpu/drm/tegra/drm.c | 8

[PATCH 09/10] drm/tegra: Boot VIC in runtime resume

This ensures that there are no concurrency issues when multiple users are trying to use VIC concurrently, and also simplifies the code slightly. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/vic.c | 47 +++--

[PATCH 08/10] drm/tegra: Implement dynamic channel allocation model

, this patch only adapts VIC to the new model. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 46 ++ drivers/gpu/drm/tegra/drm.h | 7 +++- drivers/gpu/drm/tegra/vic.c | 79 +++-- 3 files chang

[PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

Add an option to host1x_channel_request to interruptibly wait for a free channel. This allows IOCTLs that acquire a channel to block the userspace. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 9 + drivers/gpu/drm/tegra/gr2d.

[PATCH 09/10] drm/tegra: Boot VIC in runtime resume

This ensures that there are no concurrency issues when multiple users are trying to use VIC concurrently, and also simplifies the code slightly. Signed-off-by: Mikko Perttunen --- drivers/gpu/drm/tegra/vic.c | 47 +++-- 1 file changed, 20 insertions

[PATCH 08/10] drm/tegra: Implement dynamic channel allocation model

, this patch only adapts VIC to the new model. Signed-off-by: Mikko Perttunen --- drivers/gpu/drm/tegra/drm.c | 46 ++ drivers/gpu/drm/tegra/drm.h | 7 +++- drivers/gpu/drm/tegra/vic.c | 79 +++-- 3 files changed, 92 insertions(+), 40

[PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

Add an option to host1x_channel_request to interruptibly wait for a free channel. This allows IOCTLs that acquire a channel to block the userspace. Signed-off-by: Mikko Perttunen --- drivers/gpu/drm/tegra/drm.c | 9 + drivers/gpu/drm/tegra/gr2d.c | 6 +++--- drivers/gpu/drm/tegra

[PATCH 02/10] gpu: host1x: Print MLOCK state in debug dumps on T186

Add support for dumping current MLOCK state in debug dumps also on T186, now that MLOCKs are used by the driver. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/hw/debug_hw_1x06.c | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff

[PATCH 02/10] gpu: host1x: Print MLOCK state in debug dumps on T186

Add support for dumping current MLOCK state in debug dumps also on T186, now that MLOCKs are used by the driver. Signed-off-by: Mikko Perttunen --- drivers/gpu/host1x/hw/debug_hw_1x06.c | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/host1x/hw

[PATCH 03/10] gpu: host1x: Add lock around channel allocation

With the new channel allocation model, multiple threads can be allocating channels simultaneously. Therefore we need to add a lock around the code. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/channel.c | 7 +++ drivers/gpu/host1x/channel.h | 2 ++ 2

[PATCH 00/10] Dynamic Host1x channel allocation

sted using the host1x_test test suite, and also by running the performance test of host1x_test in parallel. Thanks, Mikko Mikko Perttunen (10): gpu: host1x: Parameterize channel aperture size gpu: host1x: Print MLOCK state in debug dumps on T186 gpu: host1x: Add lock around channel allocation g

[PATCH 03/10] gpu: host1x: Add lock around channel allocation

With the new channel allocation model, multiple threads can be allocating channels simultaneously. Therefore we need to add a lock around the code. Signed-off-by: Mikko Perttunen --- drivers/gpu/host1x/channel.c | 7 +++ drivers/gpu/host1x/channel.h | 2 ++ 2 files changed, 9 insertions

[PATCH 00/10] Dynamic Host1x channel allocation

sted using the host1x_test test suite, and also by running the performance test of host1x_test in parallel. Thanks, Mikko Mikko Perttunen (10): gpu: host1x: Parameterize channel aperture size gpu: host1x: Print MLOCK state in debug dumps on T186 gpu: host1x: Add lock around channel allocation g

Re: [PATCH v3 1/6] gpu: host1x: Enable Tegra186 syncpoint protection

On 09/30/2017 05:41 AM, Dmitry Osipenko wrote: On 28.09.2017 15:50, Mikko Perttunen wrote: .. diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c index 8447a56c41ca..b929d7f1e291 100644 --- a/drivers/gpu/host1x/hw/channel_hw.c +++ b/drivers/gpu/host1x/hw

Re: [PATCH v3 1/6] gpu: host1x: Enable Tegra186 syncpoint protection

On 09/30/2017 05:41 AM, Dmitry Osipenko wrote: On 28.09.2017 15:50, Mikko Perttunen wrote: .. diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c index 8447a56c41ca..b929d7f1e291 100644 --- a/drivers/gpu/host1x/hw/channel_hw.c +++ b/drivers/gpu/host1x/hw

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