Re: [PATCH 4/7] net: stmmac: Parse FIFO sizes from feature registers

fosz = priv->dma_cap.rx_fifo_size; + if (priv->plat->force_thresh_dma_mode) priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com>

Re: [PATCH 4/7] net: stmmac: Parse FIFO sizes from feature registers

gt;plat->force_thresh_dma_mode) priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { Reviewed-by: Mikko Perttunen

Re: [PATCH 6/7] clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:14, Peter De Schrijver wrote: Return the actually achieved rate in cfg->output_rate rather than just the requested rate. This is important to make clk_round_rate return the correct result. Signed-off-by: Peter De

Re: [PATCH 6/7] clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation

Reviewed-by: Mikko Perttunen On 22.02.2017 17:14, Peter De Schrijver wrote: Return the actually achieved rate in cfg->output_rate rather than just the requested rate. This is important to make clk_round_rate return the correct result. Signed-off-by: Peter De Schrijver --- drivers/clk/te

Re: [PATCH 7/7] clk: tegra: fix type for m field

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:14, Peter De Schrijver wrote: When used as part of fractional ndiv calculations, the current range is not enough because the denominator of the fraction is multiplied with m. Signed-off-by: Peter De Schrijver <

Re: [PATCH 7/7] clk: tegra: fix type for m field

Reviewed-by: Mikko Perttunen On 22.02.2017 17:14, Peter De Schrijver wrote: When used as part of fractional ndiv calculations, the current range is not enough because the denominator of the fraction is multiplied with m. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk.h | 2

Re: [PATCH 5/7] clk: tegra: don't warn for PLL defaults unnecessarily

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:14, Peter De Schrijver wrote: If the PLL is on, only warn if the defaults are not yet set. Otherwise be silent. Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- drivers/clk/tegra/clk-teg

Re: [PATCH 5/7] clk: tegra: don't warn for PLL defaults unnecessarily

Reviewed-by: Mikko Perttunen On 22.02.2017 17:14, Peter De Schrijver wrote: If the PLL is on, only warn if the defaults are not yet set. Otherwise be silent. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra210.c | 18 -- 1 file changed, 12 insertions(+), 6

Re: [PATCH 3/7] clk: tegra: correct afi parent

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:13, Peter De Schrijver wrote: The parent for afi is actually mselect, not clk_m. Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 ins

Re: [PATCH 3/7] clk: tegra: correct afi parent

Reviewed-by: Mikko Perttunen On 22.02.2017 17:13, Peter De Schrijver wrote: The parent for afi is actually mselect, not clk_m. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk

Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:13, Peter De Schrijver wrote: Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- drivers/clk/tegra/clk-tegra210.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/clk/tegra/clk-

Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock

Reviewed-by: Mikko Perttunen On 22.02.2017 17:13, Peter De Schrijver wrote: Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra210.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 7bda8ba

Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock

Whoops, that is, after a commit message is added. On 23.02.2017 10:17, Mikko Perttunen wrote: Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:13, Peter De Schrijver wrote: Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- drivers/clk/tegra/cl

Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock

Whoops, that is, after a commit message is added. On 23.02.2017 10:17, Mikko Perttunen wrote: Reviewed-by: Mikko Perttunen On 22.02.2017 17:13, Peter De Schrijver wrote: Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra210.c | 5 - 1 file changed, 5 deletions(-) diff

Re: [PATCH 2/7] clk: tegra: fix isp clock modelling

The TRM shows a CLK_SOURCE_ISPB register, but after some discussion, it seems like that is a documentation generation bug, so this should be correct. Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:13, Peter De Schrijver wrote: The 2 isp clocks (ispa and ispb)

Re: [PATCH 2/7] clk: tegra: fix isp clock modelling

The TRM shows a CLK_SOURCE_ISPB register, but after some discussion, it seems like that is a documentation generation bug, so this should be correct. Reviewed-by: Mikko Perttunen On 22.02.2017 17:13, Peter De Schrijver wrote: The 2 isp clocks (ispa and ispb) share a mux/divider control. So

Re: [PATCH 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 02/22/2017 05:13 PM, Peter De Schrijver wrote: pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1 to the set of clocks defined for Te

Re: [PATCH 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1

Reviewed-by: Mikko Perttunen On 02/22/2017 05:13 PM, Peter De Schrijver wrote: pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1 to the set of clocks defined for Tegra210. Signed-off-by: Peter De

Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock

Missing commit message Cheers, Mikko. On 02/22/2017 05:13 PM, Peter De Schrijver wrote: Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra210.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c

Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock

Missing commit message Cheers, Mikko. On 02/22/2017 05:13 PM, Peter De Schrijver wrote: Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra210.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index

Re: [PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

On 07/25/16 18:23, Mikko Perttunen wrote: On 07/25/16 14:05, Antonio Ospite wrote: You can also find out the length of the raw output report with trial and error, start with a line like this: $ sudo hexdump -v -e '49/1 "%02x " "\n"' /dev/hidraw0 and increase/decrease

Re: [PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

On 07/25/16 18:23, Mikko Perttunen wrote: On 07/25/16 14:05, Antonio Ospite wrote: You can also find out the length of the raw output report with trial and error, start with a line like this: $ sudo hexdump -v -e '49/1 "%02x " "\n"' /dev/hidraw0 and increase/decrease

Re: [PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

On 07/25/16 14:05, Antonio Ospite wrote: On Mon, 25 Jul 2016 11:14:04 +0200 Benjamin Tissoires wrote: On Jul 21 2016 or thereabouts, Antonio Ospite wrote: [...] It would be interesting to understand why some (supposedly) compatible devices break, maybe they

Re: [PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

On 07/25/16 14:05, Antonio Ospite wrote: On Mon, 25 Jul 2016 11:14:04 +0200 Benjamin Tissoires wrote: On Jul 21 2016 or thereabouts, Antonio Ospite wrote: [...] It would be interesting to understand why some (supposedly) compatible devices break, maybe they rely on the fact that the PS3

Re: [PATCH v2] HID: sony: disable descriptor fixup for FutureMax Dance Mat

Reviewed-by: Benjamin Tissoires Acked-by: Antonio Ospite Thanks! Mikko

Re: [PATCH v2] HID: sony: disable descriptor fixup for FutureMax Dance Mat

Reviewed-by: Benjamin Tissoires Acked-by: Antonio Ospite Thanks! Mikko

[PATCH v2] HID: sony: disable descriptor fixup for FutureMax Dance Mat

From: Mikko Perttunen <mperttu...@nvidia.com> The FutureMax Dance Mat claims to be a SixAxis controller but breaks if descriptor fixups are applied. Detect the device using its USB product string and disable fixups when it is detected. Signed-off-by: Mikko Perttunen <mperttu...@n

[PATCH v2] HID: sony: disable descriptor fixup for FutureMax Dance Mat

From: Mikko Perttunen The FutureMax Dance Mat claims to be a SixAxis controller but breaks if descriptor fixups are applied. Detect the device using its USB product string and disable fixups when it is detected. Signed-off-by: Mikko Perttunen --- v2: don't use usb device properties drivers

Re: [PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

On 07/18/16 17:28, Benjamin Tissoires wrote: On Jul 17 2016 or thereabouts, Mikko Perttunen wrote: From: Mikko Perttunen <mperttu...@nvidia.com> ... #include #include #include +#include + +#include "usbhid/usbhid.h" I spent a lot of effort 2 years ago to remove the usb

Re: [PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

On 07/18/16 17:28, Benjamin Tissoires wrote: On Jul 17 2016 or thereabouts, Mikko Perttunen wrote: From: Mikko Perttunen ... #include #include #include +#include + +#include "usbhid/usbhid.h" I spent a lot of effort 2 years ago to remove the usb dependency, I'd prefer

[PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

From: Mikko Perttunen <mperttu...@nvidia.com> The FutureMax Dance Mat claims to be a SixAxis controller but breaks if descriptor fixups are applied. Detect the device using its USB product string and disable fixups when it is detected. Signed-off-by: Mikko Perttunen <mperttu...@n

[PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

From: Mikko Perttunen The FutureMax Dance Mat claims to be a SixAxis controller but breaks if descriptor fixups are applied. Detect the device using its USB product string and disable fixups when it is detected. Signed-off-by: Mikko Perttunen --- drivers/hid/hid-sony.c | 15 ++- 1

Re: [RFC PATCH] dt: Tegra XUSB padctl: per-lane PHYs and USB lane map

On 10/20/2015 06:56 PM, Stephen Warren wrote: ... In drivers/pci/host/pci-tegra.c tegra_pcie_get_resources() I see a call to devm_phy_optional_get(). The SATA driver doesn't seem to do anything with phys at the moment, although tegra124.dtsi does put phy-related properties into the SATA DT

Re: [RFC PATCH] dt: Tegra XUSB padctl: per-lane PHYs and USB lane map

On 10/20/2015 06:56 PM, Stephen Warren wrote: ... In drivers/pci/host/pci-tegra.c tegra_pcie_get_resources() I see a call to devm_phy_optional_get(). The SATA driver doesn't seem to do anything with phys at the moment, although tegra124.dtsi does put phy-related properties into the SATA DT

[PATCH] clk: tegra: Unlock top rates for Tegra124 DFLL clock

The new determine_rate prototype allows for clock rates exceeding 2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate instead of round_rate and unlock the top rates supported by the Tegra124. Signed-off-by: Mikko Perttunen --- drivers/clk/tegra/clk-dfll.c | 15

[PATCH] clk: tegra: Unlock top rates for Tegra124 DFLL clock

The new determine_rate prototype allows for clock rates exceeding 2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate instead of round_rate and unlock the top rates supported by the Tegra124. Signed-off-by: Mikko Perttunen <mikko.perttu...@kapsi.fi> --- drivers/clk/tegra/clk-

[PATCH] regulator: max8973: Set VSEL regmap ops if DVS GPIO is not set

of the *hardware_vsel* regulator APIs. Signed-off-by: Mikko Perttunen --- This was just compile-tested as I don't have a board with this regulator. drivers/regulator/max8973-regulator.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/regulator/max8973-regulator.c b/drivers/regulator/max8973

[PATCH] regulator: max8973: Set VSEL regmap ops if DVS GPIO is not set

of the *hardware_vsel* regulator APIs. Signed-off-by: Mikko Perttunen mperttu...@nvidia.com --- This was just compile-tested as I don't have a board with this regulator. drivers/regulator/max8973-regulator.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/regulator/max8973-regulator.c b

Re: [PATCH 3/4] drm/tegra: Add VIC support

On 05/21/2015 06:10 PM, Arto Merilainen wrote: ... + +vic->rst = devm_reset_control_get(dev, "vic03"); I might prefer just "vic" as the clock/reset name. The name is often used as a sort of "role" for the clock/reset for the device, not necessarily the raw name of the "correct"

Re: [PATCH 3/4] drm/tegra: Add VIC support

Hi, very good patch! Here are a few small comments. Aside those, you should also add a section to Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt in a separate patch. Thanks, Mikko. On 05/21/2015 04:20 PM, Arto Merilainen wrote: > This patch adds support for Video Image

Re: [PATCH 3/4] drm/tegra: Add VIC support

Hi, very good patch! Here are a few small comments. Aside those, you should also add a section to Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt in a separate patch. Thanks, Mikko. On 05/21/2015 04:20 PM, Arto Merilainen wrote: This patch adds support for Video Image

Re: [PATCH 3/4] drm/tegra: Add VIC support

On 05/21/2015 06:10 PM, Arto Merilainen wrote: ... + +vic-rst = devm_reset_control_get(dev, vic03); I might prefer just vic as the clock/reset name. The name is often used as a sort of role for the clock/reset for the device, not necessarily the raw name of the correct clock/reset. I

Re: [PATCH 01/15] thermal: consistently use int for temperatures

On 05/20/15 11:34, Sascha Hauer wrote: On Wed, May 20, 2015 at 10:12:44AM +0300, Mikko Perttunen wrote: On 05/13/15 11:52, Sascha Hauer wrote: The thermal code uses int, long and unsigned long for temperatures in different places. Using an unsigned type limits the thermal framework to positive

Re: [PATCH 06/15] thermal: inline only once used function

fore but aren't now. But I don't know why that would matter. Reviewed-by: Mikko Perttunen -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/

Re: [PATCH 05/15] thermal: Add comment explaining test for critical temperature

; crit_temp) *temp = tz->emul_temperature; } Reviewed-by: Mikko Perttunen -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordo

Re: [PATCH 01/15] thermal: consistently use int for temperatures

On 05/13/15 11:52, Sascha Hauer wrote: The thermal code uses int, long and unsigned long for temperatures in different places. Using an unsigned type limits the thermal framework to positive temperatures without need. 'long' is 64bit on several architectures which is not needed. Consistently use

[PATCH v11 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

ile. Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette --- drivers/clk/tegra/clk.c | 39 +++ drivers/clk/tegra/clk.h | 3 +++ 2 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 41cd

Re: [PATCH 05/15] thermal: Add comment explaining test for critical temperature

crit_temp) *temp = tz-emul_temperature; } Reviewed-by: Mikko Perttunen mperttu...@nvidia.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http

Re: [PATCH 06/15] thermal: inline only once used function

. But I don't know why that would matter. Reviewed-by: Mikko Perttunen mperttu...@nvidia.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please

Re: [PATCH 01/15] thermal: consistently use int for temperatures

On 05/13/15 11:52, Sascha Hauer wrote: The thermal code uses int, long and unsigned long for temperatures in different places. Using an unsigned type limits the thermal framework to positive temperatures without need. 'long' is 64bit on several architectures which is not needed. Consistently use

[PATCH v11 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

. Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk.c | 39 +++ drivers/clk/tegra/clk.h | 3 +++ 2 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra/clk.c

Re: [PATCH 01/15] thermal: consistently use int for temperatures

On 05/20/15 11:34, Sascha Hauer wrote: On Wed, May 20, 2015 at 10:12:44AM +0300, Mikko Perttunen wrote: On 05/13/15 11:52, Sascha Hauer wrote: The thermal code uses int, long and unsigned long for temperatures in different places. Using an unsigned type limits the thermal framework to positive

Re: [PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

On 05/19/2015 05:59 PM, Thierry Reding wrote: On Tue, May 19, 2015 at 02:39:27PM +0300, Mikko Perttunen wrote: This patch allows SoC-specific CAR initialization routines to register their own reset_assert and reset_deassert callbacks with the common Tegra CAR code. If defined, the common code

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

On 05/19/15 16:58, Sascha Hauer wrote: On Mon, May 18, 2015 at 02:09:44PM +0200, Sascha Hauer wrote: Hi Mikko, On Mon, May 18, 2015 at 12:06:50PM +0300, Mikko Perttunen wrote: + for (i = 0; i < tz->trips; i++) { + int trip_low; + + tz->ops->get_

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

On 05/18/15 23:28, Brian Norris wrote: On Mon, May 18, 2015 at 10:13:46PM +0300, Mikko Perttunen wrote: On 05/18/2015 09:44 PM, Brian Norris wrote: On Mon, May 18, 2015 at 02:09:44PM +0200, Sascha Hauer wrote: On Mon, May 18, 2015 at 12:06:50PM +0300, Mikko Perttunen wrote: One interesting

Re: [PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

to Thierry for the idea. Mikko On 05/19/15 14:39, Mikko Perttunen wrote: This patch allows SoC-specific CAR initialization routines to register their own reset_assert and reset_deassert callbacks with the common Tegra CAR code. If defined, the common code will call these callbacks when a reset

[PATCH v10 06/17] clk: tegra: Add DFLL DVCO reset control for Tegra124

block will complete. Thanks to Aleksandr Frid for identifying this and saving hours of debugging time. Signed-off-by: Paul Walmsley [ttynkkynen: ported to tegra124 from tegra114] Signed-off-by: Tuomas Tynkkynen [mikko.perttunen: ported to special reset callback] Signed-off-by: Mikko Perttunen

[PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

ile. Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette --- drivers/clk/tegra/clk.c | 39 +++ drivers/clk/tegra/clk.h | 3 +++ 2 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 41cd

[PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

. Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk.c | 39 +++ drivers/clk/tegra/clk.h | 3 +++ 2 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra

[PATCH v10 06/17] clk: tegra: Add DFLL DVCO reset control for Tegra124

[mikko.perttunen: ported to special reset callback] Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk-tegra124.c | 68 include/dt-bindings/reset/tegra124-car.h | 12 ++ 2 files

Re: [PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

to Thierry for the idea. Mikko On 05/19/15 14:39, Mikko Perttunen wrote: This patch allows SoC-specific CAR initialization routines to register their own reset_assert and reset_deassert callbacks with the common Tegra CAR code. If defined, the common code will call these callbacks when a reset

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

On 05/18/15 23:28, Brian Norris wrote: On Mon, May 18, 2015 at 10:13:46PM +0300, Mikko Perttunen wrote: On 05/18/2015 09:44 PM, Brian Norris wrote: On Mon, May 18, 2015 at 02:09:44PM +0200, Sascha Hauer wrote: On Mon, May 18, 2015 at 12:06:50PM +0300, Mikko Perttunen wrote: One interesting

Re: [PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

On 05/19/2015 05:59 PM, Thierry Reding wrote: On Tue, May 19, 2015 at 02:39:27PM +0300, Mikko Perttunen wrote: This patch allows SoC-specific CAR initialization routines to register their own reset_assert and reset_deassert callbacks with the common Tegra CAR code. If defined, the common code

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

On 05/19/15 16:58, Sascha Hauer wrote: On Mon, May 18, 2015 at 02:09:44PM +0200, Sascha Hauer wrote: Hi Mikko, On Mon, May 18, 2015 at 12:06:50PM +0300, Mikko Perttunen wrote: + for (i = 0; i tz-trips; i++) { + int trip_low; + + tz-ops-get_trip_temp(tz, i

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

On 05/18/2015 09:44 PM, Brian Norris wrote: On Mon, May 18, 2015 at 02:09:44PM +0200, Sascha Hauer wrote: On Mon, May 18, 2015 at 12:06:50PM +0300, Mikko Perttunen wrote: One interesting thing I noticed was that at least the bang-bang governor only acts if the temperature is properly smaller

Re: [PATCH 12/15] thermal: of: implement .set_trips for device tree thermal zones

On 05/13/15 11:52, Sascha Hauer wrote: Signed-off-by: Sascha Hauer --- drivers/thermal/of-thermal.c | 12 include/linux/thermal.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c index bd3185e..f8dd847

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

e' > for the respective thermal zone. This will cause the trip points > to be updated again. > > If .set_trips is not implemented, the framework behaves as before. > > This patch is based on an earlier version from Mikko Perttunen > > > Signed-off

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

On 05/18/2015 09:44 PM, Brian Norris wrote: On Mon, May 18, 2015 at 02:09:44PM +0200, Sascha Hauer wrote: On Mon, May 18, 2015 at 12:06:50PM +0300, Mikko Perttunen wrote: One interesting thing I noticed was that at least the bang-bang governor only acts if the temperature is properly smaller

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

the trip points to be updated again. If .set_trips is not implemented, the framework behaves as before. This patch is based on an earlier version from Mikko Perttunen mikko.perttu...@kapsi.fi Signed-off-by: Sascha Hauer s.ha...@pengutronix.de --- drivers/thermal/thermal_core.c | 43

Re: [PATCH 12/15] thermal: of: implement .set_trips for device tree thermal zones

On 05/13/15 11:52, Sascha Hauer wrote: Signed-off-by: Sascha Hauer s.ha...@pengutronix.de --- drivers/thermal/of-thermal.c | 12 include/linux/thermal.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c

Re: [PATCH v2 1/2] clk: change clk_ops' ->round_rate() prototype

ested rate as a pointer so that it can be adjusted depending on hardware capabilities. Signed-off-by: Boris Brezillon Tested-by: Heiko Stuebner Tested-by: Mikko Perttunen Reviewed-by: Heiko Stuebner This patch is fairly invasive, and it probably doesn't even matter for most of these clock providers

Re: [PATCH v2 1/2] clk: change clk_ops' -round_rate() prototype

, and pass the requested rate as a pointer so that it can be adjusted depending on hardware capabilities. Signed-off-by: Boris Brezillon boris.brezil...@free-electrons.com Tested-by: Heiko Stuebner he...@sntech.de Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi Reviewed-by: Heiko Stuebner he

Re: [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

On 05/15/2015 05:09 AM, Viresh Kumar wrote: On 15 May 2015 at 01:45, Rafael J. Wysocki wrote: You need ACKs from Viresh for those two, then. He's officially responsible for ARM cpufreq drivers. I thought an Ack for 14th is enough :) For: 12/13/14. Acked-by: Viresh Kumar Thanks! :) It

Re: [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

On 05/14/2015 01:47 AM, Rafael J. Wysocki wrote: > ... If I'm supposed to apply this, I need ACKs from the appropriate people on all the patches where they are still missing. Thanks! I believe Thierry Reding will apply the series; your ACK as cpufreq maintainer for patch 13, and maybe

Re: [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

On 05/15/2015 05:09 AM, Viresh Kumar wrote: On 15 May 2015 at 01:45, Rafael J. Wysocki r...@rjwysocki.net wrote: You need ACKs from Viresh for those two, then. He's officially responsible for ARM cpufreq drivers. I thought an Ack for 14th is enough :) For: 12/13/14. Acked-by: Viresh Kumar

Re: [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

On 05/14/2015 01:47 AM, Rafael J. Wysocki wrote: ... If I'm supposed to apply this, I need ACKs from the appropriate people on all the patches where they are still missing. Thanks! I believe Thierry Reding will apply the series; your ACK as cpufreq maintainer for patch 13, and maybe also

[PATCH v9 06/17] clk: tegra: Add DFLL DVCO reset control for Tegra124

block will complete. Thanks to Aleksandr Frid for identifying this and saving hours of debugging time. Signed-off-by: Paul Walmsley [ttynkkynen: ported to tegra124 from tegra114] Signed-off-by: Tuomas Tynkkynen [mikko.perttunen: ported to special reset callback] Signed-off-by: Mikko Perttunen

[PATCH v9 02/17] clk: tegra: Add library for the DFLL clock source (open-loop mode)

-off-by: Paul Walmsley Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Peter De Schrijver Acked-by: Michael Turquette --- drivers/clk/tegra/Makefile |1 + drivers/clk/tegra/clk-dfll.c | 1095 ++ drivers/clk/tegra/clk-dfll.h

[PATCH v9 09/17] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

From: Tuomas Tynkkynen The DFLL clocksource was missing from the list of possible parents for the fast CPU cluster. Add it to the list. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette --- drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +++- 1 file

[PATCH v9 10/17] ARM: tegra: Add the DFLL to Tegra124 device tree

From: Tuomas Tynkkynen The DFLL clocksource is a separate IP block from the usual clock-and-reset controller, so it gets its own device tree node. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette --- arch/arm/boot/dts/tegra124.dtsi | 25

[PATCH v9 14/17] cpufreq: Add cpufreq driver for Tegra124

driver for all the cpufreq operations. This driver also relies on the DFLL driver to fill the OPP table for the CPU0 device, so that the cpufreq-dt driver knows what frequencies to use. Signed-off-by: Tuomas Tynkkynen Acked-by: Viresh Kumar Signed-off-by: Mikko Perttunen --- drivers/cpufreq

[PATCH v9 03/17] clk: tegra: Add closed loop support for the DFLL

Signed-off-by: Mikko Perttunen Acked-by: Peter De Schrijver Acked-by: Michael Turquette --- drivers/clk/tegra/clk-dfll.c | 666 ++- 1 file changed, 663 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk

[PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

just renames a driver), so hopefully we can get this merged. Mikko Perttunen (2): clk: tegra: Introduce ability for SoC-specific reset control callbacks ARM: tegra: Add CPU regulator to the Jetson TK1 device tree Paul Walmsley (1): clk: tegra: Add DFLL DVCO reset control for Tegra124 Tuomas

[PATCH v9 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

set should not be used, as some functions interpret these as negative error codes. Each SoC with these special resets should specify the defined reset control numbers in a device tree header file. Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette --- drivers/clk/tegra/clk.c |

[PATCH v9 17/17] ARM: tegra: enable Tegra124 cpufreq driver by default

From: Tuomas Tynkkynen The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so enable it to get the Tegra driver to build by default. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen --- arch/arm/configs/tegra_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH v9 13/17] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq

From: Tuomas Tynkkynen The Tegra124 will use a different driver for frequency scaling, so rename the old driver (which handles only Tegra20) appropriately. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen --- drivers/cpufreq/Kconfig.arm| 6

[PATCH v9 16/17] ARM: tegra: Add CPU regulator to the Jetson TK1 device tree

Specify the CPU voltage regulator for the cpufreq driver. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts

[PATCH v9 12/17] cpufreq: tegra124: Add device tree bindings

From: Tuomas Tynkkynen The cpufreq driver for Tegra124 will be a different one than the old Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device tree. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen --- .../bindings/cpufreq/tegra124-cpufreq.txt | 44

[PATCH v9 07/17] clk: tegra: Add Tegra124 DFLL clocksource platform driver

-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette --- drivers/clk/tegra/Makefile | 2 + drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 161 + 2 files changed, 163 insertions(+) create mode 100644 drivers/clk/tegra/clk

[PATCH v9 15/17] ARM: tegra: Add entries for cpufreq on Tegra124

From: Tuomas Tynkkynen The Tegra124 cpufreq driver relies on certain clocks being present in the /cpus/cpu@0 node. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen --- arch/arm/boot/dts/tegra124.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts

[PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1

From: Tuomas Tynkkynen Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette --- arch/arm

[PATCH v9 04/17] clk: tegra: Add functions for parsing CVB tables

on an per-chip basis. Add utility functions to parse the Tegra-specific tables and export the voltage-frequency pairs to the generic OPP framework for other drivers to use. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Peter De Schrijver Acked-by: Michael Turquette

[PATCH v9 08/17] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend

From: Tuomas Tynkkynen Save and restore this register since the LP1 restore assembly routines fiddle with it. Otherwise the CPU would keep running on PLLX after resume from suspend even when DFLL was the original clocksource. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen

[PATCH v9 01/17] clk: tegra: Add binding for the Tegra124 DFLL clocksource

-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette --- .../bindings/clock/nvidia,tegra124-dfll.txt| 79 ++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt diff --git

[PATCH v9 13/17] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq

From: Tuomas Tynkkynen ttynkky...@nvidia.com The Tegra124 will use a different driver for frequency scaling, so rename the old driver (which handles only Tegra20) appropriately. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi

[PATCH v9 08/17] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend

...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Peter De Schrijver pdeschrij...@nvidia.com Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk-tegra124.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/tegra/clk

[PATCH v9 04/17] clk: tegra: Add functions for parsing CVB tables

to be calculated on an per-chip basis. Add utility functions to parse the Tegra-specific tables and export the voltage-frequency pairs to the generic OPP framework for other drivers to use. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi

[PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1

From: Tuomas Tynkkynen ttynkky...@nvidia.com Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen

[PATCH v9 17/17] ARM: tegra: enable Tegra124 cpufreq driver by default

From: Tuomas Tynkkynen ttynkky...@nvidia.com The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so enable it to get the Tegra driver to build by default. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi --- arch/arm/configs

[PATCH v9 03/17] clk: tegra: Add closed loop support for the DFLL

-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Peter De Schrijver pdeschrij...@nvidia.com Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk-dfll.c | 666 ++- 1 file

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