Re: Linux Interrupt Context maps to ARM CPSR.mode = IRQ

On Fri, May 2, 2014 at 7:17 PM, Marc Zyngier wrote: > On 2014-05-02 13:34, Mj Embd wrote: >> >> Adding Marc to comment >> Marc Please clarify the doubt >> >> >> >> On Fri, May 2, 2014 at 5:15 PM, Mj Embd wrote: >>> >>> Hi, >

Re: Linux Interrupt Context maps to ARM CPSR.mode = IRQ

Adding Marc to comment Marc Please clarify the doubt On Fri, May 2, 2014 at 5:15 PM, Mj Embd wrote: > Hi, > > As per a lot of linux documentation some components work in process > context and some work in interrupt context. > > If we try to map these contexts to ARM processo

Linux Interrupt Context maps to ARM CPSR.mode = IRQ

Hi, As per a lot of linux documentation some components work in process context and some work in interrupt context. If we try to map these contexts to ARM processor modes then is it safely to assume that Process Context : CPSR.mode = SVC Interrupt Context : CPSR.mode = IRQ If not how to define i

Re: Arndale Timer Interrupt Question

On 1/10/14, Tomasz Figa wrote: > Hi, > > On 09.01.2014 13:52, Bartlomiej Zolnierkiewicz wrote: >> >> added linux-samsung-soc to cc:, >> it is a better suited list for this question >> >> On Thursday, January 09, 2014 10:30:56 AM Mj Embd wrote: >>>

Arndale Timer Interrupt Question

I am a bit confused on the interrupt number for CNTVIRQ..CNTHPIRQ. Can you please help here. As per the exynos5 public manual What is the difference between  CPU_nCNTHPIRQ[0] and CNTHPIRQ. While the later has an interrupt ID 26, the former is part of a group with combined interrupt id as 33 for

Latest Linux version known to be working with Fast Model

Hi all, Can anyone help on this... Looking for latest linux version working with FastModel (A15x2 or A15x2_A7x2) along with device tree and config file. Many thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org Mor

ARM GIC Virtualization question

Hi All, a) As per GIC-400 all Physical interrupts trap into hypervisor b) Hypervisor does ACK, programs Virtual GIC list registers (with PhysIRQ:VIRQ) and does a world switch. c) GIC CPU I/f interrupts Guest with the VIRQ d) Guest does a ACK and EOI to GIC cpu i/f e) Hypervisor gets a maintenance

Re: AMP linux and GPU/HDMI controller sharing

Hello All, Please help me out. No comments so far ... On 9/29/13, Mj Embd wrote: > Hi, > > I have got a client request to support on their board 2 instances of > linux(Ubuntu) running as an AMP. > The board has 2 ARM cores and a GPU. The LED monitor which connects to > the b

AMP linux and GPU/HDMI controller sharing

Hi, I have got a client request to support on their board 2 instances of linux(Ubuntu) running as an AMP. The board has 2 ARM cores and a GPU. The LED monitor which connects to the board is using HDMI. Two cores can communicate via a IPI handshake. So release and acquire of the GPU can be done co

Re: [V3,3/7] ARM: dts: Add gpio-button entries for Arndale board

PS:Adding linux kernel for a larger forum comments Hi Linaro, I am trying to attach interrupt handlers to the push buttons on the arndale board. Your patch adds in dts information on the push buttons menu { + label = "SW-TACT2"; + gpios = <&gpx1 4 1>;