Hi Hao,
this looks suspiciously like a hwmon driver ;-)
https://www.kernel.org/doc/Documentation/hwmon/hwmon-kernel-api.txt
Cheers,
Moritz
On Thu, Apr 11, 2019 at 1:08 PM Alan Tull wrote:
>
> On Sun, Mar 24, 2019 at 10:24 PM Wu Hao wrote:
>
> Hi Hao,
>
> >
> > This patch adds support for
DMA_BIDIRECTIONAL);
> > - if (dma_mapping_error(>dev->dev, region->iova)) {
> > + if (dma_mapping_error(dfl_fpga_pdata_to_parent(pdata), region->iova))
> > {
> > dev_err(>dev->dev, "failed to map for dma\n");
> > ret = -EFAULT;
> > goto unpin_pages;
> > --
> > 1.8.3.1
Acked-by: Moritz Fischer
Thanks
Moritz
: Tuesday, April 9, 2019 12:04 PM
> > To: Moritz Fischer ; Nava kishore Manne
> >
> > Cc: at...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> > Simek ; Rajan Vaja ; Jolly Shah
> > ; linux-f...@vger.kernel.org; devicet...@vger.kernel.org;
> &g
Hi Nava,
On Tue, Apr 02, 2019 at 06:01:21PM +0530, Nava kishore Manne wrote:
> This Patch Adds fpga API's to support the Bitstream loading
> by using firmware interface.
>
> Signed-off-by: Nava kishore Manne
> ---
> Changes for v4:
> -None.
>
> Chnages for v3:
>
Hi Michal,
On Mon, Apr 08, 2019 at 04:36:15PM +0200, Michal Simek wrote:
> On 08. 04. 19 16:17, Alan Tull wrote:
> > On Mon, Apr 8, 2019 at 7:39 AM Nava kishore Manne wrote:
> >>
> >> Hi Alan,
> >>
> >> Thanks for look into it and providing the A
On Wed, Apr 03, 2019 at 01:37:51PM -0500, Alan Tull wrote:
> >
> > it's state, not status for most fpga manager drivers. It should
> > return 'operating' if everything went well.
Yeah, sorry :)
> > It seems like there's a possible scenario where the FPGA starts up
> > with the FPGA in
Hi Hao,
On Thu, Apr 04, 2019 at 12:31:47AM +0800, Wu Hao wrote:
> On Tue, Apr 02, 2019 at 07:59:25AM -0700, Moritz Fischer wrote:
> > Hi Wu,
> >
> > On Mon, Mar 25, 2019 at 11:07:41AM +0800, Wu Hao wrote:
> > > This patch adds support to thermal management priv
Hi Richard,
On Wed, Apr 03, 2019 at 11:43:26AM -0500, Richard Gong wrote:
> Hi Moritz,
>
>
> On 4/3/19 9:20 AM, Moritz Fischer wrote:
> > Hi Richard,
> >
> > On Tue, Apr 02, 2019 at 05:25:43PM -0500, richard.g...@linux.intel.com
> > wrote:
> > &g
Hi Richard,
On Tue, Apr 02, 2019 at 05:25:43PM -0500, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add a log for user to know FPGA configuration is successful
>
> Signed-off-by: Richard Gong
> ---
> drivers/fpga/fpga-mgr.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
-by: Wu Hao
Acked-by: Moritz Fischer
> ---
> drivers/fpga/dfl-afu-main.c | 25 ++---
> drivers/fpga/dfl-afu.h | 3 +++
> 2 files changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
> index
-by: Wu Hao
Acked-by: Moritz Fischer
> ---
> drivers/fpga/dfl-afu-main.c | 14 --
> drivers/fpga/dfl-fme-main.c | 11 ---
> drivers/fpga/dfl-fme-pr.c | 7 ++-
> drivers/fpga/dfl-fme.h | 3 ++-
> drivers/fpga/dfl.c | 21 +++--
STP service.
>
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
> ---
> drivers/fpga/dfl-afu-main.c | 34 ++
> 1 file changed, 34 insertions(+)
>
> diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-ma
Hi Wu,
On Mon, Mar 25, 2019 at 11:07:41AM +0800, Wu Hao wrote:
> This patch adds support to thermal management private feature for DFL
> FPGA Management Engine (FME). As thermal throttling is handled by
> hardware automatically per pre-defined thresholds, this private
> feature driver only
Hi Wu,
On Tue, Apr 02, 2019 at 12:38:45PM +0800, Wu Hao wrote:
> On Mon, Apr 01, 2019 at 12:54:47PM -0700, Moritz Fischer wrote:
> > Hi Wu,
> >
> > On Mon, Mar 25, 2019 at 11:07:28AM +0800, Wu Hao wrote:
> > > FME_PR_INTFC_ID is used as compat_id for fpga manager
> + */
> +struct zynqmp_fpga_priv {
> + struct device *dev;
> + u32 flags;
> +};
> +
[..]
Reviewed-by: Moritz Fischer
Thanks,
Moritz
.
> > >
> > > Signed-off-by: Nava kishore Manne
> > > ---
> > > Changes for v5:
> > > -Moved pcap node as a child to firwmare
> > >node as suggested by Rob.
> > > Changes for v4:
> > >
Hi Wu,
On Mon, Mar 25, 2019 at 11:07:28AM +0800, Wu Hao wrote:
> FME_PR_INTFC_ID is used as compat_id for fpga manager and region,
> but high 64 bits and low 64 bits of the compat_id are swapped by
> mistake. This patch fixes this problem by fixing register address.
>
> Signed-off-by: Wu Hao
>
Hi Lee,
thanks for your feedback!
On Thu, Feb 14, 2019 at 1:34 AM Lee Jones wrote:
>
> On Mon, 11 Feb 2019, Virendra Kakade wrote:
>
> > Signed-off-by: Virendra Kakade
> > ---
> > drivers/mfd/Kconfig | 7 +++
> > drivers/mfd/Makefile | 2 +-
> > drivers/mfd/e31x-pmu.c
Hi Nava,
On Sun, Feb 10, 2019 at 8:17 AM Nava kishore Manne
wrote:
>
> This patch adds FPGA Manager support for the Xilinx
> ZynqMP chip.
>
> Signed-off-by: Nava kishore Manne
> ---
> Changes for v3:
> -Created patches on top of 5.0-rc5.
> No functional changes.
Hi Nava,
a couple of nits inline. otherwise looks fine to me.
On Sun, Feb 10, 2019 at 8:17 AM Nava kishore Manne
wrote:
>
> Add documentation to describe Xilinx ZynqMP fpga driver
> bindings.
>
> Signed-off-by: Nava kishore Manne
> ---
> Changes for v3:
> -Created patches on
Hi Virendra,
On Mon, Feb 11, 2019 at 5:02 PM Virendra Kakade wrote:
>
> Document bindings for E31x device PMU MFD driver.
>
> Signed-off-by: Virendra Kakade
> ---
> Documentation/devicetree/bindings/mfd/e31x-pmu.txt | 14 ++
> 1 file changed, 14 insertions(+)
> create mode 100644
Hi David,
On Thu, Feb 7, 2019 at 6:15 PM David Miller wrote:
>
> From: Moritz Fischer
> Date: Thu, 7 Feb 2019 12:14:55 -0800
>
> > Add fixed_phy_register_with_gpiod() API. It lets users create a
> > fixed_phy instance that uses a GPIO descriptor which was obtained
>
Add fixed_phy_register_with_gpiod() API. It lets users create a
fixed_phy instance that uses a GPIO descriptor which was obtained
externally e.g. through platform data.
This enables platform devices (non-DT based) to use GPIOs for link
status.
Reviewed-by: Florian Fainelli
Signed-off-by: Moritz
Add fixed_phy_register_with_gpiod() API. It lets users create a
fixed_phy instance that uses a GPIO descriptor which was obtained
externally e.g. through platform data.
This enables platform devices (non-DT based) to use GPIOs for link
status.
Signed-off-by: Moritz Fischer
---
Changes from RFC
Fix fixed_phy not checking GPIO if no link_update callback
is registered.
In the original version all users registered a link_update
callback so the issue was masked.
Fixes: a5597008dbc2 ("phy: fixed_phy: Add gpio to determine link up/down.")
Reviewed-by: Andrew Lunn
Signed-off-
Hi Andrew,
thanks for your feedback.
On Wed, Feb 06, 2019 at 10:53:22PM +0100, Andrew Lunn wrote:
> On Wed, Feb 06, 2019 at 12:51:06PM -0800, Moritz Fischer wrote:
> > Move the DT based link GPIO parsing to of_mdio and let the places
> > that register a fixed_phy pass in a
Move the DT based link GPIO parsing to of_mdio and let the places
that register a fixed_phy pass in a GPIO descriptor or NULL.
This allows fixed_phy on non-DT platforms to have link GPIOs, too.
Signed-off-by: Moritz Fischer
---
drivers/net/dsa/dsa_loop.c | 2 +-
drivers/net
From: Moritz Fischer
Update device-tree binding with fixed-link support.
With fixed-link support the formerly required property 'phy-handle'
is now optional if 'fixed-link' child is present.
Signed-off-by: Moritz Fischer
---
.../devicetree/bindings/net/nixge.txt | 33
From: Moritz Fischer
This series adds fixed-link support to nixge.
The first patch corrects the binding to correctly reflect
hardware that does not come with MDIO cores instantiated.
The second patch adds fixed link support to the driver.
The third patch updates the binding document
From: Moritz Fischer
Make MDIO child optional and only instantiate the
MDIO bus if the child is actually present.
There are currently no (in-tree) users of this
binding; all (out-of-tree) users use overlays that
get shipped together with the FPGA images that contain
the IP
From: Moritz Fischer
Add support for fixed-link configurations to nixge driver.
Signed-off-by: Moritz Fischer
---
drivers/net/ethernet/ni/nixge.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/ni/nixge.c b/drivers/net
On Mon, Feb 04, 2019 at 03:58:54PM +0100, Andrew Lunn wrote:
> On Fri, Feb 01, 2019 at 06:50:48PM -0800, Moritz Fischer wrote:
> > Make MDIO child optional and only instantiate the
> > MDIO bus if the child is actually present.
> >
> > There are currently no (in-tree
maintainabilty
of future revisions of this IP.
Signed-off-by: Moritz Fischer
Cc: Andrew Lunn
Cc: Rob Herring
---
Hi Rob, Andrew,
I know generally changing bindings is a no-no. Ultimately
I'm working on adding fixed-link support to this driver,
during the review of that Andrew suggested to drop
data bss dec hex filename
> >72812096 0937724a1 drivers/fpga/altera-ps-spi.o
> >
> > (gcc version 8.2.0 x86_64)
> >
> > Signed-off-by: Colin Ian King
>
> Acked-by: Alan Tull
Acked-by: Moritz Fischer
>
>
> > ---
Hi Dick,
On Fri, Jan 18, 2019 at 03:41:04PM -0600, Dick Hollenbeck wrote:
> Add Cyclone-10 support to altera-ps-spi.c.
> Invert logic involving nCONFIG, nSTATUS, and CONFIG_DONE so it matches
> datasheets
> by going with GPIO_ACTIVE_HIGH instead of GPIO_ACTIVE_LOW in the device
> tree. Add
Hi Enrico,
On Mon, Jan 21, 2019 at 11:19:34PM +0100, Enric Balletbo Serra wrote:
> I tried with a Samsung Chromebook Plus (arm64 Chromebook)
>
> > What was the ioctl you ran?
> >
>
> The code that I ran is this: https://hastebin.com/cupecuvowi.py
> No guarantee :) I'll try to look deeper
Hi Enrico,
On Mon, Jan 21, 2019 at 06:32:48PM +0100, Enric Balletbo Serra wrote:
> Hi Moritz,
>
> Missatge de Moritz Fischer del dia dj., 10 de gen.
> 2019 a les 5:40:
> >
> > Add cros_ec_readmem() helpers for I2C/SPI based ECs.
> > Unlike the LPC based ECs the
On Tue, Jan 15, 2019 at 6:01 PM Alan Tull wrote:
>
> The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA
> since it can be used on other platforms such as Stratix10.
>
> Signed-off-by: Alan Tull
Reviewed-by: Moritz Fischer
> ---
> v2: add depends on HAS
Hi Alan,
On Thu, Jan 10, 2019 at 3:06 PM Alan Tull wrote:
>
> The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA
> since it can be used on other platforms such as Stratix10.
>
> Signed-off-by: Alan Tull
> ---
> drivers/fpga/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1
Add cros_ec_readmem() helpers for I2C/SPI based ECs.
Unlike the LPC based ECs the I2C/SPI based ones cannot just directly
read the mapped region, but have to resort to EC_CMD_READ_MEMMAP.
This is useful for things like accessing fan speeds or temperatures.
Signed-off-by: Moritz Fischer
---
Hi
s for the patch,I've one concern on this, and I'd be also
> >> interested
> >> on Benson and Guenter opinion ...
> >>
> >> On 8/1/19 4:56, Moritz Fischer wrote:
> >>> From: Moritz Fischer
> >>>
> >>> Add cros_ec_readmem() based he
From: Moritz Fischer
Add cros_ec_readmem() based helpers for I2C/SPI based ECs.
Unlike the LPC based ECs the I2C/SPI based ones cannot just directly
read the mapped region.
This is useful for things like accessing fan speeds or temperatures.
Signed-off-by: Moritz Fischer
---
Hi all,
I had
tree/bindings/power/reset/gpio-poweroff.txt | 2 ++
> > drivers/power/reset/gpio-poweroff.c| 10 --
> > 2 files changed, 10 insertions(+), 2 deletions(-)
> >
>
> Reviewed-by: Rob Herring
Reviewed-by: Moritz Fischer
tree/bindings/power/reset/gpio-poweroff.txt | 2 ++
> > drivers/power/reset/gpio-poweroff.c| 10 --
> > 2 files changed, 10 insertions(+), 2 deletions(-)
> >
>
> Reviewed-by: Rob Herring
Reviewed-by: Moritz Fischer
nt on that node
> > again.
> >
> > This patch removes the unwarranted call to of_node_put().
> >
> > Fixes: e7eef1d7633a ("fpga: add intel stratix10 soc fpga manager driver")
> > Signed-off-by: Nicolas Saenz Julienne
> Acked-by: Alan Tull
Acked-by: Moritz F
nt on that node
> > again.
> >
> > This patch removes the unwarranted call to of_node_put().
> >
> > Fixes: e7eef1d7633a ("fpga: add intel stratix10 soc fpga manager driver")
> > Signed-off-by: Nicolas Saenz Julienne
> Acked-by: Alan Tull
Acked-by: Moritz F
: 34d1dc17ce97 ("fpga manager: Add Altera CvP driver")
> Signed-off-by: Andreas Puhm
> Signed-off-by: Anatolij Gustschin
Reviewed-by: Moritz Fischer
> ---
> Changes in v2:
> - improve Fixes tag
> - wrap lines in commit description
>
> drivers/fpga/altera-cvp.c | 9
: 34d1dc17ce97 ("fpga manager: Add Altera CvP driver")
> Signed-off-by: Andreas Puhm
> Signed-off-by: Anatolij Gustschin
Reviewed-by: Moritz Fischer
> ---
> Changes in v2:
> - improve Fixes tag
> - wrap lines in commit description
>
> drivers/fpga/altera-cvp.c | 9
Hi Andreas,
On Thu, Oct 25, 2018 at 08:44:06AM +, Andreas Puhm wrote:
> >My experience with cvp is with Arria10 and Stratix 10. The PCIe Hard IP
> >gets configured when the IOring gets configured at power on. The idea is
> >that the load of the IOring is very fast, much before the infamous
Hi Andreas,
On Thu, Oct 25, 2018 at 08:44:06AM +, Andreas Puhm wrote:
> >My experience with cvp is with Arria10 and Stratix 10. The PCIe Hard IP
> >gets configured when the IOring gets configured at power on. The idea is
> >that the load of the IOring is very fast, much before the infamous
gt; With that change feel free to add my Reviewed-by: Moritz Fischer
> > in your v2.
>
> That clock can be used by something else that's why you didn't observe
> any issue. Anyway I have no problem with reverting that setting back
> that icap can be used.
Ok, thanks for clarifi
gt; With that change feel free to add my Reviewed-by: Moritz Fischer
> > in your v2.
>
> That clock can be used by something else that's why you didn't observe
> any issue. Anyway I have no problem with reverting that setting back
> that icap can be used.
Ok, thanks for clarifi
Hi Anatolij, Andreas,
On Tue, Oct 23, 2018 at 06:46:47PM +, Andreas Puhm wrote:
> Hi Anatolij,
>
> > The CvP docs says that on some FPGAs (e.g. Arria 10) the assertion of CVP
> > status can take up to 500ms. However it is not clear whether this delay
> > might be required after peripheral
Hi Anatolij, Andreas,
On Tue, Oct 23, 2018 at 06:46:47PM +, Andreas Puhm wrote:
> Hi Anatolij,
>
> > The CvP docs says that on some FPGAs (e.g. Arria 10) the assertion of CVP
> > status can take up to 500ms. However it is not clear whether this delay
> > might be required after peripheral
Hi Mike,
On Tue, Oct 23, 2018 at 10:53:50AM +, Mike Looijmans wrote:
> On 23-10-18 11:01, Moritz Fischer wrote:
> > Hi Mike,
> >
> > seems like a good usecase (though uncommon), question below
>
> Usecases for ICAP:
> - It's considerably faster than PCAP
Hi Mike,
On Tue, Oct 23, 2018 at 10:53:50AM +, Mike Looijmans wrote:
> On 23-10-18 11:01, Moritz Fischer wrote:
> > Hi Mike,
> >
> > seems like a good usecase (though uncommon), question below
>
> Usecases for ICAP:
> - It's considerably faster than PCAP
Hi Andreas,
we're getting there :) It seems your mail setup is still a bit
funky though. Did you use git send-email / git format-patch?
On Tue, Oct 23, 2018 at 09:01:39AM +, Andreas Puhm wrote:
> From bfc602900b016f65bc2f183aa93702101a1fdc17 Mon Sep 17 00:00:00 2001
> From: Andreas Puhm
>
Hi Andreas,
we're getting there :) It seems your mail setup is still a bit
funky though. Did you use git send-email / git format-patch?
On Tue, Oct 23, 2018 at 09:01:39AM +, Andreas Puhm wrote:
> From bfc602900b016f65bc2f183aa93702101a1fdc17 Mon Sep 17 00:00:00 2001
> From: Andreas Puhm
>
Hi Mike,
seems like a good usecase (though uncommon), question below
On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote:
> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
> it impossible to use the ICAP interface for partial reconfiguration.
>
> This patch
Hi Mike,
seems like a good usecase (though uncommon), question below
On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote:
> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
> it impossible to use the ICAP interface for partial reconfiguration.
>
> This patch
Hi Andreas,
On Mon, Oct 22, 2018 at 01:15:34PM +, Andreas Puhm wrote:
Can you please send your patch using git-send-email?
[..]
> Subject: [PATCH] fpga: altera_cvp: restrict registration to CvP enabled
> devices
How about:
fpga: altera-cvp: Fix registration for CvP incapable devices
Hi Andreas,
On Mon, Oct 22, 2018 at 01:15:34PM +, Andreas Puhm wrote:
Can you please send your patch using git-send-email?
[..]
> Subject: [PATCH] fpga: altera_cvp: restrict registration to CvP enabled
> devices
How about:
fpga: altera-cvp: Fix registration for CvP incapable devices
Hi Andreas,
On Fri, Oct 19, 2018 at 03:53:02PM +, Andreas Puhm wrote:
> Hello,
>
> I hope the following information is descriptive enough.
> If this is no the case, I will provide further details.
>
>
> Full description:
>
Hi Andreas,
On Fri, Oct 19, 2018 at 03:53:02PM +, Andreas Puhm wrote:
> Hello,
>
> I hope the following information is descriptive enough.
> If this is no the case, I will provide further details.
>
>
> Full description:
>
On Mon, Oct 22, 2018 at 10:03:55AM +, Nava kishore Manne wrote:
> Hi Mortiz,
>
> Thanks for the quick response
> Please find my response inline.
>
> > -Original Message-----
> > From: Moritz Fischer [mailto:moritz.fisc...@ettus.com]
> > Sent: S
On Mon, Oct 22, 2018 at 10:03:55AM +, Nava kishore Manne wrote:
> Hi Mortiz,
>
> Thanks for the quick response
> Please find my response inline.
>
> > -Original Message-----
> > From: Moritz Fischer [mailto:moritz.fisc...@ettus.com]
> > Sent: S
On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
wrote:
>
> Hi Nava,
>
> Looks good to me, a couple of nits inline below.
>
> On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> wrote:
> >
> > This patch adds FPGA Manager support for the Xilinx
>
On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
wrote:
>
> Hi Nava,
>
> Looks good to me, a couple of nits inline below.
>
> On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> wrote:
> >
> > This patch adds FPGA Manager support for the Xilinx
>
Hi Nava,
Looks good to me, a couple of nits inline below.
On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
wrote:
>
> This patch adds FPGA Manager support for the Xilinx
> ZynqMp chip.
Isn't it ZynqMP ?
>
> Signed-off-by: Nava kishore Manne
> ---
> Changes for v1:
> -None.
>
Hi Nava,
Looks good to me, a couple of nits inline below.
On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
wrote:
>
> This patch adds FPGA Manager support for the Xilinx
> ZynqMp chip.
Isn't it ZynqMP ?
>
> Signed-off-by: Nava kishore Manne
> ---
> Changes for v1:
> -None.
>
forms")
Signed-off-by: Moritz Fischer
Cc: Arnd Bergmann
---
drivers/net/ethernet/ni/nixge.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/ni/nixge.c b/drivers/net/ethernet/ni/nixge.c
index 74cf52e3fb09..0611f2335b4a 100644
--- a/d
forms")
Signed-off-by: Moritz Fischer
Cc: Arnd Bergmann
---
drivers/net/ethernet/ni/nixge.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/ni/nixge.c b/drivers/net/ethernet/ni/nixge.c
index 74cf52e3fb09..0611f2335b4a 100644
--- a/d
Hi Olof,
On Sat, Sep 8, 2018 at 6:18 PM, Olof Johansson wrote:
> Hi,
>
> On Fri, Aug 3, 2018 at 10:53 AM, Jolly Shah wrote:
>> From: Rajan Vaja
>>
>> Add ZynqMP firmware IOCTL API to control and configure
>> devices like PLLs, SD, Gem, etc.
>>
>> Signed-off-by: Rajan Vaja
>> Signed-off-by:
Hi Olof,
On Sat, Sep 8, 2018 at 6:18 PM, Olof Johansson wrote:
> Hi,
>
> On Fri, Aug 3, 2018 at 10:53 AM, Jolly Shah wrote:
>> From: Rajan Vaja
>>
>> Add ZynqMP firmware IOCTL API to control and configure
>> devices like PLLs, SD, Gem, etc.
>>
>> Signed-off-by: Rajan Vaja
>> Signed-off-by:
ically:
>
> compatible = "altr,freeze-bridge";
>
> The compatibility string should be "altr,freeze-bridge-controller"
> as set forth in altera-freeze-bridge.txt.
>
> Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
Cheers,
Moritz
ically:
>
> compatible = "altr,freeze-bridge";
>
> The compatibility string should be "altr,freeze-bridge-controller"
> as set forth in altera-freeze-bridge.txt.
>
> Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
Cheers,
Moritz
Use platform_set_drvdata rather than dev_set_drvdata
to match the platform_get_drvdata in the _remove()
function of the platform driver.
Signed-off-by: Moritz Fischer
---
drivers/fpga/of-fpga-region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/of-fpga
Use platform_set_drvdata rather than dev_set_drvdata
to match the platform_get_drvdata in the _remove()
function of the platform driver.
Signed-off-by: Moritz Fischer
---
drivers/fpga/of-fpga-region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/of-fpga
Use platform_get_drvdata() in remove() function of
the platform driver rather than dev_get_drvdata()
to match the platform_set_drvdata in the probe().
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl-fme-region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga
Use platform_get_drvdata() in remove() function of
the platform driver rather than dev_get_drvdata()
to match the platform_set_drvdata in the probe().
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl-fme-region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga
Hi Alan,
On Mon, Aug 20, 2018 at 12:46:32PM -0500, Alan Tull wrote:
> On Mon, Aug 20, 2018 at 12:18 PM, Moritz Fischer wrote:
>
> Hi Moritz,
>
> > Replace dev_get_drvdata() with platform_get_drvdata() to
> > match the platform_set_drvdata() in the probe function of
Hi Alan,
On Mon, Aug 20, 2018 at 12:46:32PM -0500, Alan Tull wrote:
> On Mon, Aug 20, 2018 at 12:18 PM, Moritz Fischer wrote:
>
> Hi Moritz,
>
> > Replace dev_get_drvdata() with platform_get_drvdata() to
> > match the platform_set_drvdata() in the probe function of
Replace dev_get_drvdata() with platform_get_drvdata() to
match the platform_set_drvdata() in the probe function of
the platform driver.
Fixes commit bb61b9be3e6b ("fpga: dfl: add fpga region platform driver for FME")
Signed-off-by: Moritz Fischer
---
Changes from v1:
- Still com
Replace dev_get_drvdata() with platform_get_drvdata() to
match the platform_set_drvdata() in the probe function of
the platform driver.
Fixes commit bb61b9be3e6b ("fpga: dfl: add fpga region platform driver for FME")
Signed-off-by: Moritz Fischer
---
Changes from v1:
- Still com
On Fri, Aug 17, 2018 at 4:40 PM, Moritz Fischer wrote:
> Replace dev_get_drvdata() with platform_get_drvdata() to
> match the platform_set_drvdata() in the probe function of
> the platform driver.
>
> Fixes commit bb61b9be3e6b ("fpga: dfl: add fpga region platform driver for
On Fri, Aug 17, 2018 at 4:40 PM, Moritz Fischer wrote:
> Replace dev_get_drvdata() with platform_get_drvdata() to
> match the platform_set_drvdata() in the probe function of
> the platform driver.
>
> Fixes commit bb61b9be3e6b ("fpga: dfl: add fpga region platform driver for
Replace dev_get_drvdata() with platform_get_drvdata() to
match the platform_set_drvdata() in the probe function of
the platform driver.
Fixes commit bb61b9be3e6b ("fpga: dfl: add fpga region platform driver for
FME")
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl-fme-region.c | 2
Replace dev_get_drvdata() with platform_get_drvdata() to
match the platform_set_drvdata() in the probe function of
the platform driver.
Fixes commit bb61b9be3e6b ("fpga: dfl: add fpga region platform driver for
FME")
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl-fme-region.c | 2
Hi Wendy,
couple of minor stuff inline.
On Thu, Aug 16, 2018 at 12:06 AM, Wendy Liang wrote:
> Add device tree binding for Xilinx Cortex-r5 remoteproc.
>
> Signed-off-by: Wendy Liang
> ---
> .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81
> ++
> 1 file changed,
Hi Wendy,
couple of minor stuff inline.
On Thu, Aug 16, 2018 at 12:06 AM, Wendy Liang wrote:
> Add device tree binding for Xilinx Cortex-r5 remoteproc.
>
> Signed-off-by: Wendy Liang
> ---
> .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81
> ++
> 1 file changed,
Hi Alan,
On Tue, Aug 14, 2018 at 02:15:25PM -0500, Alan Tull wrote:
> Add flags #defines to kerneldoc documentation in a
> useful place.
>
> Signed-off-by: Alan Tull
> ---
> Documentation/driver-api/fpga/fpga-mgr.rst | 5 +
> include/linux/fpga/fpga-mgr.h | 18
Hi Alan,
On Tue, Aug 14, 2018 at 02:15:25PM -0500, Alan Tull wrote:
> Add flags #defines to kerneldoc documentation in a
> useful place.
>
> Signed-off-by: Alan Tull
> ---
> Documentation/driver-api/fpga/fpga-mgr.rst | 5 +
> include/linux/fpga/fpga-mgr.h | 18
Hi Appana,
On Tue, Jul 24, 2018 at 7:17 AM, Appana Durga Kedareswara rao
wrote:
> This patch does the below
> --> Adds support for readback of pl configuration data
> --> Adds support for readback of pl configuration registers
Can you please make the commit message such that you have full
Hi Appana,
On Tue, Jul 24, 2018 at 7:17 AM, Appana Durga Kedareswara rao
wrote:
> This patch does the below
> --> Adds support for readback of pl configuration data
> --> Adds support for readback of pl configuration registers
Can you please make the commit message such that you have full
On Wed, Jul 18, 2018 at 08:25:26AM +0100, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to two spelling mistakes
> "execeeded" -> "exceeded"
> "Invaild" -> "Invalid"
>
> Signed-off-by: Colin Ian King
Acked-by:
On Wed, Jul 18, 2018 at 08:25:26AM +0100, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to two spelling mistakes
> "execeeded" -> "exceeded"
> "Invaild" -> "Invalid"
>
> Signed-off-by: Colin Ian King
Acked-by:
Hi Alan,
On Wed, Jul 11, 2018 at 10:59:01AM -0500, Alan Tull wrote:
> On Wed, Jul 11, 2018 at 7:38 AM, Federico Vaga wrote:
[..]
> > This makes the usage consistent: the user creates and destroy its own
> > objects. This is also consistent with our other discussion where we
> > said, among the
Hi Alan,
On Wed, Jul 11, 2018 at 10:59:01AM -0500, Alan Tull wrote:
> On Wed, Jul 11, 2018 at 7:38 AM, Federico Vaga wrote:
[..]
> > This makes the usage consistent: the user creates and destroy its own
> > objects. This is also consistent with our other discussion where we
> > said, among the
Hi Hao,
small nit below, looks good otherwise.
On Tue, Jun 12, 2018 at 06:10:32PM +0800, Wu Hao wrote:
> This patch adds fpga manager driver for FPGA Management Engine (FME). It
> implements fpga_manager_ops for FPGA Partial Reconfiguration function.
>
> Signed-off-by: Tim Whisonant
>
Hi Hao,
small nit below, looks good otherwise.
On Tue, Jun 12, 2018 at 06:10:32PM +0800, Wu Hao wrote:
> This patch adds fpga manager driver for FPGA Management Engine (FME). It
> implements fpga_manager_ops for FPGA Partial Reconfiguration function.
>
> Signed-off-by: Tim Whisonant
>
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