[PATCH v3 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer <m...@kernel.org> Cc: Michal Simek <michal.si...@xilinx.com> Cc: Sören Brinkmann <soren.brinkm...

[PATCH v3 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer Cc: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: devicet...@vger.kernel.org --- Changes

[PATCH v2 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer <m...@kernel.org> Cc: Michal Simek <michal.si...@xilinx.com> Cc: Sören Brinkmann <soren.brinkm...

[PATCH v2 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer <m...@kernel.org> Cc: Michal Simek <michal.si...@xilinx.com> Cc: Sören Brinkmann <soren.brinkm...@xilinx.com> Cc: linux-kernel@vger.kernel.org Cc: devicet.

[PATCH v2 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer Cc: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: devicet...@vger.kernel.org --- Changes

[PATCH v2 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer Cc: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: devicet...@vger.kernel.org --- Changes from v1: - Added clock names & clock to example - Merged

Re: [PATCH v2] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

Hi Lars, On Thu, Mar 16, 2017 at 9:51 AM, Lars-Peter Clausen <l...@metafoo.de> wrote: > On 03/16/2017 05:45 PM, Michal Simek wrote: >> On 16.3.2017 17:39, Moritz Fischer wrote: >>> On Thu, Mar 16, 2017 at 9:16 AM, Michal Simek <michal.si...@xilinx.com> >>>

Re: [PATCH v2] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

Hi Lars, On Thu, Mar 16, 2017 at 9:51 AM, Lars-Peter Clausen wrote: > On 03/16/2017 05:45 PM, Michal Simek wrote: >> On 16.3.2017 17:39, Moritz Fischer wrote: >>> On Thu, Mar 16, 2017 at 9:16 AM, Michal Simek >>> wrote: >>>> Hi, >>>> >

Re: [PATCH v2] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

On Thu, Mar 16, 2017 at 9:16 AM, Michal Simek <michal.si...@xilinx.com> wrote: > Hi, > > On 8.3.2017 21:11, Moritz Fischer wrote: >> Fix >> >> OF: /iio_hwmon: could not get #io-channel-cells for >> /amba/adc@f8007100 >> OF: /iio_hwmon: could not ge

Re: [PATCH v2] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

On Thu, Mar 16, 2017 at 9:16 AM, Michal Simek wrote: > Hi, > > On 8.3.2017 21:11, Moritz Fischer wrote: >> Fix >> >> OF: /iio_hwmon: could not get #io-channel-cells for >> /amba/adc@f8007100 >> OF: /iio_hwmon: could not get #io-channel-cells for >>

Re: [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver

On Tue, Feb 28, 2017 at 8:40 AM, Anatolij Gustschin <ag...@denx.de> wrote: > The driver loads FPGA firmware over SPI, using the "slave serial" > configuration interface on Xilinx FPGAs. > > Signed-off-by: Anatolij Gustschin <ag...@denx.de> Reviewed-b

Re: [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver

On Tue, Feb 28, 2017 at 8:40 AM, Anatolij Gustschin wrote: > The driver loads FPGA firmware over SPI, using the "slave serial" > configuration interface on Xilinx FPGAs. > > Signed-off-by: Anatolij Gustschin Reviewed-by: Moritz Fischer > --- > This patch requires

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

s to be used by the various bus implementations > like the platform bus or the PCIe bus. > > Signed-off-by: Matthew Gerlach <matthew.gerl...@linux.intel.com> Reviewed-by: Moritz Fischer <m...@kernel.org> > --- > v5: > Fix comment as suggested by Rob Herring <r

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

us or the PCIe bus. > > Signed-off-by: Matthew Gerlach Reviewed-by: Moritz Fischer > --- > v5: > Fix comment as suggested by Rob Herring > v4: > v3 patch set mistakenly sent out labeled as v4 > v3: > s/alt_pr_probe/alt_pr_register/ > s/alt_pr_remove/

Re: [PATCH v5 4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

Signed-off-by: Matthew Gerlach <matthew.gerl...@linux.intel.com> Reviewed-by: Moritz Fischer <m...@kernel.org> > --- > v5: fix comment as suggested by Rob Herring <r...@kernel.org> > v4: v3 patch set mistakenly sent out labeled as v4 > v3: > s/altr,pr-ip/altr,a10-pr-

Re: [PATCH v5 4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

On Fri, Mar 10, 2017 at 11:40 AM, wrote: > From: Matthew Gerlach > > This adds a platform bus driver for a fpga-mgr driver > that uses the Altera Partial Reconfiguration IP component. > > Signed-off-by: Matthew Gerlach Reviewed-by: Moritz Fischer > --- > v5: fix com

Re: [PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

om> > Acked-by: Rob Herring <r...@kernel.org> Acked-by: Moritz Fischer <m...@kernel.org> > --- > v5: > fix comment as suggested by Rob Herring <r...@kernel.org> > added Acked-by: Rob Herring <r...@kernel.org> > v4: v3 patch set mistakenly sent

Re: [PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

On Fri, Mar 10, 2017 at 11:40 AM, wrote: > From: Matthew Gerlach > > Device Tree bindings for Altera Partial Reconfiguration IP. > > Signed-off-by: Matthew Gerlach > Acked-by: Rob Herring Acked-by: Moritz Fischer > --- > v5: > fix comment as suggested by Rob

Re: [PATCH v5 1/4] fpga: add config complete timeout

> Signed-off-by: Alan Tull <at...@opensource.altera.com> Acked-by: Moritz Fischer <m...@kernel.org> > --- > drivers/fpga/fpga-region.c| 3 +++ > include/linux/fpga/fpga-mgr.h | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-r

Re: [PATCH v5 1/4] fpga: add config complete timeout

On Fri, Mar 10, 2017 at 11:40 AM, wrote: > From: Alan Tull > > Adding timeout for maximum allowed time for FPGA to go to > operating mode after a FPGA region has been programmed. > > Signed-off-by: Alan Tull Acked-by: Moritz Fischer > --- > drivers/fpga/fpga-region

Re: [PATCH v5 0/4] Altera Partial Reconfiguration IP

Hi Matthew, On Fri, Mar 10, 2017 at 11:40 AM, wrote: > From: Matthew Gerlach > > This set of patches implements a fpga-mgr driver for the Altera Partial > Reconfiguration IP. The driver depends on a patch from Alan Tull that >

Re: [PATCH v5 0/4] Altera Partial Reconfiguration IP

Hi Matthew, On Fri, Mar 10, 2017 at 11:40 AM, wrote: > From: Matthew Gerlach > > This set of patches implements a fpga-mgr driver for the Altera Partial > Reconfiguration IP. The driver depends on a patch from Alan Tull that > adds a config complete timeout. The driver code itself is divided

Re: [PATCH 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

On Mon, Mar 13, 2017 at 3:27 AM, Michal Simek <michal.si...@xilinx.com> wrote: > Hi Moritz, > > On 10.3.2017 23:42, Moritz Fischer wrote: >> On Fri, Mar 10, 2017 at 1:30 PM, Moritz Fischer <m...@kernel.org> wrote: >>> This adds support for the Xilinx LogiCOR

Re: [PATCH 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

On Mon, Mar 13, 2017 at 3:27 AM, Michal Simek wrote: > Hi Moritz, > > On 10.3.2017 23:42, Moritz Fischer wrote: >> On Fri, Mar 10, 2017 at 1:30 PM, Moritz Fischer wrote: >>> This adds support for the Xilinx LogiCORE PR Decoupler >>> soft-ip that does dec

Re: [PATCH 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

On Fri, Mar 10, 2017 at 1:30 PM, Moritz Fischer <m...@kernel.org> wrote: > This adds support for the Xilinx LogiCORE PR Decoupler > soft-ip that does decoupling of PR regions in the FPGA > fabric during partial reconfiguration. > > Signed-off-by: Moritz Fischer <m...@kernel

Re: [PATCH 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

On Fri, Mar 10, 2017 at 1:30 PM, Moritz Fischer wrote: > This adds support for the Xilinx LogiCORE PR Decoupler > soft-ip that does decoupling of PR regions in the FPGA > fabric during partial reconfiguration. > > Signed-off-by: Moritz Fischer > Cc: Michal Simek > Cc:

[PATCH 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer <m...@kernel.org> Cc: Michal Simek <michal.si...@xilinx.com> Cc: Sören Brinkmann <soren.brinkm...

[PATCH 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler

This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer Cc: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: devicet...@vger.kernel.org --- drivers

[PATCH 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer <m...@kernel.org> Cc: Michal Simek <michal.si...@xilinx.com> Cc: Sören Brinkmann <soren.brinkm...@xilinx.com> Cc: linux-kernel@vger.kernel.org Cc: devicet.

[PATCH 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer Cc: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: devicet...@vger.kernel.org --- .../bindings/fpga/xilinx-pr-decoupler.txt | 24

[PATCH] fpga: bridge: Replace open-coded list_for_each + list_entry

Replaces open-coded list_for_each() + list_entry() with macro list_for_each_entry() Signed-off-by: Moritz Fischer <m...@kernel.org> Cc: Alan Tull <at...@kernel.org> Cc: linux-f...@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- drivers/fpga/fpga-bridge.c | 15 --- 1

[PATCH] fpga: bridge: Replace open-coded list_for_each + list_entry

Replaces open-coded list_for_each() + list_entry() with macro list_for_each_entry() Signed-off-by: Moritz Fischer Cc: Alan Tull Cc: linux-f...@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- drivers/fpga/fpga-bridge.c | 15 --- 1 file changed, 4 insertions(+), 11 deletions

Re: [PATCH v2 1/2] doc: bindings: Add bindings documentation for mtd nvmem

On Thu, Mar 9, 2017 at 7:17 PM, Marek Vasut wrote: > On 03/07/2017 09:26 AM, Alban wrote: >> Config data for drivers, like MAC addresses, is often stored in MTD. >> Add a binding that define how such data storage can be represented in >> device tree. >> >> Signed-off-by:

Re: [PATCH v2 1/2] doc: bindings: Add bindings documentation for mtd nvmem

On Thu, Mar 9, 2017 at 7:17 PM, Marek Vasut wrote: > On 03/07/2017 09:26 AM, Alban wrote: >> Config data for drivers, like MAC addresses, is often stored in MTD. >> Add a binding that define how such data storage can be represented in >> device tree. >> >> Signed-off-by: Alban >> --- >>

[PATCH] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

Fix issue when exposing xadc via iio-hwmon by adding missing OF: /iio_hwmon: could not get #io-channel-cells for /amba/adc@f8007100 Signed-off-by: Moritz Fischer <m...@kernel.org> Cc: Michal Simek <michal.si...@xilinx.com> Cc: Sören Brinkmann <soren.brinkm...@xilinx.com> Cc: Ju

[PATCH] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

Fix issue when exposing xadc via iio-hwmon by adding missing OF: /iio_hwmon: could not get #io-channel-cells for /amba/adc@f8007100 Signed-off-by: Moritz Fischer Cc: Michal Simek Cc: Sören Brinkmann Cc: Julia Cartwright Cc: linux-kernel@vger.kernel.org --- arch/arm/boot/dts/zynq-7000.dtsi

[PATCH v2] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

Fix OF: /iio_hwmon: could not get #io-channel-cells for /amba/adc@f8007100 OF: /iio_hwmon: could not get #io-channel-cells for /amba/adc@f8007100 OF: /iio_hwmon: could not get #io-channel-cells for /amba/adc@f8007100 by adding the #io-channel-cells property. Signed-off-by: Moritz Fischer &l

[PATCH v2] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

Fix OF: /iio_hwmon: could not get #io-channel-cells for /amba/adc@f8007100 OF: /iio_hwmon: could not get #io-channel-cells for /amba/adc@f8007100 OF: /iio_hwmon: could not get #io-channel-cells for /amba/adc@f8007100 by adding the #io-channel-cells property. Signed-off-by: Moritz Fischer Cc

Re: [PATCH] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

On Wed, Mar 8, 2017 at 12:08 PM, Moritz Fischer <m...@kernel.org> wrote: > Fix issue when exposing xadc via iio-hwmon by adding missing > That was messed up ... let me resend that. Sorry for the noise ... Thanks, Moritz

Re: [PATCH] ARM: zynq: Add #io-channel-cells to (x)adc node for iio-hwmon

On Wed, Mar 8, 2017 at 12:08 PM, Moritz Fischer wrote: > Fix issue when exposing xadc via iio-hwmon by adding missing > That was messed up ... let me resend that. Sorry for the noise ... Thanks, Moritz

Re: [PATCH 3/3] nvmem: core: Allow allocating several anonymous nvmem devices

me. When no name is provided take the uinque ID of >> the nvmem device instead. >> >> Signed-off-by: Alban <al...@free.fr> > > Reviewed-by: Boris Brezillon <boris.brezil...@free-electrons.com> Reviewed-by: Moritz Fischer <m...@kernel.org> Thanks, Moritz

Re: [PATCH 3/3] nvmem: core: Allow allocating several anonymous nvmem devices

> the nvmem device instead. >> >> Signed-off-by: Alban > > Reviewed-by: Boris Brezillon Reviewed-by: Moritz Fischer Thanks, Moritz

Re: [PATCH] fpga fr br: separate freeze bridge driver code

Hi Matthew, small nit inline. On Mon, Feb 27, 2017 at 12:03 PM, wrote: > From: Matthew Gerlach > > This patch separates the core Freeze Bridge > driver code from the platform driver code. > The intent is to allow the core driver code

Re: [PATCH] fpga fr br: separate freeze bridge driver code

Hi Matthew, small nit inline. On Mon, Feb 27, 2017 at 12:03 PM, wrote: > From: Matthew Gerlach > > This patch separates the core Freeze Bridge > driver code from the platform driver code. > The intent is to allow the core driver code > to be used without requiring platform driver support. > >

Re: [RFC 7/8] fpga-region: add sysfs interface

Alan, On Mon, Feb 27, 2017 at 12:09 PM, Alan Tull wrote: > First case: embedded FPGA. The hardware has one FPGA. The image is > designed for a specific board, so there's no problem including the > enumeration in the image. Agreed. > Second case: embedded FPGA +

Re: [RFC 7/8] fpga-region: add sysfs interface

Alan, On Mon, Feb 27, 2017 at 12:09 PM, Alan Tull wrote: > First case: embedded FPGA. The hardware has one FPGA. The image is > designed for a specific board, so there's no problem including the > enumeration in the image. Agreed. > Second case: embedded FPGA + a PCIe FPGA. The image will

Re: [RFC 0/3] drivers: Add an API to read device specific config data

Hi all, On Mon, Feb 27, 2017 at 12:42 PM, Boris Brezillon wrote: > +Moritz > > Hi Alban, > > On Mon, 27 Feb 2017 21:28:09 +0100 > Alban wrote: > >> Hi all, >> >> while looking at adding OF support for the ath9k driver I had the problem of >>

Re: [RFC 0/3] drivers: Add an API to read device specific config data

Hi all, On Mon, Feb 27, 2017 at 12:42 PM, Boris Brezillon wrote: > +Moritz > > Hi Alban, > > On Mon, 27 Feb 2017 21:28:09 +0100 > Alban wrote: > >> Hi all, >> >> while looking at adding OF support for the ath9k driver I had the problem of >> reading the EEPROM data. On the SoC platforms this

Re: [RFC 7/8] fpga-region: add sysfs interface

On Wed, Feb 22, 2017 at 9:54 AM, Jason Gunthorpe <jguntho...@obsidianresearch.com> wrote: > On Wed, Feb 22, 2017 at 09:50:54AM -0800, Moritz Fischer wrote: > >> > For instance, we could mark Encrypted as required, and a zynq driver >> > that does not support th

Re: [RFC 7/8] fpga-region: add sysfs interface

On Wed, Feb 22, 2017 at 9:54 AM, Jason Gunthorpe wrote: > On Wed, Feb 22, 2017 at 09:50:54AM -0800, Moritz Fischer wrote: > >> > For instance, we could mark Encrypted as required, and a zynq driver >> > that does not support the Encrypted tag would not load the bitf

Re: [RFC 7/8] fpga-region: add sysfs interface

Jason, On Wed, Feb 22, 2017 at 8:44 AM, Jason Gunthorpe <jguntho...@obsidianresearch.com> wrote: > On Tue, Feb 21, 2017 at 10:05:42PM -0800, Moritz Fischer wrote: > >> That being said older drivers / fpga-mgr will not deal with newer features. >> TLV / KV or whatever

Re: [RFC 7/8] fpga-region: add sysfs interface

Jason, On Wed, Feb 22, 2017 at 8:44 AM, Jason Gunthorpe wrote: > On Tue, Feb 21, 2017 at 10:05:42PM -0800, Moritz Fischer wrote: > >> That being said older drivers / fpga-mgr will not deal with newer features. >> TLV / KV or whatever doesn't change this fact, or am I

Re: [RFC 7/8] fpga-region: add sysfs interface

On Wed, Feb 22, 2017 at 8:33 AM, Alan Tull <delicious.qui...@gmail.com> wrote: > On Tue, Feb 21, 2017 at 11:38 PM, Moritz Fischer > <moritz.fisc...@ettus.com> wrote: > > Hi Moritz, > >> Hi all, >> >> On Tue, Feb 21, 2017 at 9:12 PM, Jason Gunthor

Re: [RFC 7/8] fpga-region: add sysfs interface

On Wed, Feb 22, 2017 at 8:33 AM, Alan Tull wrote: > On Tue, Feb 21, 2017 at 11:38 PM, Moritz Fischer > wrote: > > Hi Moritz, > >> Hi all, >> >> On Tue, Feb 21, 2017 at 9:12 PM, Jason Gunthorpe >> wrote: >>> On Tue, Feb 21, 2017 at 07:49:19P

Re: [RFC 7/8] fpga-region: add sysfs interface

On Tue, Feb 21, 2017 at 9:46 PM, Nadathur, Sundar <sundar.nadat...@intel.com> wrote: > On February 21, 2017 9:39 PM, Moritz Fischer wrote: > >> TLV Seems easy enough. To give an update, I played with fdt a bit to see how >> far I get in half an hour. I got bool / int / st

Re: [RFC 7/8] fpga-region: add sysfs interface

On Tue, Feb 21, 2017 at 9:46 PM, Nadathur, Sundar wrote: > On February 21, 2017 9:39 PM, Moritz Fischer wrote: > >> TLV Seems easy enough. To give an update, I played with fdt a bit to see how >> far I get in half an hour. I got bool / int / strings to work quite fast >&

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi all, On Tue, Feb 21, 2017 at 9:12 PM, Jason Gunthorpe <jguntho...@obsidianresearch.com> wrote: > On Tue, Feb 21, 2017 at 07:49:19PM -0800, Moritz Fischer wrote: > >> fdt does this out of the box, too. So far I've seen nothing fdt >> couldn't do (or doesn't do let's

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi all, On Tue, Feb 21, 2017 at 9:12 PM, Jason Gunthorpe wrote: > On Tue, Feb 21, 2017 at 07:49:19PM -0800, Moritz Fischer wrote: > >> fdt does this out of the box, too. So far I've seen nothing fdt >> couldn't do (or doesn't do let's rather say). > > tlv/fdt/http hea

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi Sundar, On Tue, Feb 21, 2017 at 7:13 PM, Nadathur, Sundar wrote: >> >>> Is there a standard you are looking at? Have you seen any use of >> >>> TLV's in the Linux kernel you could point to? > > Here are some examples of TLVs in the Linux kernel: >

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi Sundar, On Tue, Feb 21, 2017 at 7:13 PM, Nadathur, Sundar wrote: >> >>> Is there a standard you are looking at? Have you seen any use of >> >>> TLV's in the Linux kernel you could point to? > > Here are some examples of TLVs in the Linux kernel: >

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi Alan, On Sun, Feb 19, 2017 at 3:16 PM, Alan Tull <delicious.qui...@gmail.com> wrote: > On Sun, Feb 19, 2017 at 9:00 AM, Alan Tull <delicious.qui...@gmail.com> wrote: >> On Sat, Feb 18, 2017 at 2:45 PM, Moritz Fischer >> <moritz.fisc...@ettus.com> wrote: >&

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi Alan, On Sun, Feb 19, 2017 at 3:16 PM, Alan Tull wrote: > On Sun, Feb 19, 2017 at 9:00 AM, Alan Tull wrote: >> On Sat, Feb 18, 2017 at 2:45 PM, Moritz Fischer >> wrote: >>> On Sat, Feb 18, 2017 at 02:10:43PM -0600, Alan Tull wrote: >>>> On Sat, Feb 1

Re: [RFC 7/8] fpga-region: add sysfs interface

On Sat, Feb 18, 2017 at 02:10:43PM -0600, Alan Tull wrote: > On Sat, Feb 18, 2017 at 6:45 AM, Nadathur, Sundar > wrote: > > > Hi all, > >Interesting discussion. The discussion so far has brought out many > > concerns such as OS independence. There is an existing

Re: [RFC 7/8] fpga-region: add sysfs interface

On Sat, Feb 18, 2017 at 02:10:43PM -0600, Alan Tull wrote: > On Sat, Feb 18, 2017 at 6:45 AM, Nadathur, Sundar > wrote: > > > Hi all, > >Interesting discussion. The discussion so far has brought out many > > concerns such as OS independence. There is an existing format, well-known > > to

Re: [RFC 7/8] fpga-region: add sysfs interface

On Fri, Feb 17, 2017 at 04:28:37PM -0600, Yves Vandervennet wrote: > Moritz, > > whatever solution we decide to go with has to work with other OS'es. The > last thing we want to do is to have wrappers that are Linux specific. I do agree that we should make sure the format is reasonably well

Re: [RFC 7/8] fpga-region: add sysfs interface

On Fri, Feb 17, 2017 at 04:28:37PM -0600, Yves Vandervennet wrote: > Moritz, > > whatever solution we decide to go with has to work with other OS'es. The > last thing we want to do is to have wrappers that are Linux specific. I do agree that we should make sure the format is reasonably well

Re: [RFC 4/8] doc: fpga-mgr: separate getting/locking FPGA manager

ga_mgr_get, fpga_mgr_get, and fpga_mgr_put no longer lock > the FPGA manager mutex. > > This makes it more straigtforward to save a reference to > a FPGA manager and only attempting to lock it when programming > the FPGA. > > Signed-off-by: Alan Tull <at...@kerne

Re: [RFC 4/8] doc: fpga-mgr: separate getting/locking FPGA manager

, and fpga_mgr_put no longer lock > the FPGA manager mutex. > > This makes it more straigtforward to save a reference to > a FPGA manager and only attempting to lock it when programming > the FPGA. > > Signed-off-by: Alan Tull Acked-by: Moritz Fischer > -

Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

Partial Reconfiguraion IP? >> >> Signed-off-by: Matthew Gerlach <matthew.gerl...@linux.intel.com> Acked-By: Moritz Fischer <m...@kernel.org> >> --- >> Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 >> 1 file changed, 12 inse

Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

Matthew, On Fri, Feb 17, 2017 at 5:31 AM, Dinh Nguyen wrote: > On Wed, Feb 15, 2017 at 3:10 PM, wrote: >> From: Matthew Gerlach >> >> Device Tree bindings for Altera Partial Reconfiguraion IP? >> >> Signed-off-by: Matthew Gerlach Acked-By: Moritz Fischer &g

Re: [RFC 7/8] fpga-region: add sysfs interface

On Thu, Feb 16, 2017 at 9:56 AM, Jason Gunthorpe wrote: > On Thu, Feb 16, 2017 at 11:47:08AM -0600, Alan Tull wrote: > >> > Just to clarify: I was proposing using the binary format of dts, >> > not actually requiring devicetree for it to work. There's plenty >> >

Re: [RFC 7/8] fpga-region: add sysfs interface

On Thu, Feb 16, 2017 at 9:56 AM, Jason Gunthorpe wrote: > On Thu, Feb 16, 2017 at 11:47:08AM -0600, Alan Tull wrote: > >> > Just to clarify: I was proposing using the binary format of dts, >> > not actually requiring devicetree for it to work. There's plenty >> > of people running u-boot on x86

Re: [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

Hi Matthew, On Wed, Feb 15, 2017 at 1:10 PM, wrote: > +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + u32 i; > + > + for (i = 0; i <

Re: [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

Hi Matthew, On Wed, Feb 15, 2017 at 1:10 PM, wrote: > +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + u32 i; > + > + for (i = 0; i < info->config_complete_timeout_us; i++) { > +

Re: [RFC 7/8] fpga-region: add sysfs interface

On Wed, Feb 15, 2017 at 2:42 PM, Alan Tull <delicious.qui...@gmail.com> wrote: > On Wed, Feb 15, 2017 at 3:36 PM, Moritz Fischer > <moritz.fisc...@ettus.com> wrote: >> Jason, >> >> On Wed, Feb 15, 2017 at 1:15 PM, Jason Gunthorpe >> <jguntho...@obsidian

Re: [RFC 7/8] fpga-region: add sysfs interface

On Wed, Feb 15, 2017 at 2:42 PM, Alan Tull wrote: > On Wed, Feb 15, 2017 at 3:36 PM, Moritz Fischer > wrote: >> Jason, >> >> On Wed, Feb 15, 2017 at 1:15 PM, Jason Gunthorpe >> wrote: >>> On Wed, Feb 15, 2017 at 12:54:27PM -0800, Moritz Fi

Re: [PATCH] net: ethernet: cadence: Add fixed-link functionality

Andrew, On Wed, Feb 15, 2017 at 2:12 PM, Andrew Lunn wrote: >> @@ -3342,8 +3371,18 @@ static int macb_probe(struct platform_device *pdev) >> macb_get_hwaddr(bp); >> >> /* Power up the PHY if there is a GPIO reset */ >> - phy_node =

Re: [PATCH] net: ethernet: cadence: Add fixed-link functionality

Andrew, On Wed, Feb 15, 2017 at 2:12 PM, Andrew Lunn wrote: >> @@ -3342,8 +3371,18 @@ static int macb_probe(struct platform_device *pdev) >> macb_get_hwaddr(bp); >> >> /* Power up the PHY if there is a GPIO reset */ >> - phy_node = of_get_next_available_child(np, NULL);

Re: [RFC 7/8] fpga-region: add sysfs interface

Jason, On Wed, Feb 15, 2017 at 1:15 PM, Jason Gunthorpe <jguntho...@obsidianresearch.com> wrote: > On Wed, Feb 15, 2017 at 12:54:27PM -0800, Moritz Fischer wrote: > >> Well I don't know ;-) With something fdt based we already have >> parsers there, > > Not sure

Re: [RFC 7/8] fpga-region: add sysfs interface

Jason, On Wed, Feb 15, 2017 at 1:15 PM, Jason Gunthorpe wrote: > On Wed, Feb 15, 2017 at 12:54:27PM -0800, Moritz Fischer wrote: > >> Well I don't know ;-) With something fdt based we already have >> parsers there, > > Not sure.. How does incbin work in DTB? > > We

Re: [PATCH] net: ethernet: cadence: Add fixed-link functionality

Hi Florian, thanks for the quick reply. On Wed, Feb 15, 2017 at 12:57 PM, Florian Fainelli <f.faine...@gmail.com> wrote: > On 02/15/2017 12:44 PM, m...@kernel.org wrote: >> From: Moritz Fischer <m...@kernel.org> >> >> This allows 'fixed-link' dire

Re: [PATCH] net: ethernet: cadence: Add fixed-link functionality

Hi Florian, thanks for the quick reply. On Wed, Feb 15, 2017 at 12:57 PM, Florian Fainelli wrote: > On 02/15/2017 12:44 PM, m...@kernel.org wrote: >> From: Moritz Fischer >> >> This allows 'fixed-link' direct MAC connections to be declared >> in devicetree. >>

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi Jason, On Wed, Feb 15, 2017 at 12:37 PM, Jason Gunthorpe wrote: > On Wed, Feb 15, 2017 at 12:07:15PM -0800, matthew.gerl...@linux.intel.com > wrote: > >> The format of the meta data associated with a fpga bitstream is certainly a >> subject on its own. HTTP

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi Jason, On Wed, Feb 15, 2017 at 12:37 PM, Jason Gunthorpe wrote: > On Wed, Feb 15, 2017 at 12:07:15PM -0800, matthew.gerl...@linux.intel.com > wrote: > >> The format of the meta data associated with a fpga bitstream is certainly a >> subject on its own. HTTP style plain text is definately

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi Jason, Alan On Wed, Feb 15, 2017 at 7:23 PM, Alan Tull wrote: >> This is usually the sort of stuff I'd punt to userspace, but since the >> kernel is doing request_firmware it is hard to see how that is an >> option in this case... > > I like how extensible (and

Re: [RFC 7/8] fpga-region: add sysfs interface

Hi Jason, Alan On Wed, Feb 15, 2017 at 7:23 PM, Alan Tull wrote: >> This is usually the sort of stuff I'd punt to userspace, but since the >> kernel is doing request_firmware it is hard to see how that is an >> option in this case... > > I like how extensible (and readable!) this is. It

Re: [PATCH 1/2] fpga: Add flag to indicate bitstream needs decrypting

On Wed, Feb 15, 2017 at 5:30 PM, Alan Tull wrote: > On Wed, Feb 15, 2017 at 9:03 AM, Michal Simek wrote: >>> #define FPGA_MGR_PARTIAL_RECONFIGBIT(0) >>> #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) >>> +#define FPGA_MGR_DECRYPT_BITSTREAM BIT(2)

Re: [PATCH 1/2] fpga: Add flag to indicate bitstream needs decrypting

On Wed, Feb 15, 2017 at 5:30 PM, Alan Tull wrote: > On Wed, Feb 15, 2017 at 9:03 AM, Michal Simek wrote: >>> #define FPGA_MGR_PARTIAL_RECONFIGBIT(0) >>> #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) >>> +#define FPGA_MGR_DECRYPT_BITSTREAM BIT(2) >>> >>> /** >>> * struct fpga_image_info

Re: [RFC 7/8] fpga-region: add sysfs interface

On Wed, Feb 15, 2017 at 11:46:01AM -0600, Alan Tull wrote: > On Wed, Feb 15, 2017 at 11:21 AM, Jason Gunthorpe > wrote: > > On Wed, Feb 15, 2017 at 10:14:20AM -0600, Alan Tull wrote: > >> Add a sysfs interface to control programming FPGA. > >> > >> Each

Re: [RFC 7/8] fpga-region: add sysfs interface

On Wed, Feb 15, 2017 at 11:46:01AM -0600, Alan Tull wrote: > On Wed, Feb 15, 2017 at 11:21 AM, Jason Gunthorpe > wrote: > > On Wed, Feb 15, 2017 at 10:14:20AM -0600, Alan Tull wrote: > >> Add a sysfs interface to control programming FPGA. > >> > >> Each fpga-region will get the following files

Re: [PATCH v3 fpga 3/4] fpga: Add scatterlist based programming

Hi Jason, On Fri, Jan 27, 2017 at 10:58 PM, Jason Gunthorpe wrote: > On Mon, Jan 09, 2017 at 04:13:38PM -0600, Alan Tull wrote: >> On Mon, Jan 9, 2017 at 10:12 AM, Jason Gunthorpe >> wrote: >> > On Mon, Jan 09, 2017 at 10:04:36AM

Re: [PATCH v3 fpga 3/4] fpga: Add scatterlist based programming

Hi Jason, On Fri, Jan 27, 2017 at 10:58 PM, Jason Gunthorpe wrote: > On Mon, Jan 09, 2017 at 04:13:38PM -0600, Alan Tull wrote: >> On Mon, Jan 9, 2017 at 10:12 AM, Jason Gunthorpe >> wrote: >> > On Mon, Jan 09, 2017 at 10:04:36AM -0600, Alan Tull wrote: >> > >> >> > diff --git

Re: [PATCH v3 fpga 4/4] fpga zynq: Use the scatterlist interface

d in. > > Since this is now a gather DMA operation the driver uses the ISR > to feed the chips DMA queue with each entry from the SGL. > > Signed-off-by: Jason Gunthorpe <jguntho...@obsidianresearch.com> Acked-by: Moritz Fischer <moritz.fisc...@ettus.com> Thanks, Moritz

Re: [PATCH v3 fpga 4/4] fpga zynq: Use the scatterlist interface

r DMA operation the driver uses the ISR > to feed the chips DMA queue with each entry from the SGL. > > Signed-off-by: Jason Gunthorpe Acked-by: Moritz Fischer Thanks, Moritz

Re: [PATCH] ARM64: zynqmp: Fix i2c node's compatible string

Hi Michal, On Wed, Dec 21, 2016 at 11:35 PM, Michal Simek wrote: > compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; I keep getting that wrong .. .damn ... :) Will resubmit. > The same of course for u-boot where also p14 should be added to the driver. Yeah, I realized

Re: [PATCH] ARM64: zynqmp: Fix i2c node's compatible string

Hi Michal, On Wed, Dec 21, 2016 at 11:35 PM, Michal Simek wrote: > compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; I keep getting that wrong .. .damn ... :) Will resubmit. > The same of course for u-boot where also p14 should be added to the driver. Yeah, I realized that part after

[PATCH] ARM64: zynqmp: Fix i2c node's compatible string

From: Moritz Fischer <m...@kernel.org> The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core which fixes some silicon bugs that needed software workarounds in Version 1.0 that was used on Zynq systems. Signed-off-by: Moritz Fischer <m...@kernel.org> Cc: Michal Sime

[PATCH] ARM64: zynqmp: Fix i2c node's compatible string

From: Moritz Fischer The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core which fixes some silicon bugs that needed software workarounds in Version 1.0 that was used on Zynq systems. Signed-off-by: Moritz Fischer Cc: Michal Simek Cc: Sören Brinkmann Cc: U-Boot List Cc: Rob Herring

Re: [PATCH v4 1/2] FPGA: Add TS-7300 FPGA manager

gt; + .write = ts73xx_fpga_write, >> + .write_complete = ts73xx_fpga_write_complete, >> +}; >> + >> +static int ts73xx_fpga_probe(struct platform_device *pdev) >> +{ >> + struct device *kdev = >dev; >> + struct ts73xx_fpga_priv *priv; >> + struct resource *res; >> + int err; >> + >> + priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL); >> + if (!priv) >> + return -ENOMEM; >> + >> + priv->dev = kdev; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + priv->io_base = devm_ioremap_resource(kdev, res); >> + if (IS_ERR(priv->io_base)) { >> + dev_err(kdev, "unable to remap registers\n"); >> + return PTR_ERR(priv->io_base); >> + } >> + >> + err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager", >> + _fpga_ops, priv); >> + if (err) { >> + dev_err(kdev, "failed to register FPGA manager\n"); >> + return err; >> + } > > > You can just 'return fpga_mgr_register(..); here. > > Thanks for your responsiveness. You can leave things up longer so > that people have time to review. That way you don't have to go > through so many versions so quickly. > > Acked-by: Alan Tull <at...@opensource.altera.com> Acked-by: Moritz Fischer <moritz.fisc...@ettus.com> Cheers, Moritz

Re: [PATCH v4 1/2] FPGA: Add TS-7300 FPGA manager

xx_fpga_write_complete, >> +}; >> + >> +static int ts73xx_fpga_probe(struct platform_device *pdev) >> +{ >> + struct device *kdev = >dev; >> + struct ts73xx_fpga_priv *priv; >> + struct resource *res; >> + int err; >> + >> + priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL); >> + if (!priv) >> + return -ENOMEM; >> + >> + priv->dev = kdev; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + priv->io_base = devm_ioremap_resource(kdev, res); >> + if (IS_ERR(priv->io_base)) { >> + dev_err(kdev, "unable to remap registers\n"); >> + return PTR_ERR(priv->io_base); >> + } >> + >> + err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager", >> + _fpga_ops, priv); >> + if (err) { >> + dev_err(kdev, "failed to register FPGA manager\n"); >> + return err; >> + } > > > You can just 'return fpga_mgr_register(..); here. > > Thanks for your responsiveness. You can leave things up longer so > that people have time to review. That way you don't have to go > through so many versions so quickly. > > Acked-by: Alan Tull Acked-by: Moritz Fischer Cheers, Moritz

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