>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
>Sent: Monday, August 21, 2017 20:04 PM
>> +
>> +/* Handle an out of bounds mtm hs counter value */ static void __init
>> +handle_mtm_hs_ctr_out_of_bounds_error(uint8_t val) {
>> +pr_err("** The value must be in range [%d,%d]
>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
>Sent: Monday, August 21, 2017 20:04 PM
>> +
>> +/* Handle an out of bounds mtm hs counter value */ static void __init
>> +handle_mtm_hs_ctr_out_of_bounds_error(uint8_t val) {
>> +pr_err("** The value must be in range [%d,%d]
From: Noam Camus <noa...@mellanox.com>
Change Log:
V2 -> V3
1) turn ARC prink's into pr_info as suggested by Vineet
2) For new command line argument (hs counter) shorten error massage to a single
line,
again as Vineet commented.
V1 -> V2
1) I added "Handle memory error as an
From: Noam Camus
Change Log:
V2 -> V3
1) turn ARC prink's into pr_info as suggested by Vineet
2) For new command line argument (hs counter) shorten error massage to a single
line,
again as Vineet commented.
V1 -> V2
1) I added "Handle memory error as an exception" patch f
From: Noam Camus <noa...@mellanox.com>
Now it can be hidden by passing higher loglevel sevirity at cmdline
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
From: Noam Camus
Now it can be hidden by passing higher loglevel sevirity at cmdline
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
From: Noam Camus <no...@ezchip.com>
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
c
parent value.
Signed-off-by: Noam Camus <no...@ezchip.com>
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff
From: Noam Camus
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while
-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/entry-compact.h
b/arch
From: Noam Camus <no...@ezchip.com>
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to r
From: Noam Camus
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to restore last one and pop
na <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch/arc/plat-eznps/Kconfig | 11 +++
arch/arc/plat-eznps/entry.S |2 +-
2 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
inde
that implement a different set of auxiliary registers
disabling this configuration insures that we initialize registers on
every cpu and not just for the first thread of the core.
Example for non shared registers is working with EZsim (non silicon)
Signed-off-by: Liav Rehana
Signed-off-by: Noam
From: Noam Camus <noa...@mellanox.com>
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HW scheduler.
Signed-off-by: Noam Camu
From: Noam Camus
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HW scheduler.
Signed-off-by: Noam Camus
---
Documentation/admin-guide/kernel
hanged afterwards.
Signed-off-by: Elad Kanfi <elad...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch/arc/plat-eznps/include/plat/ctop.h |1 +
arch/arc/plat-eznps/mtm.c | 12
2 files changed, 13 insertions(+), 0 deletions(-)
diff --g
From: Noam Camus <noa...@mellanox.com>
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch/arc/Kconfig
-by: Elad Kanfi
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/include/plat/ctop.h |1 +
arch/arc/plat-eznps/mtm.c | 12
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h
b/arch/arc/plat-eznps/include/plat
From: Noam Camus
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig | 11 +++
arch/arc/include/asm/highmem.h |8
From: Noam Camus <noa...@mellanox.com>
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch
From: Noam Camus
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig| 27
arch/arc
From: Noam Camus <noa...@mellanox.com>
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. a
From: Noam Camus <noa...@mellanox.com>
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Sign
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
From: Noam Camus
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed
thread in each core.
On platforms that implement a different set of auxiliary registers
there is a need to initialize them on every cpu and not just the for the
first thread of the core.
Signed-off-by: Liav Rehana <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
a
.
On platforms that implement a different set of auxiliary registers
there is a need to initialize them on every cpu and not just the for the
first thread of the core.
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/Kconfig | 11 +++
arch/arc/plat-eznps/entry.S |2
From: Noam Camus <no...@ezchip.com>
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
c
From: Noam Camus
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while
From: Noam Camus <noa...@mellanox.com>
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch/arc/Kconfig
From: Noam Camus <noa...@mellanox.com>
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. a
From: Noam Camus
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed
From: Noam Camus
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig | 11 +++
arch/arc/include/asm/highmem.h |8
From: Noam Camus <noa...@mellanox.com>
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.
Signed-off-by: Noam Camu
From: Noam Camus <noa...@mellanox.com>
On ARC700, user mode memory error is treated as L2 interrupt, but NPS
hardware treats it as Machine Check exception.
Address this by defining an NPS specific bus error handler.
Signed-off-by: Noam Camus <noa...@mellanox.com>
Signed-off-by: Elad
From: Noam Camus
On ARC700, user mode memory error is treated as L2 interrupt, but NPS
hardware treats it as Machine Check exception.
Address this by defining an NPS specific bus error handler.
Signed-off-by: Noam Camus
Signed-off-by: Elad Kanfi
---
arch/arc/kernel/traps.c |2
From: Noam Camus
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.
Signed-off-by: Noam Camus
---
Documentation/admin-guide/kernel
From: Noam Camus <noa...@mellanox.com>
Chanlog:
V1 -> V2
1) I added "Handle memory error as an exception" patch from previous set
It now turn do_memory_error() into weak sybol.
It is then overriden by NPS400 platform, to simply call die().
2) This set is now based on arc-
From: Noam Camus
Chanlog:
V1 -> V2
1) I added "Handle memory error as an exception" patch from previous set
It now turn do_memory_error() into weak sybol.
It is then overriden by NPS400 platform, to simply call die().
2) This set is now based on arc-next branch
Summary:
With t
From: Noam Camus <noa...@mellanox.com>
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Sign
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
parent value.
Signed-off-by: Noam Camus <no...@ezchip.com>
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff
From: Noam Camus <no...@ezchip.com>
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to r
From: Noam Camus
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to restore last one and pop
-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/entry-compact.h
b/arch
hanged afterwards.
Signed-off-by: Elad Kanfi <elad...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch/arc/plat-eznps/include/plat/ctop.h |1 +
arch/arc/plat-eznps/mtm.c | 12
2 files changed, 13 insertions(+), 0 deletions(-)
diff --g
From: Noam Camus <noa...@mellanox.com>
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch
From: Noam Camus <noa...@mellanox.com>
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus <noa...@mel
-by: Elad Kanfi
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/include/plat/ctop.h |1 +
arch/arc/plat-eznps/mtm.c | 12
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h
b/arch/arc/plat-eznps/include/plat
From: Noam Camus
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig| 27
arch/arc
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6
From: Noam Camus <noa...@mellanox.com>
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus <noa...@mel
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6
From: Noam Camus <no...@ezchip.com>
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to r
parent value.
Signed-off-by: Noam Camus <no...@ezchip.com>
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff
From: Noam Camus
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to restore last one and pop
-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/entry-compact.h
b/arch
From: Noam Camus <noa...@mellanox.com>
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.
Signed-off-by: Noam Camu
hanged afterwards.
Signed-off-by: Elad Kanfi <elad...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch/arc/plat-eznps/include/plat/ctop.h |1 +
arch/arc/plat-eznps/mtm.c | 12
2 files changed, 13 insertions(+), 0 deletions(-)
diff --g
-by: Elad Kanfi
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/include/plat/ctop.h |1 +
arch/arc/plat-eznps/mtm.c | 12
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h
b/arch/arc/plat-eznps/include/plat
From: Noam Camus
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.
Signed-off-by: Noam Camus
---
Documentation/admin-guide/kernel
From: Noam Camus <no...@ezchip.com>
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
c
thread in each core.
On platforms that implement a different set of auxiliary registers
there is a need to initialize them on every cpu and not just the for the
first thread of the core.
Signed-off-by: Liav Rehana <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
a
From: Noam Camus
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while
.
On platforms that implement a different set of auxiliary registers
there is a need to initialize them on every cpu and not just the for the
first thread of the core.
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/Kconfig | 11 +++
arch/arc/plat-eznps/entry.S |2
From: Noam Camus <noa...@mellanox.com>
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch
From: Noam Camus
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig| 27
arch/arc
From: Noam Camus <noa...@mellanox.com>
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch/arc/Kconfig
From: Noam Camus
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig | 11 +++
arch/arc/include/asm/highmem.h |8
From: Noam Camus <noa...@mellanox.com>
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. a
From: Noam Camus
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed
From: Noam Camus <noa...@mellanox.com>
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Sign
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
From: Noam Camus <noa...@mellanox.com>
With this patch set I continue the effort of upstreaming the eznps platform for
arch/arc.
It comprise of couple of patches from last set yet not accepted,
patches for HW erratas and some misc extensions such for HIGHMEM / NUMA.
This set got more g
From: Noam Camus
With this patch set I continue the effort of upstreaming the eznps platform for
arch/arc.
It comprise of couple of patches from last set yet not accepted,
patches for HW erratas and some misc extensions such for HIGHMEM / NUMA.
This set got more generic ARC changes than
> From: Noam Camus
> Sent: Wednesday, June 7, 2017 9:08 AM
>To: 'Vineet Gupta' <vineet.gup...@synopsys.com>;
>linux-snps-...@lists.infradead.org
>Cc: linux-kernel@vger.kernel.org; Elad Kanfi <elad...@mellanox.com>
>Subject: RE: [PATCH v2 11/11] ARC: [p
> From: Noam Camus
> Sent: Wednesday, June 7, 2017 9:08 AM
>To: 'Vineet Gupta' ;
>linux-snps-...@lists.infradead.org
>Cc: linux-kernel@vger.kernel.org; Elad Kanfi
>Subject: RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an
>exception
>>From: Vine
>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
>Sent: Wednesday, June 7, 2017 1:11 AM
...
>> +
>> +config EZNPS_MEM_ERROR
>> + bool "ARC-EZchip Memory error as an exception"
>> + depends on ARC_PLAT_EZNPS
>> + default n
>So you set default to "n" - thus by default it
>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
>Sent: Wednesday, June 7, 2017 1:11 AM
...
>> +
>> +config EZNPS_MEM_ERROR
>> + bool "ARC-EZchip Memory error as an exception"
>> + depends on ARC_PLAT_EZNPS
>> + default n
>So you set default to "n" - thus by default it
> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
> Sent: Friday, June 2, 2017 21:36 PM
...
>> arch/arc/include/asm/spinlock.h |6 ++
>> 1 files changed, 6 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arc/include/asm/spinlock.h
>> b/arch/arc/include/asm/spinlock.h
> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
> Sent: Friday, June 2, 2017 21:36 PM
...
>> arch/arc/include/asm/spinlock.h |6 ++
>> 1 files changed, 6 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arc/include/asm/spinlock.h
>> b/arch/arc/include/asm/spinlock.h
> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
> Sent: Friday, June 2, 2017 22:04 PM
>> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
>> index feaa471..c5f946c 100644
>> --- a/arch/arc/plat-eznps/Kconfig
>> +++ b/arch/arc/plat-eznps/Kconfig
>> @@ -32,3 +32,14
> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
> Sent: Friday, June 2, 2017 22:04 PM
>> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
>> index feaa471..c5f946c 100644
>> --- a/arch/arc/plat-eznps/Kconfig
>> +++ b/arch/arc/plat-eznps/Kconfig
>> @@ -32,3 +32,14
From: Noam Camus <noa...@mellanox.com>
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus <noa...@mel
From: Noam Camus <noa...@mellanox.com>
Change Log
---
v1 --> v2:
Outcome of Alexey Brodkin comments
1) Turned mem_service into weak symbol, so it can be override
by any platform
2) remove ifedf wrapper on '88' lable at assembly of TLB exception.
With this patch set I continue t
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6
From: Noam Camus
Change Log
---
v1 --> v2:
Outcome of Alexey Brodkin comments
1) Turned mem_service into weak symbol, so it can be override
by any platform
2) remove ifedf wrapper on '88' lable at assembly of TLB exception.
With this patch set I continue the effort of upstream
From: Noam Camus <noa...@mellanox.com>
When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all
From: Noam Camus <noa...@mellanox.com>
This counter represents threshold for consecutive stall that which
trigger HW threads scheduling.
When this feature is enabled low values of this counter cause
downgrade in performance and in the worst case even a livelock.
Remove those couple of
From: Noam Camus
When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all other are still awake
and can
From: Noam Camus
This counter represents threshold for consecutive stall that which
trigger HW threads scheduling.
When this feature is enabled low values of this counter cause
downgrade in performance and in the worst case even a livelock.
Remove those couple of lines and resort to HW reset
From: Noam Camus <noa...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
Reviewed-by: Alexey Brodkin <abrod...@synopsys.com>
---
arch/arc/plat-eznps/Kconfig |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arc/plat-eznps/Kconfig b/a
From: Noam Camus
Signed-off-by: Noam Camus
Reviewed-by: Alexey Brodkin
---
arch/arc/plat-eznps/Kconfig |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 1595a38..feaa471 100644
--- a/arch/arc/plat-eznps
From: Noam Camus <noa...@mellanox.com>
This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.
We noticed about 10% improvement of execution time with hackbench test.
Signed-off-by:
From: Noam Camus <noa...@mellanox.com>
Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
arch/arc/mm/tlbex.S |9 +
1 files changed, 9 insertions(+), 0 deleti
From: Noam Camus <noa...@mellanox.com>
For User Mode Memory Bus Error some platforms do not creat interrupt
level 2 e.g. nps400 creates machine check exception.
Turning mem_service into weak symbol allows each platform to override
mem_service with its own implementation.
Signed-off-by
From: Noam Camus
This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.
We noticed about 10% improvement of execution time with hackbench test.
Signed-off-by: Noam Camus
---
arch/arc/i
From: Noam Camus
Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.
Signed-off-by: Noam Camus
---
arch/arc/mm/tlbex.S |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm
From: Noam Camus
For User Mode Memory Bus Error some platforms do not creat interrupt
level 2 e.g. nps400 creates machine check exception.
Turning mem_service into weak symbol allows each platform to override
mem_service with its own implementation.
Signed-off-by: Noam Camus
---
arch/arc
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