Re: [PATCH v5 01/11] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC

rs Cheng > > Signed-off-by: Owen Chen > > --- > > .../bindings/arm/mediatek/mediatek,apmixedsys.txt |1 + > > .../bindings/arm/mediatek/mediatek,audsys.txt |1 + > > .../bindings/arm/mediatek/mediatek,camsys.txt | 27 > >

Re: [PATCH v5 09/11] clk: mediatek: add new clkmux register API

On Thu, 2018-07-19 at 14:57 +0800, Sean Wang wrote: > On Tue, 2018-07-17 at 16:52 +0800, Mars Cheng wrote: > > From: Owen Chen > > > > MT6765 add "set/clr" register for each clkmux setting, and > > one update register to trigger value change. It is desi

Re: [PATCH v5 06/11] soc: mediatek: add new flow for mtcmos power.

Hi Matthias On Wed, 2018-07-18 at 16:50 +0200, Matthias Brugger wrote: > > On 17/07/18 10:52, Mars Cheng wrote: > > From: Owen Chen > > > > MT6765 need multiple register and actions to setup bus > > protect. > > 1. turn on subsys CG before release bus protec