frequency
So this patch adds parameter tck-rate to set user defined values from
above pool to control the clock frequency.
Signed-off-by: Ranjit Waghmode
---
Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation
frequency
So this patch adds parameter tck-rate to set user defined values from
above pool to control the clock frequency.
Signed-off-by: Ranjit Waghmode <ranjit.waghm...@xilinx.com>
---
Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt | 7 +++
1 file changed, 7 insertions(+)
, sector_size, erase_size and toatal flash size
as and when required.
- Dividing address by 2
- Updating spi->master->flags for qspi driver to change CS
Signed-off-by: Ranjit Waghmode
---
V3 Changes:
- No change in this patch
V2 Changes:
- Splitted to separate MTD layer change
This patch adds struct spi_device instacne to the spi_nor structure.
Signed-off-by: Ranjit Waghmode
---
V3 Changes:
- No change in this patch
V2 Changes:
- This is new patch, basically splitted on request of Mark Brown
---
drivers/mtd/devices/m25p80.c | 1 +
include/linux/mtd
This patch adds support of dual parallel mode configuration
for Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode
---
V3 Changes:
- No change in this patch
V2 Changes:
- No change in this patch
---
drivers/spi/spi-zynqmp-gqspi.c | 24
bytes i.e. 1, 3, 5,.. are transmitted on upper data bus.
To support data stripe; need to assert both chip selects once.
This is achieved throught API SPI_MASTER_BOTH_CS.
Signed-off-by: Ranjit Waghmode
---
V3 Changes:
- Updated comments for newly added APIs.
- Changed patch
clear.
---
V3 Changes:
- Changed couple of comments to remove ambiguity in understanding
V2 Changes:
a) Splitted patches based on logical changes
b) Added error handling for newly added APIs in SPI core
---
Ranjit Waghmode (4):
spi: addng support for data stripe feature in core
mtd: add spi_
, sector_size, erase_size and toatal flash size
as and when required.
- Dividing address by 2
- Updating spi->master->flags for qspi driver to change CS
Signed-off-by: Ranjit Waghmode <ranjit.waghm...@xilinx.com>
---
V3 Changes:
- No change in this patch
V2 Changes:
bytes i.e. 1, 3, 5,.. are transmitted on upper data bus.
To support data stripe; need to assert both chip selects once.
This is achieved throught API SPI_MASTER_BOTH_CS.
Signed-off-by: Ranjit Waghmode <ranjit.waghm...@xilinx.com>
---
V3 Changes:
- Updated comments for newly adde
clear.
---
V3 Changes:
- Changed couple of comments to remove ambiguity in understanding
V2 Changes:
a) Splitted patches based on logical changes
b) Added error handling for newly added APIs in SPI core
---
Ranjit Waghmode (4):
spi: addng support for data stripe feature in core
mtd: add spi_
This patch adds support of dual parallel mode configuration
for Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode <ranjit.waghm...@xilinx.com>
---
V3 Changes:
- No change in this patch
V2 Changes:
- No change in this patch
---
drivers/spi/spi-
This patch adds struct spi_device instacne to the spi_nor structure.
Signed-off-by: Ranjit Waghmode <ranjit.waghm...@xilinx.com>
---
V3 Changes:
- No change in this patch
V2 Changes:
- This is new patch, basically splitted on request of Mark Brown
---
drivers/mtd/devices/
of the above issue by updating 'channels' structure
inside xadc_parse_dt() function with the help of 'xadc_channels' structure
so that every channel's parameters will be updated properly. Also for the
sake of simplicity this patch updates default values for extend_name.
Signed-off-by: Ranjit Waghmode
of the above issue by updating 'channels' structure
inside xadc_parse_dt() function with the help of 'xadc_channels' structure
so that every channel's parameters will be updated properly. Also for the
sake of simplicity this patch updates default values for extend_name.
Signed-off-by: Ranjit Waghmode
This patch adds support of dual parallel mode configuration
for Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode
---
V2 Changes:
- No change in this patch
---
drivers/spi/spi-zynqmp-gqspi.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion
mments and suggestions are always welcomed
---
V2 Changes:
a) Splitted patches based on logical changes
b) Added error handling for newly added APIs in SPI core
---
Ranjit Waghmode (4):
spi: add support of two chip selects & data stripe
mtd: add spi_device instance to spi_nor struct
spi-nor
, erase_size and toatal flash size
as and when required.
- Dividing address by 2
- Updating spi->master->flags for qspi driver to change CS
Signed-off-by: Ranjit Waghmode
---
V2 Changes:
Splitted to separate MTD layer changes from SPI core changes
---
drivers/mtd/spi-nor/spi-nor.
This patch adds struct spi_device instacne to the spi_nor structure
Signed-off-by: Ranjit Waghmode
---
V2 Changes:
This is new patch, basically splitted on request of Mark Brown
---
drivers/mtd/devices/m25p80.c | 1 +
include/linux/mtd/spi-nor.h | 1 +
2 files changed, 2 insertions(+)
diff
the flash devices.
So newly added API will help in enabling both the chips.
- Added API to support data stripe feature:
with data stripe enabled,
even bytes i.e. 0, 2, 4,... are transmitted on lower data bus
odd bytes i.e. 1, 3, 5,.. are transmitted on upper data bus.
Signed-off-by: Ranjit
This patch adds support of dual parallel mode configuration
for Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
V2 Changes:
- No change in this patch
---
drivers/spi/spi-zynqmp-gqspi.c | 24 +++-
1 file changed, 23
This patch adds struct spi_device instacne to the spi_nor structure
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
V2 Changes:
This is new patch, basically splitted on request of Mark Brown
---
drivers/mtd/devices/m25p80.c | 1 +
include/linux/mtd/spi-nor.h | 1 +
2 files changed
and suggestions are always welcomed
---
V2 Changes:
a) Splitted patches based on logical changes
b) Added error handling for newly added APIs in SPI core
---
Ranjit Waghmode (4):
spi: add support of two chip selects data stripe
mtd: add spi_device instance to spi_nor struct
spi-nor: add dual
the flash devices.
So newly added API will help in enabling both the chips.
- Added API to support data stripe feature:
with data stripe enabled,
even bytes i.e. 0, 2, 4,... are transmitted on lower data bus
odd bytes i.e. 1, 3, 5,.. are transmitted on upper data bus.
Signed-off-by: Ranjit
, erase_size and toatal flash size
as and when required.
- Dividing address by 2
- Updating spi-master-flags for qspi driver to change CS
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
V2 Changes:
Splitted to separate MTD layer changes from SPI core changes
---
drivers/mtd/spi-nor
This patch adds support of dual parallel mode configuration for
Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode
---
drivers/spi/spi-zynqmp-gqspi.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-zynqmp
functions by:
a) Increasing page_size, sector_size, erase_size and toatal flash size
as and when required.
b) Dividing address by 2
c) Updating spi->master->flags for qspi driver to change CS
- Added defines for data stripe and two flash support
Signed-off-by: Ranjit Waghmode
---
d
e very high level changes and expected to make an idea clear.
Comments and suggestions are always welcomed.
Ranjit Waghmode (2):
mtd: spi-nor: add dual parallel mode support
spi: zynqmp: gqspi: add support for dual parallel mode configuration
drivers/mtd/devices/m25p80.c | 1 +
drivers/m
high level changes and expected to make an idea clear.
Comments and suggestions are always welcomed.
Ranjit Waghmode (2):
mtd: spi-nor: add dual parallel mode support
spi: zynqmp: gqspi: add support for dual parallel mode configuration
drivers/mtd/devices/m25p80.c | 1 +
drivers/mtd/spi-nor
This patch adds support of dual parallel mode configuration for
Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
drivers/spi/spi-zynqmp-gqspi.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git
functions by:
a) Increasing page_size, sector_size, erase_size and toatal flash size
as and when required.
b) Dividing address by 2
c) Updating spi-master-flags for qspi driver to change CS
- Added defines for data stripe and two flash support
Signed-off-by: Ranjit Waghmode ranjit.waghm
This patch adds support of dual parallel mode configuration for
Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode
---
drivers/spi/spi-zynqmp-gqspi.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-zynqmp
dependencies.
Ranjit Waghmode (2):
spi: zynqmp: gqspi: add support for dual parallel mode configuration
spi: zynqmp: gqspi: add support for stacked mode configuration
drivers/spi/spi-zynqmp-gqspi.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
--
2.1.2
This patch adds support of stacked mode configuration for
Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode
---
drivers/spi/spi-zynqmp-gqspi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
This patch adds support of stacked mode configuration for
Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
drivers/spi/spi-zynqmp-gqspi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers
dependencies.
Ranjit Waghmode (2):
spi: zynqmp: gqspi: add support for dual parallel mode configuration
spi: zynqmp: gqspi: add support for stacked mode configuration
drivers/spi/spi-zynqmp-gqspi.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
--
2.1.2
This patch adds support of dual parallel mode configuration for
Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
drivers/spi/spi-zynqmp-gqspi.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git
This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode
---
In v3, accommodating review comments given by Shubhrajyoti.
Changes in v3:
- Updated chip assert/de-assert timeout loop using jiffies
- Updated minor kernel doc comments
Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode
---
Changes in v3:
- Did split in register addressing as per Sorens request
Changes in v2:
No changes in v2
---
.../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26
Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
Changes in v3:
- Did split in register addressing as per Sorens request
Changes in v2:
No changes in v2
---
.../devicetree/bindings/spi/spi-zynqmp
This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
In v3, accommodating review comments given by Shubhrajyoti.
Changes in v3:
- Updated chip assert/de-assert timeout loop using jiffies
- Updated minor
This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode
---
Here is the v2 series.
Following comments are not taken care in this version:
a) Comment from Mark Brown regarding DMA manual mapping-
This QSPI DMA only supports RX and not TX
Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode
---
No changes in v2
---
.../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26 ++
1 file changed, 26 insertions(+)
create mode 100644 Documentation
This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
Here is the v2 series.
Following comments are not taken care in this version:
a) Comment from Mark Brown regarding DMA manual mapping-
This QSPI DMA
Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
No changes in v2
---
.../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26 ++
1 file changed, 26 insertions(+)
create mode
Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode
---
.../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26 ++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi
This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode
---
drivers/spi/Kconfig|6 +
drivers/spi/Makefile |1 +
drivers/spi/spi-zynqmp-gqspi.c | 1092
3 files changed
This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
drivers/spi/Kconfig|6 +
drivers/spi/Makefile |1 +
drivers/spi/spi-zynqmp-gqspi.c | 1092
Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
.../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26 ++
1 file changed, 26 insertions(+)
create mode 100644 Documentation
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