On 07.09.15 18:09:48, Marc Zyngier wrote:
> On 07/09/15 17:54, Suzuki K. Poulose wrote:
> > On 14/08/15 19:28, Robert Richter wrote:
> >> From: Robert Richter <rrich...@cavium.com>
> >> +static void gicv3_enable_quirks(void)
> >> +{
> >>
YNC command by avoiding inter node
io and collections/cpu mapping. This fix is only applicable for
Cavium's ThunderX dual-socket platforms.
Signed-off-by: Ganapatrao Kulkarni
[ rric: Reworked errata code, added helper functions, updated commit
message. ]
Signed-off-by: Robert Richter
---
a
message. ]
Signed-off-by: Robert Richter rrich...@cavium.com
---
arch/arm64/Kconfig | 14 +++
drivers/irqchip/irq-gic-common.c | 5 ++--
drivers/irqchip/irq-gic-v3-its.c | 54 ++--
3 files changed, 64 insertions(+), 9 deletions(-)
diff
On 17.08.15 10:00:53, David Daney wrote:
> On 08/14/2015 11:28 AM, Robert Richter wrote:
> >+config CAVIUM_ERRATUM_23154
> >+bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
> >+depends on ARCH_THUNDER
>
> None of the other errata dep
On 17.08.15 17:40:03, Catalin Marinas wrote:
> On Fri, Aug 14, 2015 at 08:28:02PM +0200, Robert Richter wrote:
> > +struct static_key is_cavium_thunderx = STATIC_KEY_INIT_FALSE;
Will add the static ...
> This could also be "static struct ...". BTW, the use of static_key
&g
On 17.08.15 10:00:53, David Daney wrote:
On 08/14/2015 11:28 AM, Robert Richter wrote:
+config CAVIUM_ERRATUM_23154
+bool Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed
+depends on ARCH_THUNDER
None of the other errata depend on a specific ARCH_*. I think we should
On 17.08.15 17:40:03, Catalin Marinas wrote:
On Fri, Aug 14, 2015 at 08:28:02PM +0200, Robert Richter wrote:
+struct static_key is_cavium_thunderx = STATIC_KEY_INIT_FALSE;
Will add the static ...
This could also be static struct BTW, the use of static_key
directly is deprecated, so
From: Robert Richter
The number of pages for the its table may exceed the maximum of 256.
Adding a range check and limitting the number to its maximum.
Based on a patch from Tirumalesh Chalamarla .
Signed-off-by: Tirumalesh Chalamarla
Reviewed-by: Marc Zyngier
Signed-off-by: Robert Richter
From: Robert Richter
This patch implements Cavium ThunderX erratum 23154.
The gicv3 of ThunderX requires a modified version for reading the IAR
status to ensure data synchronization. Since this is in the fast-path
and called with each interrupt, runtime patching is used using jump
label
From: Robert Richter
No need to read the typer register in the loop. Values do not change.
This patch is basically a prerequisite for a follow-on patch that adds
errata code for Cavium ThunderX. It moves the calculation of the
number of id entries to the beginning of the function close to other
From: Robert Richter
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. There are functions that read the IIDR registers
From: Robert Richter
This implements two gicv3-its errata workarounds for ThunderX. Both
with small impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization and basically ignore memory
From: Robert Richter
This patch series adds gicv3 updates and workarounds for HW errata in
Cavium's ThunderX GICV3.
The first one is an unchanged resubmission of a patch from a gicv3
series I sent a while ago.
The next patches implement the workarounds for ThunderX's gicv3. Patch
#2 implements
From: Robert Richter
No need to read the typer register in the loop. Values do not change.
This patch is basically a prerequisite for a follow-on patch that adds
errata code for Cavium ThunderX. It moves the calculation of the
number of id entries to the beginning of the function close to other
From: Robert Richter
The number of pages for the its table may exceed the maximum of 256.
Adding a range check and limitting the number to its maximum.
Based on a patch from Tirumalesh Chalamarla .
Signed-off-by: Tirumalesh Chalamarla
Reviewed-by: Marc Zyngier
Signed-off-by: Robert Richter
From: Robert Richter
This patch series adds gicv3 updates and workarounds for HW errata in
Cavium's ThunderX GICV3.
The first one is an unchanged resubmission of a patch from a gicv3
series I sent a while ago.
The next patches implement the workarounds for ThunderX's gicv3. Patch
#2 adds
From: Robert Richter
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. There are functions that read the IIDR registers
From: Robert Richter
This patch make caps usable optionally. If its value is zero, then all
cpus are matched. E.g. if caps resides in a stuct for marking it
dependend on a certain cpu feature/errata, then an empty value will
indicate not to use caps detection. An empty value will match all cpus
From: Robert Richter
This patch implements Cavium ThunderX erratum 23154.
The gicv3 of ThunderX requires a modified version for reading the IAR
status to ensure data synchronization. Since this is in the fast-path
and called with each interrupt, runtime patching is used using jump
label
From: Robert Richter
This implements two gicv3-its errata workarounds for ThunderX. Both
with small impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization and basically ignore memory
On 14.08.15 09:28:12, Marc Zyngier wrote:
> On 13/08/15 18:11, Robert Richter wrote:
> > On 13.08.15 17:54:41, Marc Zyngier wrote:
> >> On 13/08/15 17:17, Robert Richter wrote:
> >>> Marc,
> >>>
> >>> thanks for your quick review.
> >>
From: Robert Richter rrich...@cavium.com
The number of pages for the its table may exceed the maximum of 256.
Adding a range check and limitting the number to its maximum.
Based on a patch from Tirumalesh Chalamarla tchalama...@cavium.com.
Signed-off-by: Tirumalesh Chalamarla tchalama
From: Robert Richter rrich...@cavium.com
This patch make caps usable optionally. If its value is zero, then all
cpus are matched. E.g. if caps resides in a stuct for marking it
dependend on a certain cpu feature/errata, then an empty value will
indicate not to use caps detection. An empty value
From: Robert Richter rrich...@cavium.com
This patch series adds gicv3 updates and workarounds for HW errata in
Cavium's ThunderX GICV3.
The first one is an unchanged resubmission of a patch from a gicv3
series I sent a while ago.
The next patches implement the workarounds for ThunderX's gicv3
From: Robert Richter rrich...@cavium.com
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. There are functions that read
From: Robert Richter rrich...@cavium.com
No need to read the typer register in the loop. Values do not change.
This patch is basically a prerequisite for a follow-on patch that adds
errata code for Cavium ThunderX. It moves the calculation of the
number of id entries to the beginning
From: Robert Richter rrich...@cavium.com
This patch implements Cavium ThunderX erratum 23154.
The gicv3 of ThunderX requires a modified version for reading the IAR
status to ensure data synchronization. Since this is in the fast-path
and called with each interrupt, runtime patching is used using
From: Robert Richter rrich...@cavium.com
This implements two gicv3-its errata workarounds for ThunderX. Both
with small impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization
From: Robert Richter rrich...@cavium.com
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. There are functions that read
From: Robert Richter rrich...@cavium.com
No need to read the typer register in the loop. Values do not change.
This patch is basically a prerequisite for a follow-on patch that adds
errata code for Cavium ThunderX. It moves the calculation of the
number of id entries to the beginning
From: Robert Richter rrich...@cavium.com
This implements two gicv3-its errata workarounds for ThunderX. Both
with small impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization
From: Robert Richter rrich...@cavium.com
This patch series adds gicv3 updates and workarounds for HW errata in
Cavium's ThunderX GICV3.
The first one is an unchanged resubmission of a patch from a gicv3
series I sent a while ago.
The next patches implement the workarounds for ThunderX's gicv3
From: Robert Richter rrich...@cavium.com
This patch implements Cavium ThunderX erratum 23154.
The gicv3 of ThunderX requires a modified version for reading the IAR
status to ensure data synchronization. Since this is in the fast-path
and called with each interrupt, runtime patching is used using
From: Robert Richter rrich...@cavium.com
The number of pages for the its table may exceed the maximum of 256.
Adding a range check and limitting the number to its maximum.
Based on a patch from Tirumalesh Chalamarla tchalama...@cavium.com.
Signed-off-by: Tirumalesh Chalamarla tchalama
On 14.08.15 09:28:12, Marc Zyngier wrote:
On 13/08/15 18:11, Robert Richter wrote:
On 13.08.15 17:54:41, Marc Zyngier wrote:
On 13/08/15 17:17, Robert Richter wrote:
Marc,
thanks for your quick review.
On 13.08.15 16:11:15, Marc Zyngier wrote:
On 13/08/15 15:47, Robert Richter
On 13.08.15 17:54:41, Marc Zyngier wrote:
> On 13/08/15 17:17, Robert Richter wrote:
> > Marc,
> >
> > thanks for your quick review.
> >
> > On 13.08.15 16:11:15, Marc Zyngier wrote:
> >> On 13/08/15 15:47, Robert Richter wrote:
> >>>
Marc,
thanks for your quick review.
On 13.08.15 16:11:15, Marc Zyngier wrote:
> On 13/08/15 15:47, Robert Richter wrote:
> > From: Robert Richter
> > static const struct gic_capabilities gicv3_errata[] = {
> > {
> > + .desc =
From: Robert Richter
No need to read the typer register in the loop. Values do not change.
This patch is basically a prerequisite for a follow-on patch that adds
errata code for Cavium ThunderX. It moves the calculation of the
number of id entries to the beginning of the function close to other
From: Robert Richter
This patch implements Cavium ThunderX erratum 23154.
The gicv3 of ThunderX requires a modified version for reading the IAR
status to ensure data synchronization. Since this is in the fast-path
and called with each interrupt, runtime patching is used using jump
label
From: Robert Richter
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. There are functions that read the IIDR registers
From: Robert Richter
This implements two gicv3-its errata workarounds for ThunderX. Both
with small impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization and basically ignore memory
From: Robert Richter
This patch series adds gicv3 updates and workarounds for HW errata in
Cavium's ThunderX GICV3.
The first one is an unchanged resubmission of a gicv3 series I sent a
while ago.
The next patches implement the workarounds for ThunderX's gicv3. Patch
#2 adds generic code
From: Robert Richter
The number of pages for the its table may exceed the maximum of 256.
Adding a range check and limitting the number to its maximum.
Based on a patch from Tirumalesh Chalamarla .
Signed-off-by: Tirumalesh Chalamarla
Reviewed-by: Marc Zyngier
Signed-off-by: Robert Richter
From: Robert Richter rrich...@cavium.com
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. There are functions that read
From: Robert Richter rrich...@cavium.com
No need to read the typer register in the loop. Values do not change.
This patch is basically a prerequisite for a follow-on patch that adds
errata code for Cavium ThunderX. It moves the calculation of the
number of id entries to the beginning
From: Robert Richter rrich...@cavium.com
This implements two gicv3-its errata workarounds for ThunderX. Both
with small impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization
From: Robert Richter rrich...@cavium.com
The number of pages for the its table may exceed the maximum of 256.
Adding a range check and limitting the number to its maximum.
Based on a patch from Tirumalesh Chalamarla tchalama...@cavium.com.
Signed-off-by: Tirumalesh Chalamarla tchalama
From: Robert Richter rrich...@cavium.com
This patch series adds gicv3 updates and workarounds for HW errata in
Cavium's ThunderX GICV3.
The first one is an unchanged resubmission of a gicv3 series I sent a
while ago.
The next patches implement the workarounds for ThunderX's gicv3. Patch
#2 adds
From: Robert Richter rrich...@cavium.com
This patch implements Cavium ThunderX erratum 23154.
The gicv3 of ThunderX requires a modified version for reading the IAR
status to ensure data synchronization. Since this is in the fast-path
and called with each interrupt, runtime patching is used using
On 13.08.15 17:54:41, Marc Zyngier wrote:
On 13/08/15 17:17, Robert Richter wrote:
Marc,
thanks for your quick review.
On 13.08.15 16:11:15, Marc Zyngier wrote:
On 13/08/15 15:47, Robert Richter wrote:
From: Robert Richter rrich...@cavium.com
static const struct
Marc,
thanks for your quick review.
On 13.08.15 16:11:15, Marc Zyngier wrote:
On 13/08/15 15:47, Robert Richter wrote:
From: Robert Richter rrich...@cavium.com
static const struct gic_capabilities gicv3_errata[] = {
{
+ .desc = GIC: Cavium erratum 23154
On 11.08.15 13:04:55, David Daney wrote:
> >In the future it might be better structured to try and get the OF
> >node, and if that fails then try and use the ACPI method to obtain
> >these values.
>
> Our current approach, as you can see in the patch, is the opposite. If ACPI
> is being used,
On 11.08.15 13:04:55, David Daney wrote:
In the future it might be better structured to try and get the OF
node, and if that fails then try and use the ACPI method to obtain
these values.
Our current approach, as you can see in the patch, is the opposite. If ACPI
is being used, prefer that
On 07.08.15 12:52:41, Tomasz Nowicki wrote:
> On 07.08.2015 12:43, Robert Richter wrote:
> >On 07.08.15 10:09:04, Tomasz Nowicki wrote:
> >>On 07.08.2015 02:33, David Daney wrote:
> >
> >...
> >
> >>>+#else
> >>>+
> >>>+stat
On 07.08.15 10:09:04, Tomasz Nowicki wrote:
> On 07.08.2015 02:33, David Daney wrote:
...
> >+#else
> >+
> >+static int bgx_init_acpi_phy(struct bgx *bgx)
> >+{
> >+return -ENODEV;
> >+}
> >+
> >+#endif /* CONFIG_ACPI */
> >+
> > #if IS_ENABLED(CONFIG_OF_MDIO)
> >
> > static int
On 07.08.15 10:09:04, Tomasz Nowicki wrote:
On 07.08.2015 02:33, David Daney wrote:
...
+#else
+
+static int bgx_init_acpi_phy(struct bgx *bgx)
+{
+return -ENODEV;
+}
+
+#endif /* CONFIG_ACPI */
+
#if IS_ENABLED(CONFIG_OF_MDIO)
static int bgx_init_of_phy(struct bgx *bgx)
On 07.08.15 12:52:41, Tomasz Nowicki wrote:
On 07.08.2015 12:43, Robert Richter wrote:
On 07.08.15 10:09:04, Tomasz Nowicki wrote:
On 07.08.2015 02:33, David Daney wrote:
...
+#else
+
+static int bgx_init_acpi_phy(struct bgx *bgx)
+{
+ return -ENODEV;
+}
+
+#endif /* CONFIG_ACPI
Marc,
On 06.07.15 11:43:02, Marc Zyngier wrote:
> On 30/06/15 15:14, Robert Richter wrote:
> > static const struct gic_capabilities gicv3_errata[] = {
> > {
> > + .desc = "GIC: Cavium erratum 23154",
> > + .id
Marc,
On 06.07.15 11:43:02, Marc Zyngier wrote:
On 30/06/15 15:14, Robert Richter wrote:
static const struct gic_capabilities gicv3_errata[] = {
{
+ .desc = GIC: Cavium erratum 23154,
+ .id = 0xa100034c, /* ThunderX pass 1.x */
+ .mask
Russell,
thanks for your comments.
On 06.07.15 11:48:12, Russell King - ARM Linux wrote:
> On Tue, Jun 30, 2015 at 04:14:02PM +0200, Robert Richter wrote:
> > +static u64 gic_read_iar_cavium_thunderx(void)
> > {
> > u64 irqstat;
> >
> > + asm volatile
Russell,
thanks for your comments.
On 06.07.15 11:48:12, Russell King - ARM Linux wrote:
On Tue, Jun 30, 2015 at 04:14:02PM +0200, Robert Richter wrote:
+static u64 gic_read_iar_cavium_thunderx(void)
{
u64 irqstat;
+ asm volatile(nop;nop;nop;nop;);
+ asm volatile(nop;nop
From: Robert Richter
No need to read the typer register in the loop. Values do not change.
Signed-off-by: Robert Richter
---
drivers/irqchip/irq-gic-v3-its.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3
From: Robert Richter
This patch series implements workarounds for HW errata in Cavium's
ThunderX GICV3.
The first one is a gicv3 code update I sent a while ago and is a
prerequisit for patch #4. Patch #2 adds generic code to parse the hw
revision provided by an IIDR register value and runs
From: Robert Richter
This patch implements Cavium ThunderX erratum 23154.
The gicv3 of ThunderX requires a modified version for reading the IAR
status to ensure data synchronization. Since this is in the fast-path
and called with each interrupt, runtime patching is used using jump
label
From: Robert Richter
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. There are functions that read the IIDR registers
From: Robert Richter
This implements two gicv3-its errata for ThunderX. Both with small
impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization and basically ignore memory access
type
From: Robert Richter rrich...@cavium.com
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. There are functions that read
From: Robert Richter rrich...@cavium.com
This implements two gicv3-its errata for ThunderX. Both with small
impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization and basically ignore
From: Robert Richter rrich...@cavium.com
This patch series implements workarounds for HW errata in Cavium's
ThunderX GICV3.
The first one is a gicv3 code update I sent a while ago and is a
prerequisit for patch #4. Patch #2 adds generic code to parse the hw
revision provided by an IIDR register
From: Robert Richter rrich...@cavium.com
This patch implements Cavium ThunderX erratum 23154.
The gicv3 of ThunderX requires a modified version for reading the IAR
status to ensure data synchronization. Since this is in the fast-path
and called with each interrupt, runtime patching is used using
From: Robert Richter rrich...@cavium.com
No need to read the typer register in the loop. Values do not change.
Signed-off-by: Robert Richter rrich...@cavium.com
---
drivers/irqchip/irq-gic-v3-its.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic
Tejun, Gerry,
On 17.06.15 17:02:20, Jiang Liu wrote:
> On 2015/6/17 16:48, Robert Richter wrote:
> > static struct msi_desc *msix_get_desc(struct pci_dev *dev, u16 entry)
> > {
> > +#ifdef CONFIG_PCI_MSI
> > struct msi_desc *desc;
> >
> > li
>From fd984f3be22f27b8d3c4cf577dbbf0a39792ea89 Mon Sep 17 00:00:00 2001
From: Robert Richter
Date: Wed, 17 Jun 2015 10:33:22 +0200
Subject: [PATCH] ahci, msix: Fix build error for !PCI_MSI
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Fixing a bu
From fd984f3be22f27b8d3c4cf577dbbf0a39792ea89 Mon Sep 17 00:00:00 2001
From: Robert Richter rrich...@cavium.com
Date: Wed, 17 Jun 2015 10:33:22 +0200
Subject: [PATCH] ahci, msix: Fix build error for !PCI_MSI
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Tejun, Gerry,
On 17.06.15 17:02:20, Jiang Liu wrote:
On 2015/6/17 16:48, Robert Richter wrote:
static struct msi_desc *msix_get_desc(struct pci_dev *dev, u16 entry)
{
+#ifdef CONFIG_PCI_MSI
struct msi_desc *desc;
list_for_each_entry(desc, dev-msi_list, list
On 05.06.15 19:49:24, Robert Richter wrote:
> From: Robert Richter
>
> This patch set adds generic support for MSI-X interrupts to the SATA
> PCI driver.
>
> One patch does the generic change, the other add support for Cavium's
> ThunderX host controller.
Tejun,
any com
On 03.06.15 12:32:04, Jiri Olsa wrote:
> On Tue, Jun 02, 2015 at 10:12:04AM -0700, Sukadev Bhattiprolu wrote:
> > From: Andi Kleen
> >
> > The Intel events use a dot to separate event name and unit mask.
> > Allow dot in names in the scanner, and remove special handling
> > of dot as EOF. Also
On 05.06.15 19:49:24, Robert Richter wrote:
From: Robert Richter rrich...@cavium.com
This patch set adds generic support for MSI-X interrupts to the SATA
PCI driver.
One patch does the generic change, the other add support for Cavium's
ThunderX host controller.
Tejun,
any comment
On 03.06.15 12:32:04, Jiri Olsa wrote:
On Tue, Jun 02, 2015 at 10:12:04AM -0700, Sukadev Bhattiprolu wrote:
From: Andi Kleen a...@linux.intel.com
The Intel events use a dot to separate event name and unit mask.
Allow dot in names in the scanner, and remove special handling
of dot as
From: Robert Richter
This patch adds generic MSI-X support for single interrupts to the
SATA PCI driver. MSI-X support is needed for host controller that only
have MSI-X support implemented, but no MSI or intx. This patch only
adds support for single interrupts, multiple per-port MSI-X
From: Robert Richter
This patch adds support for Cavium's ThunderX host controller. The
controller resides on the SoC and is a AHCI compatible SATA controller
with one port, compliant with Serial ATA 3.1 and AHCI Revision 1.31.
There can exists multiple SATA controllers on the SoC
From: Robert Richter
This patch set adds generic support for MSI-X interrupts to the SATA
PCI driver.
One patch does the generic change, the other add support for Cavium's
ThunderX host controller.
Robert Richter (2):
ahci: Add generic MSI-X support for single interrupts to SATA PCI
From: Robert Richter rrich...@cavium.com
This patch adds generic MSI-X support for single interrupts to the
SATA PCI driver. MSI-X support is needed for host controller that only
have MSI-X support implemented, but no MSI or intx. This patch only
adds support for single interrupts, multiple per
From: Robert Richter rrich...@cavium.com
This patch set adds generic support for MSI-X interrupts to the SATA
PCI driver.
One patch does the generic change, the other add support for Cavium's
ThunderX host controller.
Robert Richter (2):
ahci: Add generic MSI-X support for single interrupts
From: Robert Richter rrich...@cavium.com
This patch adds support for Cavium's ThunderX host controller. The
controller resides on the SoC and is a AHCI compatible SATA controller
with one port, compliant with Serial ATA 3.1 and AHCI Revision 1.31.
There can exists multiple SATA controllers
Tejun,
thanks for applying first 2 patches of this series already.
I will address the comments you made on this patch in my next
submission. But see my question below.
On 03.06.15 14:44:22, Tejun Heo wrote:
> > + /*
> > +* Per-port msix interrupts are not supported. Assume single
> > +
Tejun,
thanks for applying first 2 patches of this series already.
I will address the comments you made on this patch in my next
submission. But see my question below.
On 03.06.15 14:44:22, Tejun Heo wrote:
+ /*
+* Per-port msix interrupts are not supported. Assume single
+*
From: Robert Richter
Currently, ahci supports only msi and intx. To also support msix the
handling of the irq number need to be changed. The irq number for msix
devices is taken from msi_list instead of pci_dev. Thus, the irq
number of a device needs to be stored in struct ahci_host_priv now
From: Robert Richter
This patch adds generic support for MSI-X interrupts to the SATA PCI
driver. MSI-X support is needed for host controller that only have
MSI-X support implemented, such as the controller on Cavium's ThunderX
SoC. Only support for single interrupts is added, multiple per-port
From: Robert Richter
This patch refactors ahci_init_interrupts() and moves msi code to a
separate function. Need the split since we add msix initialization in
a later patch. The initialization for msix will be done after msi but
before intx.
Signed-off-by: Robert Richter
---
drivers/ata
From: Robert Richter
This patch set adds generic support for MSI-X interrupts to the SATA
PCI driver.
The first 2 patches rework the code, one splits msi and intx code into
separate functions, the other changes interrupt initialization to
store the irq number in the ahci data structure (struct
From: Robert Richter rrich...@cavium.com
This patch set adds generic support for MSI-X interrupts to the SATA
PCI driver.
The first 2 patches rework the code, one splits msi and intx code into
separate functions, the other changes interrupt initialization to
store the irq number in the ahci data
From: Robert Richter rrich...@cavium.com
Currently, ahci supports only msi and intx. To also support msix the
handling of the irq number need to be changed. The irq number for msix
devices is taken from msi_list instead of pci_dev. Thus, the irq
number of a device needs to be stored in struct
From: Robert Richter rrich...@cavium.com
This patch refactors ahci_init_interrupts() and moves msi code to a
separate function. Need the split since we add msix initialization in
a later patch. The initialization for msix will be done after msi but
before intx.
Signed-off-by: Robert Richter
From: Robert Richter rrich...@cavium.com
This patch adds generic support for MSI-X interrupts to the SATA PCI
driver. MSI-X support is needed for host controller that only have
MSI-X support implemented, such as the controller on Cavium's ThunderX
SoC. Only support for single interrupts is added
On 27.05.15 10:01:32, Robert Richter wrote:
> From: Robert Richter
>
> The irq number for msix devices is taken from msi_list instead of
> pci_dev. Thus, the irq number of a device needs to be stored in struct
> ahci_host_priv now. Host controller can be activated then in
From: Robert Richter
This patch refactors ahci_init_interrupts() and moves code to separate
functions for msi and intx. Needed since we add msix initialization in
a later patch. The initialization for msix is done after msi but
before intx.
Signed-off-by: Robert Richter
---
drivers/ata/ahci.c
From: Robert Richter
The irq number for msix devices is taken from msi_list instead of
pci_dev. Thus, the irq number of a device needs to be stored in struct
ahci_host_priv now. Host controller can be activated then in a
generic way.
Signed-off-by: Robert Richter
---
drivers/ata/acard-ahci.c
From: Robert Richter
This patch adds generic support for MSI-X interrupts to the SATA PCI
driver. MSI-X support is needed for host controller that only have
MSI-X support implemented, such as the controller on Cavium's ThunderX
SoC. Only support for single interrupts is added, multiple per-port
From: Robert Richter
This patch set adds generic support for MSI-X interrupts to the SATA
PCI driver.
The first 2 patches rework the code, one splits msi and intx code into
separate functions, the other changes interrupt initialization to
store the irq number in the ahci data structure (struct
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