On Mon, Sep 21, 2020 at 08:47:23AM +0200, Christoph Hellwig wrote:
> On Mon, Sep 21, 2020 at 09:44:18AM +0300, Tony Lindgren wrote:
> > * Janusz Krzysztofik [200919 22:29]:
> > > Hi Tony,
> > >
> > > On Friday, September 18, 2020 7:49:33 A.M. CEST Tony Lindgren wrote:
> > > > * Christoph Hellwig
On Fri, Sep 18, 2020 at 02:46:15PM +0200, Arnd Bergmann wrote:
> Hi Christoph, Russell,
>
> Here is an updated series for removing set_fs() from arch/arm,
> based on the previous feedback.
>
> I have tested the oabi-compat changes using the LTP tests for the three
> modified syscalls using an Arm
On Thu, Sep 17, 2020 at 07:29:37PM +0200, Arnd Bergmann wrote:
> On Tue, Sep 8, 2020 at 8:15 AM Christoph Hellwig wrote:
> >
> > > +static void dump_mem(const char *, const char *, unsigned long, unsigned
> > > long, bool kernel_mode);
> >
> > This adds a pointlessly long line.
>
> Fixed.
>
> >
On Thu, Sep 17, 2020 at 07:32:27PM +0200, Christoph Hellwig wrote:
> static int __init cats_pci_init(void)
> {
> - if (machine_is_cats())
> - pci_common_init(&cats_pci);
> + if (!machine_is_cats())
> + return 0;
> + bus_register_notifier(&pci_bus_type, &footbri
On Thu, Sep 17, 2020 at 07:32:28PM +0200, Christoph Hellwig wrote:
> The DMA API removed support for not passing in a device a long time
> ago, so remove the NULL checks.
What happens with ISA devices?
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps dow
On Wed, Sep 16, 2020 at 09:57:15AM +0800, Leizhen (ThunderTown) wrote:
> On 2020/9/16 3:01, Russell King - ARM Linux admin wrote:
> > On Tue, Sep 15, 2020 at 09:16:15PM +0800, Zhen Lei wrote:
> >> Currently, only support the kernels where the base of physical memory is
> &
On Tue, Sep 15, 2020 at 09:16:13PM +0800, Zhen Lei wrote:
> v1 --> v2:
> Nothing changed, but add mail list: patc...@armlinux.org.uk
It isn't a mailing list, it's a bot, and it should only be copied
when you're ready to submit the patches, and only after they've been
reviewed. It queues the patch
On Tue, Sep 15, 2020 at 09:16:15PM +0800, Zhen Lei wrote:
> Currently, only support the kernels where the base of physical memory is
> at a 16MiB boundary. Because the add/sub instructions only contains 8bits
> unrotated value. But we can use one more "add/sub" instructions to handle
> bits 23-16.
On Fri, Sep 11, 2020 at 09:01:01AM -0700, Nathan Chancellor wrote:
> On Fri, Sep 11, 2020 at 08:22:36AM -0700, Jakub Kicinski wrote:
> > On Fri, 11 Sep 2020 12:11:58 +0100 Russell King - ARM Linux admin wrote:
> > > On Thu, Sep 10, 2020 at 05:31:42PM -0700, Nathan Chancellor
On Thu, Sep 10, 2020 at 07:40:37AM +0200, Christoph Hellwig wrote:
> The DMA offset notifier can only be used if PHYS_OFFSET is at least
> KEYSTONE_HIGH_PHYS_START, which can't be represented by a 32-bit
> phys_addr_t. Currently the code compiles fine despite that, a pending
> change to the DMA of
On Thu, Sep 10, 2020 at 05:31:42PM -0700, Nathan Chancellor wrote:
> On Thu, Sep 10, 2020 at 03:28:11PM -0700, David Miller wrote:
> > From: Nathan Chancellor
> > Date: Thu, 10 Sep 2020 10:48:27 -0700
> >
> > > Clang warns (trimmed for brevity):
> > >
> > > drivers/net/ethernet/marvell/mvpp2/mvp
On Thu, Sep 10, 2020 at 10:31:12PM +0200, Marek Behun wrote:
> On Thu, 10 Sep 2020 19:34:35 +0100
> Russell King - ARM Linux admin wrote:
>
> > On Thu, Sep 10, 2020 at 08:31:54PM +0200, Andrew Lunn wrote:
> > > Generally the driver will default to the hardware reset bl
On Thu, Sep 10, 2020 at 08:31:54PM +0200, Andrew Lunn wrote:
> Generally the driver will default to the hardware reset blink
> pattern. There are a few PHY drivers which change this at probe, but
> not many. The silicon defaults are pretty good.
The "right" blink pattern can be a matter of how the
gt; Reviewed-by: Andrew Lunn
> Reviewed-by: Florian Fainelli
Reviewed-by: Russell King
Thanks.
> ---
> v1->v2
> - fix the commit subject spilled into the commit message
> ---
> drivers/net/dsa/mt7530.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
&g
On Sun, Aug 23, 2020 at 09:10:25PM +0200, Christian Gmeiner wrote:
> Hi
>
> > I have formally tested the patch with 5.7.10 - and it doesn't resolve
> > the issue - sadly :(
> >
> > From my testing, the reads on
> > VIVS_HI_CHIP_PRODUCT_ID
> > VIVS_HI_CHIP_ECO_ID
> > need to be conditional - while
On Sun, Aug 16, 2020 at 09:14:51PM -0700, David Miller wrote:
> From: Randy Dunlap
> Date: Sun, 16 Aug 2020 15:25:49 -0700
>
> > Fix a kernel-doc warning for the pcs_config() function prototype:
> >
> > ../include/linux/phylink.h:406: warning: Excess function parameter
> > 'permit_pause_to_mac'
On Thu, Aug 06, 2020 at 03:26:09PM -0700, Doug Anderson wrote:
> Hi,
>
> Sigh. OK, hopefully correct now:
>
> https://www.armlinux.org.uk/developer/patches/viewpatch.php?id=8997/2
LGTM. Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10
On Thu, Aug 06, 2020 at 05:46:50PM -0400, Peter Geis wrote:
> Good Evening,
>
> I had attempted to get this working as well, but have run into
> difficulties with both my implementation and yours as well.
> My implementation was almost the same as yours, with the exception of
> also changing:
> @@
On Thu, Aug 06, 2020 at 11:28:09AM -0700, Doug Anderson wrote:
> Let's hope this one works:
>
> https://www.armlinux.org.uk/developer/patches/viewpatch.php?id=8997/1
Almost. It seems that you must have grabbed a copy off the patch
system, edited it and sent it back?
The commit message appears t
On Thu, Aug 06, 2020 at 04:41:44PM +0100, Russell King - ARM Linux admin wrote:
> On Thu, Aug 06, 2020 at 08:05:10AM -0700, Doug Anderson wrote:
> > Yet if I go check mainline the patch is not there. This came to my
> > attention since we had my patch picked to the Chrome O
to the arm64 code.
> >
> >
> > > I think it looks fine, so please put it into the patch system
> > > with my Ack:
> > >
> > > Acked-by: Will Deacon
> >
> > Thanks! Submitted as:
> >
> > https://www.arm.linux.org.uk/dev
Add the TEXT_OFFSET to the decompressor's kexec image structure to
kexec knows what offset to use.
Signed-off-by: Russell King
---
arch/arm/Makefile | 3 +++
arch/arm/boot/compressed/Makefile | 1 +
arch/arm/boot/compressed/vmlinux.lds.S | 3 ++-
3 files chang
Add the required malloc size to the decompressor kexec size structure.
Signed-off-by: Russell King
---
arch/arm/boot/compressed/Makefile | 5 -
arch/arm/boot/compressed/head.S| 4 ++--
arch/arm/boot/compressed/vmlinux.lds.S | 3 ++-
3 files changed, 8 insertions(+), 4 deletions
On Thu, Aug 06, 2020 at 10:45:42AM +0200, Norbert Lange wrote:
> Am Do., 6. Aug. 2020 um 02:30 Uhr schrieb Russell King - ARM Linux
> admin :
> >
> > On Thu, Aug 06, 2020 at 01:05:55AM +0200, Norbert Lange wrote:
> > > diff --git a/arch/arm/boot/compressed/head.S
>
On Thu, Aug 06, 2020 at 01:05:55AM +0200, Norbert Lange wrote:
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 434a16982e34..1af01bfe6638 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -614,7 +614,11 @@ not_reloca
On Wed, Aug 05, 2020 at 03:09:34PM -0700, Joe Perches wrote:
> On Wed, 2020-08-05 at 23:02 +0100, Russell King - ARM Linux admin wrote:
> > On Wed, Aug 05, 2020 at 11:54:25AM -0700, Joe Perches wrote:
> > > On Wed, 2020-08-05 at 19:22 +0100, Russell King - ARM Linux admin wro
On Wed, Aug 05, 2020 at 11:47:38AM -0700, Joe Perches wrote:
> On Wed, 2020-08-05 at 19:22 +0100, Russell King - ARM Linux admin wrote:
> > On Wed, Aug 05, 2020 at 11:11:28AM -0700, Linus Torvalds wrote:
> > > On Wed, Aug 5, 2020 at 7:34 AM Russell King
> > > wrote
On Wed, Aug 05, 2020 at 11:54:25AM -0700, Joe Perches wrote:
> On Wed, 2020-08-05 at 19:22 +0100, Russell King - ARM Linux admin wrote:
> > On Wed, Aug 05, 2020 at 11:11:28AM -0700, Linus Torvalds wrote:
> > > On Wed, Aug 5, 2020 at 7:34 AM Russell King
> > > wrote
ake use of phylink to be detected.
Signed-off-by: Russell King
---
Linus,
Is this something you're willing to merge directly please?
Thanks.
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4e2698cc7e23..3b11a8b84129 100644
--- a/MA
On Wed, Aug 05, 2020 at 11:11:28AM -0700, Linus Torvalds wrote:
> On Wed, Aug 5, 2020 at 7:34 AM Russell King
> wrote:
> >
> > Is this something you're willing to merge directly please?
>
> Done.
>
> That said:
>
> > -K: phylink
> >
On Mon, Aug 03, 2020 at 10:21:04AM -0700, Eric Biggers wrote:
> On Mon, Aug 03, 2020 at 06:12:33PM +0100, Russell King - ARM Linux admin
> wrote:
> > Dear syzbot,
> >
> > Please explain why you are spamming me with all these reports - four so
> > far. I don'
Dear syzbot,
Please explain why you are spamming me with all these reports - four so
far. I don't understand why you think I should be doing anything with
these.
Thanks.
On Mon, Aug 03, 2020 at 08:05:21AM -0700, syzbot wrote:
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:
On Mon, Aug 03, 2020 at 03:34:39PM +0200, Krzysztof Kozlowski wrote:
> On Wed, Jul 29, 2020 at 02:47:31PM +0100, Guillaume Tucker wrote:
> > The L220_AUX_CTRL_NS_LOCKDOWN flag is set during the L2C enable
> > sequence. There is no need to set it in the default register value,
> > this was done bef
On Thu, Jul 30, 2020 at 09:00:36AM +, codrin.ciubota...@microchip.com wrote:
> On 27.07.2020 13:50, Russell King - ARM Linux admin wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > On Mon, Jul 2
On Wed, Jul 29, 2020 at 02:47:32PM +0100, Guillaume Tucker wrote:
> The L310_PREFETCH_CTRL register bits 28 and 29 to enable data and
> instruction prefetch respectively can also be accessed via the
> L2X0_AUX_CTRL register. They appear to be actually wired together in
> hardware between the regis
On Wed, Jul 29, 2020 at 05:49:09PM +0800, Jisheng Zhang wrote:
> mvneta has switched to phylink, so the comment should look
> like "We may have called phylink_speed_down before".
>
> Signed-off-by: Jisheng Zhang
Reviewed-by: Russell King
> ---
> Since v1:
>
On Tue, Jul 28, 2020 at 02:27:43PM +0200, Frank Wunderlich wrote:
> From: Landen Chao
>
> in recent Kernel-Versions there are warnings about incorrect MTU-Size
> like these:
Can the above also be fixed for incorrect capitalisation and improper
hyphernation please?
Thanks.
>
> eth0: mtu greate
On Mon, Jul 27, 2020 at 06:16:32PM +0200, Alexandre Belloni wrote:
> On 27/07/2020 17:55:50+0200, Jon Nettleton wrote:
> > > So, can we please have that discussion, it is pertinent to this patch.
> > >
> >
> > Thinking about this some more, I believe whether or not an IOCTL
> > interface is in the
On Mon, Jul 27, 2020 at 05:41:04PM +0200, Alexandre Belloni wrote:
> On 27/07/2020 16:24:39+0100, Russell King - ARM Linux admin wrote:
> > On Mon, Jul 27, 2020 at 04:49:38PM +0200, Alexandre Belloni wrote:
> > > On 27/07/2020 10:45:53+0100, Russell King - ARM Linux admin wrote:
On Mon, Jul 27, 2020 at 04:49:38PM +0200, Alexandre Belloni wrote:
> On 27/07/2020 10:45:53+0100, Russell King - ARM Linux admin wrote:
> > > This is but this shouldn't be a DT property as it has to be changed
> > > dynamically. I'm working on an ioctl interface to
On Mon, Jul 27, 2020 at 03:33:17PM +0200, Jon Nettleton wrote:
> On Mon, Jul 27, 2020 at 11:46 AM Russell King - ARM Linux admin
> wrote:
> >
> > On Thu, Jul 23, 2020 at 09:57:55PM +0200, Alexandre Belloni wrote:
> > > On 23/07/2020 11:49:05-0600, Rob Herring wrote:
&
On Mon, Jul 27, 2020 at 10:44:57AM +, codrin.ciubota...@microchip.com wrote:
> On 24.07.2020 23:52, Russell King - ARM Linux admin wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > On Fri, Jul 2
On Thu, Jul 23, 2020 at 09:57:55PM +0200, Alexandre Belloni wrote:
> On 23/07/2020 11:49:05-0600, Rob Herring wrote:
> > On Mon, Jul 20, 2020 at 12:23:59PM +0100, miguelborgesdefrei...@gmail.com
> > wrote:
> > > From: Miguel Borges de Freitas
> > >
> > > This adds direct-switching mode as a conf
A is not fully
> > converted to the best of my knowledge, so maybe it is no problem for PXA
> > to switch to "gpio", too? We should ask Russell King (cced).
Fully converted to what? The generic handling where the i2c core layer
handles everything to do with recovery, includ
On Tue, Jul 21, 2020 at 06:16:24PM +0100, Jonathan McDowell wrote:
> This adds full 802.1q VLAN support to the qca8k, allowing the use of
> vlan_filtering and more complicated bridging setups than allowed by
> basic port VLAN support.
>
> Tested with a number of untagged ports with separate VLANs
On Tue, Jul 21, 2020 at 05:43:15PM +0200, Arnd Bergmann wrote:
> On Tue, Jul 21, 2020 at 5:07 PM Naresh Kamboju
> wrote:
> >
> > This might add little value.
> >
> > arm build sets failed on linux next 20200721.
> > The defconfig ( +config fragments ) builds PASS.
> > The tinyconfig and allnoconfi
On Mon, Jul 20, 2020 at 03:55:26PM +0800, Icenowy Zheng wrote:
> 在 2020-07-08星期三的 12:03 +0100，Russell King - ARM Linux admin写道：
> > On Wed, Jul 08, 2020 at 12:55:27PM +0200, Ondrej Jirman wrote:
> > > I noticed several mobile Linux distributions failing to enable the
> &
On Sat, Jul 18, 2020 at 04:44:35PM +0200, Andrew Lunn wrote:
> On Sat, Jul 18, 2020 at 02:20:11PM +0100, Russell King - ARM Linux admin
> wrote:
> > On Fri, Jul 17, 2020 at 10:44:19PM +0200, John Crispin wrote:
> > > in regards to the sgmii clk skew. I never understood
On Fri, Jul 17, 2020 at 10:44:19PM +0200, John Crispin wrote:
> in regards to the sgmii clk skew. I never understood the electrics fully I
> am afraid, but without the patch it simply does not work. my eletcric foo is
> unfortunately is not sufficient to understand the "whys" I am afraid.
Do you h
On Thu, Jul 09, 2020 at 11:35:23PM +0200, Michael Walle wrote:
> The constants are taken from the USXGMII Singleport Copper Interface
> specification. The naming are based on the SGMII ones, but with an MDIO_
> prefix.
>
> Signed-off-by: Michael Walle
> ---
> include/uapi/linux/mdio.h | 26 +
hey're a little harder to check, it would
have been easier for them to be 2 << 9 etc), tick.
The speed+duplex bits correspond (same issue with the raw speed bits,
defining them as MDIO_LPA_USXGMII_1000 | MDIO_LPA_USXGMII_FULL_DUPLEX
would've made them more obvious, but at the
I doubt anyone is going to fix this; it's an XIP kernel, and it looks
like the .data and .rodata sections are correctly placed as per the
configuration, but for some reason the .text (and sections that follow)
are incorrectly placed in VMA space. The configuration file says that
the kernel should
On Thu, Jul 09, 2020 at 03:41:15PM +0200, Andrew Lunn wrote:
> On Thu, Jul 09, 2020 at 07:57:42AM +0200, Frank Wunderlich wrote:
> > From: René van Dorst
> >
> > in recent Kernel-Versions there are warnings about incorrect MTU-Size
> > like these:
> >
> > mt7530 mdio-bus:00: nonfatal error -95 s
On Wed, Jul 08, 2020 at 12:55:27PM +0200, Ondrej Jirman wrote:
> I noticed several mobile Linux distributions failing to enable the
> thermal regulation correctly, because the kernel is silent
> when thermal driver fails to probe. Add enough error reporting
> to debug issues and warn users in case
On Tue, Jul 07, 2020 at 12:02:53AM +0200, Michael Walle wrote:
> The ENETC has the same PCS PHY and thus needs the same definitions. Move
> them into the common enetc_mdio.h header which has already the macros
> for the SGMII PCS.
>
> Signed-off-by: Michael Walle
> ---
> drivers/net/dsa/ocelot/f
On Mon, Jul 06, 2020 at 12:38:37PM -0700, Chris Healy wrote:
> Dynamically generate a unique GPIO interrupt name, based on the
> device name and the GPIO name. For example:
>
> 103: 0 sx1503q 12 Edge sff2-los
> 104: 0 sx1503q 13 Edge sff3-los
>
> The sffX indica
On Thu, Jul 02, 2020 at 12:41:39PM +0300, Vladimir Oltean wrote:
> On Thu, 2 Jul 2020 at 11:41, Russell King - ARM Linux admin
> wrote:
> >
> > On Thu, Jul 02, 2020 at 01:04:02AM +0300, Vladimir Oltean wrote:
> > > On Thu, 2 Jul 2020 at 00:53, Russell King - A
; Signed-off-by: Codrin Ciubotariu
For the code _transformation_ that the patch does:
Reviewed-by: Russell King
as it is equivalent. However, for a deeper review of what is going
on here, I've a question:
$ grep live_ports *
ksz8795.c: dev->live_ports = dev->host_mask;
ksz8
On Thu, Jul 02, 2020 at 01:04:02AM +0300, Vladimir Oltean wrote:
> On Thu, 2 Jul 2020 at 00:53, Russell King - ARM Linux admin
> wrote:
> >
> > fixing up almost every driver the best I can with the exception of two -
> > felix DSA and Mediatek.
> >
> > I'
On Wed, Jul 01, 2020 at 11:34:30PM +0200, Michael Walle wrote:
> This is a resend of the series because the conversion to the phylink
> interface will likely take longer:
> https://lore.kernel.org/netdev/CA+h21hpBodyY8CtNH2ktRdc2FqPi=Fjp94=vvzvzsvbnvnf...@mail.gmail.com/
I don't think it will; I'v
On Mon, Jun 29, 2020 at 11:54:01AM -0400, Arvind Sankar wrote:
> On Sun, Jun 28, 2020 at 11:18:37PM -0700, Kees Cook wrote:
> > We don't want to depend on the linker's orphan section placement
> > heuristics as these can vary between linkers, and may change between
> > versions. All sections need t
On Mon, Jun 29, 2020 at 02:15:14PM -0400, Arvind Sankar wrote:
> On Mon, Jun 29, 2020 at 07:07:04PM +0100, Russell King - ARM Linux admin
> wrote:
> > On Mon, Jun 29, 2020 at 11:54:01AM -0400, Arvind Sankar wrote:
> > > On Sun, Jun 28, 2020 at 11:18:37PM -0700, Kees Cook wr
On Fri, Jun 26, 2020 at 12:02:05PM -0700, Florian Fainelli wrote:
> On 6/22/20 8:08 AM, Madalin Bucur (OSS) wrote:
> > Hi Andrew, the reasons behind this selection:
> >
> > - the PCS that is controlled by the backplane driver belongs to the PHY
> > layer so the representation as a PHY device is le
On Thu, Jun 25, 2020 at 10:47:30PM +0200, Christophe JAILLET wrote:
> The dev_id used in 'request_irq()' and 'free_irq()' should match.
> Use 'info' in both cases.
>
> Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
> Signed-off-by: Christop
On Wed, Jun 24, 2020 at 05:57:19PM +0100, Russell King - ARM Linux admin wrote:
> On Tue, Jun 23, 2020 at 06:27:06PM +0200, Bartosz Golaszewski wrote:
> > wt., 23 cze 2020 o 11:56 Russell King - ARM Linux admin
> > napisał(a):
> > >
> > > On Tue, Jun 23,
On Tue, Jun 23, 2020 at 06:27:06PM +0200, Bartosz Golaszewski wrote:
> wt., 23 cze 2020 o 11:56 Russell King - ARM Linux admin
> napisał(a):
> >
> > On Tue, Jun 23, 2020 at 11:46:15AM +0200, Bartosz Golaszewski wrote:
> > > wt., 23 cze 2020 o 11:43 Russell King - ARM L
On Wed, Jun 24, 2020 at 09:06:28AM -0700, Florian Fainelli wrote:
> On 6/24/2020 6:48 AM, Bartosz Golaszewski wrote:
> > I didn't expect to open such a can of worms...
> >
> > This has evolved into several new concepts being proposed vs my
> > use-case which is relatively simple. The former will p
onfiguration register. As mentioned by Russell King
> its purpose was also to check for valid interface modes early so that
> later in the driver we do not have to care for unexpected interface
> modes.
> Add back the test to let the driver bail out early on unhandled
> interface modes.
("net: ethernet: mvneta: Fix Serdes configuration for SoCs
without comphy")
Reviewed-by: Russell King
Thanks.
> ---
> drivers/net/ethernet/marvell/mvneta.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvneta.c
&g
On Tue, Jun 23, 2020 at 08:36:46PM -0700, Florian Fainelli wrote:
> Le 2020-06-23 à 20:26, Jisheng Zhang a écrit :
> > Call phy_disable_interrupts() in phy_init_hw() to "have a defined init
> > state as we don't know in which state the PHY is if the PHY driver is
> > loaded. We shouldn't assume tha
On Tue, Jun 23, 2020 at 11:46:15AM +0200, Bartosz Golaszewski wrote:
> wt., 23 cze 2020 o 11:43 Russell King - ARM Linux admin
> napisał(a):
> >
> > On Tue, Jun 23, 2020 at 11:41:11AM +0200, Bartosz Golaszewski wrote:
> > > pon., 22 cze 2020 o 15:29 Russell King - ARM L
On Tue, Jun 23, 2020 at 11:41:11AM +0200, Bartosz Golaszewski wrote:
> pon., 22 cze 2020 o 15:29 Russell King - ARM Linux admin
> napisał(a):
> >
>
> [snip!]
>
> >
> > This is likely to cause issues for some PHY drivers. Note that we have
> > some P
()")
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Russell King
Thanks.
> ---
> include/linux/phylink.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/linux/phylink.h b/include/linux/phylink.h
> index cc5b452a184e..02ff1419d4be 100644
>
itialization, so that depending on the SoC either comphy or
> MVNETA_SERDES_CFG is configured.
> With this we no longer write to the MVNETA_SERDES_CFG on SoCs where it
> doesn't exist.
>
> Suggested-by: Russell King
> Signed-off-by: Sascha Hauer
> ---
> d
On Mon, Jun 22, 2020 at 11:37:43AM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> The MDIO sub-system now supports PHY regulators. Let's reuse the code
> to extend this support over to the PHY device.
>
> Signed-off-by: Bartosz Golaszewski
> ---
> drivers/net/phy/phy_device.
On Mon, Jun 22, 2020 at 11:37:42AM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> Currently many MAC drivers control the regulator supplying the PHY but
> this is conceptually wrong. The regulator should be defined as a property
> of the PHY node on the MDIO bus and controlled
On Fri, Jun 19, 2020 at 11:02:50PM +0300, Serge Semin wrote:
> Really instead of twice checking the clk_round_rate() return value
> we could do it once, and if it isn't error the clock rate can be changed.
> By doing so we decrease a number of ret-value tests and remove a weird
> goto-based constru
On Fri, Jun 19, 2020 at 03:26:59PM +0200, Andrew Lunn wrote:
> On Thu, Jun 18, 2020 at 09:47:59PM -0700, Florian Fainelli wrote:
> > Commit 02a6efcab675 ("net: phy: allow scanning busses with missing
> > phys") added a special condition to return -ENODEV in case -ENODEV or
> > -EIO was returned fro
On Wed, Jun 17, 2020 at 06:23:48AM +0200, Sedat Dilek wrote:
> On Wed, Jun 17, 2020 at 12:36 AM 'Nathan Huckleberry' via Clang Built
> Linux wrote:
> >
> > Since clang does not push pc and sp in function prologues, the current
> > implementation of unwind_frame does not work. By using the previous
On Thu, Jun 18, 2020 at 06:01:29PM +0200, Heiko Stübner wrote:
> Am Donnerstag, 18. Juni 2020, 17:47:48 CEST schrieb Russell King - ARM Linux
> admin:
> > On Thu, Jun 18, 2020 at 05:41:54PM +0200, Heiko Stübner wrote:
> > > Though I'm not sure how this fits in the whol
On Thu, Jun 18, 2020 at 05:41:54PM +0200, Heiko Stübner wrote:
> Am Donnerstag, 18. Juni 2020, 15:41:02 CEST schrieb Russell King - ARM Linux
> admin:
> > On Thu, Jun 18, 2020 at 03:28:22PM +0200, Andrew Lunn wrote:
> > > On Thu, Jun 18, 2020 at 02:11:39PM +0200,
On Thu, Jun 18, 2020 at 03:28:22PM +0200, Andrew Lunn wrote:
> On Thu, Jun 18, 2020 at 02:11:39PM +0200, Heiko Stuebner wrote:
> > From: Heiko Stuebner
> >
> > At least VSC8530/8531/8540/8541 contain a clock output that can emit
> > a predefined rate of 25, 50 or 125MHz.
> >
> > This may then fe
On Wed, Jun 17, 2020 at 08:43:34PM +0200, Andrew Lunn wrote:
> You have explained what the change does. But not why it is
> needed. What exactly is happening. To me, the key thing is
> understanding why we get -110, and why it is not an actual error we
> should be reporting as an error. That is wha
On Tue, Jun 16, 2020 at 11:10:27AM +0200, Heiko Stübner wrote:
> >
> > You also need to provide a proper header posting when you repost this series
> > after fixing this bug.
>
> not sure I understand what you mean with "header posting" here.
David is requesting that you send a "0/N" email summa
On Sat, Jun 13, 2020 at 05:34:32PM +0530, afzal mohammed wrote:
> Hi,
>
> On Fri, Jun 12, 2020 at 10:07:28PM +0200, Arnd Bergmann wrote:
>
> > I think a lot
> > of usercopy calls are only for a few bytes, though this is of course
> > highly workload dependent and you might only care about the lar
On Fri, Jun 12, 2020 at 01:52:50PM +0200, Sascha Hauer wrote:
> On Fri, Jun 12, 2020 at 12:30:31PM +0100, Russell King - ARM Linux admin
> wrote:
> > On Fri, Jun 12, 2020 at 12:22:13PM +0100, Russell King - ARM Linux admin
> > wrote:
> > > On Fri, Jun 12, 2020 at 11:
On Fri, Jun 12, 2020 at 02:06:04PM +0200, Sascha Hauer wrote:
> And here is the same patch which applies on master and the net tree.
> It works as expected on my Armada XP in 2.5Gbps mode. Provided you are
> happy with the patch I can send it as a formal patch on monday if by
> then you haven't don
On Fri, Jun 12, 2020 at 12:22:13PM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 11:42:08AM +0100, Russell King - ARM Linux admin
> wrote:
> > With the obvious mistakes fixed (extraneous 'i' and lack of default
> > case), it seems to still wor
On Fri, Jun 12, 2020 at 11:42:08AM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 11:18:20AM +0100, Russell King - ARM Linux admin
> wrote:
> > On Fri, Jun 12, 2020 at 11:01:15AM +0100, Russell King - ARM Linux admin
> > wrote:
> > > On Fri,
On Fri, Jun 12, 2020 at 11:18:20AM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 11:01:15AM +0100, Russell King - ARM Linux admin
> wrote:
> > On Fri, Jun 12, 2020 at 09:47:10AM +0100, Russell King - ARM Linux admin
> > wrote:
> > > On Fri,
On Fri, Jun 12, 2020 at 11:01:15AM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 09:47:10AM +0100, Russell King - ARM Linux admin
> wrote:
> > On Fri, Jun 12, 2020 at 10:38:47AM +0200, Sascha Hauer wrote:
> > > The Marvell MVNETA Ethernet controll
On Fri, Jun 12, 2020 at 09:47:10AM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 10:38:47AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > called DRSGMII. Depending on the Port MAC Control Reg
On Fri, Jun 12, 2020 at 10:38:47AM +0200, Sascha Hauer wrote:
> The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> called DRSGMII. Depending on the Port MAC Control Register0 PortType
> setting this seems to be either an overclocked SGMII mode or 2500BaseX.
>
> This patch adds
On Wed, Jun 10, 2020 at 08:14:03PM +0100, Jonathan McDowell wrote:
> Update the driver to use the new PHYLINK callbacks, removing the
> legacy adjust_link callback.
Looks good, there's a couple of issues / questions
> static void
> +qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsig
On Wed, Jun 10, 2020 at 08:15:13PM +0100, Jonathan McDowell wrote:
> This patch improves the handling of the SGMII interface on the QCA8K
> devices. Previously the driver did no configuration of the port, even if
> it was selected. We now configure it up in the appropriate
> PHY/MAC/Base-X mode dep
Hi Jonathan,
A quick read through on the first review...
On Mon, Jun 08, 2020 at 07:39:53PM +0100, Jonathan McDowell wrote:
> +static int
> +qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
> + struct phylink_link_state *state)
> +{
> + struct qca8k_priv
On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode
> called DRSGMII.
>
> This patch adds a corresponding phy-mode string 'drsgmii' and parses it
> from DT. The MVNETA then configures the SERDES protocol value
> acco
On Sun, Jun 07, 2020 at 06:29:32PM +0530, afzal mohammed wrote:
> Hi,
>
> On Sat, May 16, 2020 at 09:35:57AM +0200, Arnd Bergmann wrote:
> > On Sat, May 16, 2020 at 8:06 AM afzal mohammed
> > wrote:
>
> > > Okay, so the conclusion i take is,
> > > 1. VMSPLIT 4G/4G have to live alongside highmem
On Sat, Jun 06, 2020 at 11:59:09AM +0100, Jonathan McDowell wrote:
> So the device in question is a 7 port stand alone switch chip. There's a
> single SGMII port which is configurable between port 0 + 6 (they can
> also be configure up as RGMII, while the remaining 5 ports have their
> own phys).
>
On Sat, Jun 06, 2020 at 12:53:43AM +0100, Russell King - ARM Linux admin wrote:
> On Sat, Feb 29, 2020 at 11:04:56AM +0000, Russell King - ARM Linux admin
> wrote:
> > Adding Ted and Andreas...
> >
> > Here's the debugfs -n "id" output for dpkg.status.
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