Hi Suzuki,
On 2021-01-19 16:03, Suzuki K Poulose wrote:
On 1/19/21 9:51 AM, Sai Prakash Ranjan wrote:
Hi Al,
On 2021-01-19 14:06, Al Grant wrote:
Hi Sai,
From: saiprakash.ranjan=codeaurora@mg.codeaurora.org
Hi Mathieu,
On 2021-01-19 01:53, Mathieu Poirier wrote:
> On Fri, Jan 15, 2
Hi Al,
On 2021-01-19 14:06, Al Grant wrote:
Hi Sai,
From: saiprakash.ranjan=codeaurora@mg.codeaurora.org
Hi Mathieu,
On 2021-01-19 01:53, Mathieu Poirier wrote:
> On Fri, Jan 15, 2021 at 11:16:24AM +0530, Sai Prakash Ranjan wrote:
>> Hello Mathieu, Suzuki
>>
>>
Hi Mathieu,
On 2021-01-19 01:53, Mathieu Poirier wrote:
On Fri, Jan 15, 2021 at 11:16:24AM +0530, Sai Prakash Ranjan wrote:
Hello Mathieu, Suzuki
On 2020-10-15 21:32, Mathieu Poirier wrote:
> On Thu, Oct 15, 2020 at 06:15:22PM +0530, Sai Prakash Ranjan wrote:
> > On productio
On 2021-01-18 20:17, Mattias Nissler wrote:
On Fri, Jan 15, 2021 at 6:46 AM Sai Prakash Ranjan
wrote:
Hello Mathieu, Suzuki
On 2020-10-15 21:32, Mathieu Poirier wrote:
> On Thu, Oct 15, 2020 at 06:15:22PM +0530, Sai Prakash Ranjan wrote:
>> On production systems with ETM
On 2021-01-16 02:09, Stephen Boyd wrote:
Let's skip printing anything if there's nothing to see. This makes it
so
the file length is 0 instead of 1, for the newline, and helps scripts
figure out if there's anything to see in these files.
Cc: Sai Prakash Ranjan
Cc: Douglas Anderson
Cc: Dmitry
Hello Mathieu, Suzuki
On 2020-10-15 21:32, Mathieu Poirier wrote:
On Thu, Oct 15, 2020 at 06:15:22PM +0530, Sai Prakash Ranjan wrote:
On production systems with ETMs enabled, it is preferred to
exclude kernel mode(NS EL1) tracing for security concerns and
support only userspace(NS EL0) tracing
Hi Jordan,
On 2021-01-11 21:41, Jordan Crouse wrote:
On Mon, Jan 11, 2021 at 09:54:12AM +0530, Sai Prakash Ranjan wrote:
Hi Rob,
On 2021-01-08 22:16, Rob Clark wrote:
>On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
> wrote:
>>
>>On 2021-01-08 19:09, Konrad Dybcio wrote
such as video where this can be used for per-buffer based
mapping.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 3 +++
include/linux/iommu.h | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
address
space creation, in this case we set them for A6XX GPUs.
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++
drivers/gpu/drm/msm/msm_iommu.c | 3 +++
drivers/gpu/drm/msm/msm_mmu.h | 4
3 files changed, 10 insertions(+)
diff --git
Rename last-level cache quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to
IO_PGTABLE_QUIRK_PTW_LLC which is used to set the required TCR
attributes for non-coherent page table walker to be more generic
and in sync with the upcoming page protection flag IOMMU_LLC.
Signed-off-by: Sai Prakash Ranjan
ction flag.
The series slightly depends on following 2 patches posted earlier and
is based on msm-next branch:
* https://lore.kernel.org/patchwork/patch/1363008/
* https://lore.kernel.org/patchwork/patch/1363010/
Sai Prakash Ranjan (3):
iommu/io-pgtable: Rename last-level c
can
use it instead of open coding domain attribute setting for each
GPU.
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 -
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 23 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++--
3
Patch 1 is a fix to not set the attributes when CONFIG_QCOM_LLCC
is disabled and Patch 2 is a cleanup to create an a6xx specific address
space.
Sai Prakash Ranjan (2):
drm/msm: Add proper checks for GPU LLCC support
drm/msm/a6xx: Create an A6XX GPU specific address space
drivers/gpu/drm/msm
C)")
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.
On 2021-01-11 11:52, Sai Prakash Ranjan wrote:
Hi Isaac,
I gave this series a go on chromebook and saw these warnings
and several device probe failures, logs attached below:
WARN corresponds to this code in arm_lpae_map_by_pgsize()
if (WARN_ON(iaext || (paddr + size) >> cf
Hi Isaac,
On 2021-01-09 07:20, Isaac J. Manjarres wrote:
> The iommu_map_sg() code currently iterates through the given
> scatter-gather list, and in the worst case, invokes iommu_map()
> for each element in the scatter-gather list, which calls into
> the IOMMU driver through an indirect call.
On 2021-01-08 23:48, Will Deacon wrote:
On Fri, Jan 08, 2021 at 11:17:25AM +0530, Sai Prakash Ranjan wrote:
On 2021-01-07 22:27, isa...@codeaurora.org wrote:
> On 2021-01-06 03:56, Will Deacon wrote:
> > On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
>
On 2021-01-08 23:39, isa...@codeaurora.org wrote:
On 2021-01-07 21:47, Sai Prakash Ranjan wrote:
On 2021-01-07 22:27, isa...@codeaurora.org wrote:
On 2021-01-06 03:56, Will Deacon wrote:
On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: R
Hi Rob,
On 2021-01-08 22:16, Rob Clark wrote:
On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
wrote:
On 2021-01-08 19:09, Konrad Dybcio wrote:
>> Konrad, can you please test this below change without your change?
>
> This brings no difference, a BUG still happens. We're s
On 2021-01-08 19:09, Konrad Dybcio wrote:
Konrad, can you please test this below change without your change?
This brings no difference, a BUG still happens. We're still calling
to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
into an A640..
Also, relying on disabling
Hi Rob, Konrad,
On 2021-01-07 22:56, Rob Clark wrote:
> On Wed, Jan 6, 2021 at 8:50 PM Sai Prakash Ranjan
> wrote:
>>
>> On 2021-01-05 01:00, Konrad Dybcio wrote:
>> > Using this code on A5xx (and probably older too) causes a
>> > smmu bug.
>> >
On 2021-01-07 22:27, isa...@codeaurora.org wrote:
On 2021-01-06 03:56, Will Deacon wrote:
On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY
flag")
removed unused IOMMU_SYS_CACHE_ONLY prot flag
Hi Will,
On 2021-01-06 17:26, Will Deacon wrote:
On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag")
removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went
the memory type settin
On 2021-01-05 01:00, Konrad Dybcio wrote:
Using this code on A5xx (and probably older too) causes a
smmu bug.
Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system
cache(LLC)")
Signed-off-by: Konrad Dybcio
Tested-by: AngeloGioacchino Del Regno
---
Reviewed-by: S
d that patch, or would someone suggest a different fix
for
the CONFIG_QCOM_LLCC dependency issue?
Thanks, your patch looks good to me unless Rob has some other idea. Once
the recursive
dependency thing is sorted,
Reviewed-by: Sai Prakash Ranjan
Thanks,
Sai
--
QUALCOMM INDIA, on behalf
ed to mark the memory as normal sys-cached for GPU to use system cache.
Without this, the system cache lines are not allocated for GPU. We use
the IO_PGTABLE_QUIRK_ARM_OUTER_WBWA quirk instead of a page protection
flag as the flag cannot be exposed via DMA api because of no in-tree
users.
Signed-off-by: S
: Sai Prakash Ranjan
Cc: Douglas Anderson
Cc: Dmitry Baryshkov
Signed-off-by: Stephen Boyd
---
drivers/soc/qcom/socinfo.c | 40 +++---
1 file changed, 20 insertions(+), 20 deletions(-)
Reviewed-by: Sai Prakash Ranjan
diff --git a/drivers/soc/qcom/socinfo.c b
On Thu, Nov 26, 2020 at 9:16 AM Youghandhar Chintala
wrote:
> --- a/drivers/net/wireless/ath/ath10k/snoc.c
> +++ b/drivers/net/wireless/ath/ath10k/snoc.c
> @@ -1790,9 +1790,6 @@ static int ath10k_snoc_remove(struct platform_device
> *pdev)
>
> reinit_completion(>driver_recovery);
>
> -
version 2.
Signed-off-by: Manivannan Sadhasivam
---
Reviewed-by: Sai Prakash Ranjan
drivers/soc/qcom/llcc-qcom.c | 38 ++
include/linux/soc/qcom/llcc-qcom.h | 1 +
2 files changed, 39 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c
b/drivers/soc
0960 0
0x5>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ };
+
usb_2: usb@a8f8800 {
compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
reg = <0 0x0a8f8800 0 0x400&g
Hi Mani,
On 2020-11-27 17:41, Manivannan Sadhasivam wrote:
SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN
register
needs to be written to enable the Write Sub Cache for each SCID. Hence,
use a dedicated "write_scid_en" member with predefined values and write
them for SoCs
Add coresight components found on Qualcomm Technologies,
Inc. SM8150 SoC.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
---
Changes in v2:
* Rebase on top of qcom for-next branch
* Add reviewed-by tag collected from previous version
---
arch/arm64/boot/dts/qcom/sm8150.dtsi
Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
drivers/iommu/arm/arm-smmu/arm
Now that we have a struct io_pgtable_domain_attr with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 15 +--
drivers/iommu/arm/arm
the right attributes to cache the
hardware pagetables into the system cache.
Signed-off-by: Sharat Masetty
[saiprakash.ranjan: fix to set attr before device attach to iommu and rebase]
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
drivers
Add support for domain attribute DOMAIN_ATTR_IO_PGTABLE_CFG
to get/set pagetable configuration data which initially will
be used to set quirks and later can be extended to include
other pagetable configuration data.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c
Changes in v2:
* Addressed review comments and rebased on top of Jordan's split
pagetables series
Jordan Crouse (1):
drm/msm/a6xx: Add support for using system cache on MMU500 based
targets
Sai Prakash Ranjan (6):
iommu/io-pgtable: Add a domain attribute for pagetable configuration
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the outer-cacheability attributes set in the TCR for a
non-coherent page table walker when using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 10 --
include/linux/io-pgtable.h | 4
and
later can be extended to include other page table configuration
data.
Signed-off-by: Sai Prakash Ranjan
---
include/linux/io-pgtable.h | 4
include/linux/iommu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index
Prakash Ranjan
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 49685571dc0e..a1e22b974b77
On 2020-11-25 03:11, Will Deacon wrote:
On Mon, Nov 23, 2020 at 10:35:55PM +0530, Sai Prakash Ranjan wrote:
Add iommu domain attribute for pagetable configuration which
initially will be used to set quirks like for system cache aka
last level cache to be used by client drivers like GPU to set
On 2020-11-25 03:09, Will Deacon wrote:
On Mon, Nov 23, 2020 at 10:35:56PM +0530, Sai Prakash Ranjan wrote:
Now that we have a struct io_pgtable_domain_attr with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed-off
On 2020-11-24 00:52, Rob Clark wrote:
On Mon, Nov 23, 2020 at 9:01 AM Sai Prakash Ranjan
wrote:
On 2020-11-23 20:51, Will Deacon wrote:
> On Tue, Nov 17, 2020 at 08:00:39PM +0530, Sai Prakash Ranjan wrote:
>> Some hardware variants contain a system cache or the last level
>
Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
drivers/iommu/arm/arm-smmu/arm
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b
Now that we have a struct io_pgtable_domain_attr with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 8 +++-
drivers/iommu/arm/arm-smmu
the right attributes to cache the
hardware pagetables into the system cache.
Signed-off-by: Sharat Masetty
[saiprakash.ranjan: fix to set attr before device attach to iommu and rebase]
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
drivers
Prakash Ranjan
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 49685571dc0e..a1e22b974b77
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the outer-cacheability attributes set in the TCR for a
non-coherent page table walker when using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 10 --
include/linux/io-pgtable.h | 4
other page
table configuration data.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 20
drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 +
include/linux/io-pgtable.h| 4
include/linux/iommu.h | 1 +
4 files changed
):
drm/msm/a6xx: Add support for using system cache on MMU500 based
targets
Sai Prakash Ranjan (5):
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add domain attribute for pagetable configuration
iommu/arm-smmu: Move non-strict mode to use io_pgtable_domain_attr
On 2020-11-23 20:51, Will Deacon wrote:
On Tue, Nov 17, 2020 at 08:00:39PM +0530, Sai Prakash Ranjan wrote:
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache
On 2020-11-23 20:49, Will Deacon wrote:
On Tue, Nov 17, 2020 at 08:00:42PM +0530, Sai Prakash Ranjan wrote:
Now that we have a struct domain_attr_io_pgtbl_cfg with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed
On 2020-11-23 20:48, Will Deacon wrote:
On Tue, Nov 17, 2020 at 08:00:41PM +0530, Sai Prakash Ranjan wrote:
Add iommu domain attribute for pagetable configuration which
initially will be used to set quirks like for system cache aka
last level cache to be used by client drivers like GPU to set
On 2020-11-23 20:36, Will Deacon wrote:
On Tue, Nov 17, 2020 at 08:00:40PM +0530, Sai Prakash Ranjan wrote:
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu
dev_attr_store
sysfs_kf_write
Fixes: 99443ea19e8b ("coresight: Add generic TMC sg table framework")
Cc: sta...@vger.kernel.org
Signed-off-by: Mao Jinlong
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 ++
1 file changed, 2 insertions(+)
the access during the save/restore.
Found by code inspection.
Thanks for the patch, I did test at the time if these accesses
in save and restore cause any hang and they do not. But
this patch doesn't leave anything to chances, so its good.
Reviewed-by: Sai Prakash Ranjan
Tested-by: Sai Prakash
other page
table configuration data.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 25 +
drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 +
include/linux/io-pgtable.h| 4
include/linux/iommu.h | 1 +
4 files
Now that we have a struct domain_attr_io_pgtbl_cfg with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 7 ++-
drivers/iommu/arm/arm-smmu
Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
drivers/iommu/arm/arm-smmu/arm
Prakash Ranjan
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 49685571dc0e..a1e22b974b77
the right attributes to cache the
hardware pagetables into the system cache.
Signed-off-by: Sharat Masetty
[saiprakash.ranjan: fix to set attr before device attach to iommu and rebase]
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
drivers
comments and rebased on top of Jordan's split
pagetables series
Jordan Crouse (1):
drm/msm/a6xx: Add support for using system cache on MMU500 based
targets
Sai Prakash Ranjan (5):
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add domain attribute for pagetable
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 10 --
include/linux/io-pgtable.h | 4
2 files changed, 12 insertions
On 2020-11-12 15:05, Will Deacon wrote:
On Wed, Nov 11, 2020 at 12:10:50PM +0530, Sai Prakash Ranjan wrote:
On 2020-11-10 17:48, Will Deacon wrote:
> On Fri, Oct 30, 2020 at 02:53:09PM +0530, Sai Prakash Ranjan wrote:
> > Add iommu domain attribute for using system cache aka l
On 2020-11-10 17:48, Will Deacon wrote:
On Fri, Oct 30, 2020 at 02:53:09PM +0530, Sai Prakash Ranjan wrote:
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache
On 2020-11-10 17:48, Will Deacon wrote:
On Fri, Oct 30, 2020 at 02:53:08PM +0530, Sai Prakash Ranjan wrote:
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io
On 2020-11-05 15:03, Will Deacon wrote:
Hi Konrad,
[+Jeffrey]
On Thu, Nov 05, 2020 at 12:22:09AM +0100, Konrad Dybcio wrote:
This series adds Spectre mitigations and errata data for
Qualcomm KRYO2XX Gold (big) and Silver (LITTLE) series of
CPU cores, used for example in MSM8998 and
Hi,
On 2020-11-10 00:58, Konrad Dybcio wrote:
From what I see from the docs, this is the only version used
in MSM8998(silver cores are based on Cortex A53) and it maps
to r0p4. @Konrad, can you include (rap4 => r0p4) in comment.
Hi,
Thanks for looking into it. Could you perhaps check if
Hi Marc,
On 2020-11-05 14:59, Marc Zyngier wrote:
On 2020-11-04 23:22, Konrad Dybcio wrote:
QCOM KRYO2XX Silver cores are Cortex-A53 based and are
susceptible to the 845719 erratum. Add them to the lookup
list to apply the erratum.
Signed-off-by: Konrad Dybcio
---
On 2020-10-30 14:53, Sai Prakash Ranjan wrote:
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache to cache
both the GPU data buffers(like textures) as well
Hi Mathieu,
On 2020-10-30 22:18, Mathieu Poirier wrote:
On Fri, Oct 30, 2020 at 01:29:56PM +0530, Sai Prakash Ranjan wrote:
Hello guys,
On 2020-10-24 02:07, Mathieu Poirier wrote:
> On Fri, Oct 23, 2020 at 03:44:16PM +0200, Peter Zijlstra wrote:
> > On Fri, Oct 23, 2020 at 02:29:5
Prakash Ranjan
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 49685571dc0e..a1e22b974b77
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b/drivers/iommu/arm/arm
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 21
-instance
pagetables support
Changes in v2:
* Addressed review comments and rebased on top of Jordan's split
pagetables series
Jordan Crouse (1):
drm/msm/a6xx: Add support for using system cache on MMU500 based
targets
Sai Prakash Ranjan (4):
iommu/io-pgtable-arm: Add support to use
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +
drivers/iommu
and modify the programming sequence
accordingly.
[1] https://patchwork.freedesktop.org/series/83037/
Signed-off-by: Jordan Crouse
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
2 files
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 7 ++-
include/linux/io-pgtable.h | 4
2 files changed, 10 insertions(+), 1
.
Signed-off-by: Sharat Masetty
[saiprakash.ranjan: fix to set attr before device attach to iommu and rebase]
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++
drivers/gpu/drm/msm/adreno
Hello guys,
On 2020-10-24 02:07, Mathieu Poirier wrote:
On Fri, Oct 23, 2020 at 03:44:16PM +0200, Peter Zijlstra wrote:
On Fri, Oct 23, 2020 at 02:29:54PM +0100, Suzuki Poulose wrote:
> On 10/23/20 2:16 PM, Peter Zijlstra wrote:
> > On Fri, Oct 23, 2020 at 01:56:47PM +0100, Suzuki Poulose
On 2020-10-27 21:10, Robin Murphy wrote:
On 2020-10-26 18:54, Jordan Crouse wrote:
This is an extension to the series [1] to enable the System Cache
(LLC) for
Adreno a6xx targets.
GPU targets with an MMU-500 attached have a slightly different process
for
enabling system cache. Use the
On 2020-10-27 20:09, Jordan Crouse wrote:
On Tue, Oct 27, 2020 at 12:38:02PM +0530, Sai Prakash Ranjan wrote:
On 2020-10-27 00:24, Jordan Crouse wrote:
>This is an extension to the series [1] to enable the System Cache (LLC)
>for
>Adreno a6xx targets.
>
>GPU targets with an M
On 2020-10-27 00:24, Jordan Crouse wrote:
This is an extension to the series [1] to enable the System Cache (LLC)
for
Adreno a6xx targets.
GPU targets with an MMU-500 attached have a slightly different process
for
enabling system cache. Use the compatible string on the IOMMU phandle
to see
Hi Bjorn,
On 2020-09-15 12:25, Sai Prakash Ranjan wrote:
Older chipsets may not be allowed to configure certain LLCC registers
as that is handled by the secure side software. However, this is not
the case for newer chipsets and they must configure these registers
according to the contents
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b/drivers/iommu/arm/arm
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 21
Prakash Ranjan
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 49685571dc0e..a1e22b974b77
.
Signed-off-by: Sharat Masetty
[saiprakash.ranjan: fix to set attr before device attach to iommu and rebase]
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++
drivers/gpu/drm/msm/adreno
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +
drivers/iommu
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 7 ++-
include/linux/io-pgtable.h | 4
2 files changed, 10 insertions(+), 1
comments and rebased on top of Jordan's split
pagetables series
Sai Prakash Ranjan (4):
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add domain attribute for system cache
iommu: arm-smmu-impl: Use table to list QCOM implementations
iommu: arm-smmu-impl: Add a space
On 2020-10-22 19:04, Peter Zijlstra wrote:
On Thu, Oct 22, 2020 at 06:19:37PM +0530, Sai Prakash Ranjan wrote:
On 2020-10-22 17:02, Peter Zijlstra wrote:
> On Thu, Oct 22, 2020 at 04:27:52PM +0530, Sai Prakash Ranjan wrote:
>
> > Looking at the ETR and other places in the
On 2020-10-22 17:02, Peter Zijlstra wrote:
On Thu, Oct 22, 2020 at 04:27:52PM +0530, Sai Prakash Ranjan wrote:
Looking at the ETR and other places in the kernel, ETF and the
ETB are the only places trying to dereference the task(owner)
in tmc_enable_etf_sink_perf() which is also called from
On 2020-10-22 16:40, Sai Prakash Ranjan wrote:
On 2020-10-22 16:27, Sai Prakash Ranjan wrote:
There was a report of NULL pointer dereference in ETF enable
path for perf CS mode with PID monitoring. It is almost 100%
reproducible when the process to monitor is something very
active
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