On Thu, December 3, 2015 08:39, Philipp Zabel wrote:
> Am Mittwoch, den 02.12.2015, 21:03 + schrieb Simon Arlott:
>> +periph_soft_rst: reset-controller {
>> +compatible = "brcm,bcm63168-reset", "brcm,bcm6345-reset";
>> +regmap = <_cntl>
On Fri, December 4, 2015 14:30, Rob Herring wrote:
> On Mon, Nov 30, 2015 at 08:52:55PM +0000, Simon Arlott wrote:
>> +periph_clk: periph_clk {
>> +compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
>> +regmap = <_cntl>;
>
&
On Fri, December 4, 2015 11:00, Mark Brown wrote:
> On Thu, Dec 03, 2015 at 11:51:16PM +0000, Simon Arlott wrote:
>> On 03/12/15 23:45, Mark Brown wrote:
>
>> > Are you *sure* these are regulators and not power domains? These names
>> > look a lot like they could
On Fri, December 4, 2015 11:00, Mark Brown wrote:
> On Thu, Dec 03, 2015 at 11:51:16PM +0000, Simon Arlott wrote:
>> On 03/12/15 23:45, Mark Brown wrote:
>
>> > Are you *sure* these are regulators and not power domains? These names
>> > look a lot like they could
On Fri, December 4, 2015 16:04, Jonas Gorski wrote:
> On Thu, Dec 3, 2015 at 12:41 AM, Simon Arlott <si...@fire.lp0.eu> wrote:
>> + * "brcm,nand-bcm6368"
>> + - compatible: should contain "brcm,nand-bcm", "brcm,nand-bcm6368"
>> +
On Fri, December 4, 2015 14:30, Rob Herring wrote:
> On Mon, Nov 30, 2015 at 08:52:55PM +0000, Simon Arlott wrote:
>> +periph_clk: periph_clk {
>> +compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
>> +regmap = <_cntl>;
>
&
On Thu, December 3, 2015 08:39, Philipp Zabel wrote:
> Am Mittwoch, den 02.12.2015, 21:03 + schrieb Simon Arlott:
>> +periph_soft_rst: reset-controller {
>> +compatible = "brcm,bcm63168-reset", "brcm,bcm6345-reset";
>> +regmap = <_cntl>
On 03/12/15 23:45, Mark Brown wrote:
> On Thu, Dec 03, 2015 at 11:38:28PM +0000, Simon Arlott wrote:
>
>> #define MISC_IDDQ_CTRL_GMAC (1<<18)
>> #define MISC_IDDQ_CTRL_WLAN_PADS(1<<13)
>> #define MISC_IDDQ_CTRL_PCIE (1<<12)
>
On 03/12/15 15:05, Mark Brown wrote:
> On Thu, Dec 03, 2015 at 08:14:33AM +0000, Simon Arlott wrote:
>> On 03/12/15 00:06, Mark Brown wrote:
>
>> > this it should know at least something about how to control the device
>> > from the compatible string. If you're mak
, then handle
the CTRL_READY interrupt.
Signed-off-by: Simon Arlott
---
drivers/mtd/nand/brcmnand/Makefile | 1 +
drivers/mtd/nand/brcmnand/bcm6368_nand.c | 145 +++
2 files changed, 146 insertions(+)
create mode 100644 drivers/mtd/nand/brcmnand/bcm6368_nand.c
Attempt to enable a clock named "nand" as some SoCs have a clock for the
controller that needs to be enabled.
Signed-off-by: Simon Arlott
---
Removed ctrl->clk not NULL check.
drivers/mtd/nand/brcmnand/brcmnand.c | 64
1 file changed, 50 inse
Add device tree binding for NAND on the BCM6368.
The BCM6368 has a NAND interrupt register with combined status and enable
registers. It also requires a clock, so add an optional clock to the
common brcmnand binding.
Signed-off-by: Simon Arlott
---
.../devicetree/bindings/mtd/brcm,brcmnand.txt
The BCM6345 contains clocks gated with a register. Clocks are indexed
by bits in the register and are active high. Clock gate bits are
interleaved with other status bits and configurable clocks in the same
register.
Enabled by default for BMIPS_GENERIC.
Signed-off-by: Simon Arlott
---
Renamed
", "nand",
+ "tbus", "robosw250";
+};
+
+timer_clk: timer_clk {
+ compatible = "brcm,bcm63168-gate-clk", "brcm,bcm6345-gate-clk";
+ regmap = <_cntl>;
+ offset = <0x4>;
+
+ #clock-cells =
On 03/12/15 00:06, Mark Brown wrote:
> On Wed, Dec 02, 2015 at 08:26:36PM +0000, Simon Arlott wrote:
>> On 02/12/15 12:53, Mark Brown wrote:
>
>> > This is the sort of thing you can pick up from the SoC compatible
>> > strings. As things stand there
On 03/12/15 00:06, Mark Brown wrote:
> On Wed, Dec 02, 2015 at 08:26:36PM +0000, Simon Arlott wrote:
>> On 02/12/15 12:53, Mark Brown wrote:
>
>> > This is the sort of thing you can pick up from the SoC compatible
>> > strings. As things stand there
Add device tree binding for NAND on the BCM6368.
The BCM6368 has a NAND interrupt register with combined status and enable
registers. It also requires a clock, so add an optional clock to the
common brcmnand binding.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
.../devicetree/bi
Attempt to enable a clock named "nand" as some SoCs have a clock for the
controller that needs to be enabled.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
Removed ctrl->clk not NULL check.
drivers/mtd/nand/brcmnand/brcmnand.c | 64
, then handle
the CTRL_READY interrupt.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
drivers/mtd/nand/brcmnand/Makefile | 1 +
drivers/mtd/nand/brcmnand/bcm6368_nand.c | 145 +++
2 files changed, 146 insertions(+)
create mode 100644 drivers/mt
"phymips", "gmac", "nand",
+ "tbus", "robosw250";
+};
+
+timer_clk: timer_clk {
+ compatible = "brcm,bcm63168-gate-clk", "brcm,bcm6345-gate-clk";
+ regmap = <_cntl>;
+ offset = <0x4>
The BCM6345 contains clocks gated with a register. Clocks are indexed
by bits in the register and are active high. Clock gate bits are
interleaved with other status bits and configurable clocks in the same
register.
Enabled by default for BMIPS_GENERIC.
Signed-off-by: Simon Arlott <
On 03/12/15 23:45, Mark Brown wrote:
> On Thu, Dec 03, 2015 at 11:38:28PM +0000, Simon Arlott wrote:
>
>> #define MISC_IDDQ_CTRL_GMAC (1<<18)
>> #define MISC_IDDQ_CTRL_WLAN_PADS(1<<13)
>> #define MISC_IDDQ_CTRL_PCIE (1<<12)
>
On 03/12/15 15:05, Mark Brown wrote:
> On Thu, Dec 03, 2015 at 08:14:33AM +0000, Simon Arlott wrote:
>> On 03/12/15 00:06, Mark Brown wrote:
>
>> > this it should know at least something about how to control the device
>> > from the compatible string. If you're mak
, then handle
the CTRL_READY interrupt.
Signed-off-by: Simon Arlott
---
Renamed from BCM63268, moved clock to brcmnand.
drivers/mtd/nand/brcmnand/Makefile | 1 +
drivers/mtd/nand/brcmnand/bcm6368_nand.c | 145 +++
2 files changed, 146 insertions(+)
create mode
Attempt to enable a clock named "nand" as some SoCs have a clock for the
controller that needs to be enabled.
Signed-off-by: Simon Arlott
---
drivers/mtd/nand/brcmnand/brcmnand.c | 69
1 file changed, 54 insertions(+), 15 deletions(-)
diff --git
Add device tree binding for NAND on the BCM6368.
The BCM6368 has a NAND interrupt register with combined status and enable
registers. It also requires a clock, so add an optional clock to the
common brcmnand binding.
Signed-off-by: Simon Arlott
---
Renamed from BCM63268, made clock a generic
the controller will still return an uncorrectable error if the page is
erased but has 1 or more bit flips.
--
Simon Arlott
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
The BCM6345 contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile| 17 +++---
drivers/reset/bcm
Add device tree binding for the BCM6345 soft reset controller.
The BCM6345 contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott
---
Renamed to bcm6345, removed "mask" property.
.../bindings/reset/brcm,bcm6345
On 02/12/15 18:03, Florian Fainelli wrote:
> 2015-11-30 12:58 GMT-08:00 Simon Arlott :
>> The BCM63xx contains a soft-reset controller activated by setting
>> a bit (that must previously have cleared).
>>
>> Signed-off-by: Simon Arlott
>> ---
>> MAINTAINER
On 02/12/15 20:21, Brian Norris wrote:
> Hi Simon,
>
> On Wed, Dec 02, 2015 at 08:12:32PM +0000, Simon Arlott wrote:
>> On 02/12/15 20:00, Brian Norris wrote:
>> > On Wed, Dec 02, 2015 at 07:41:07PM +, Simon Arlott wrote:
>> >> I've created a bcm963268part
On 02/12/15 12:53, Mark Brown wrote:
> On Wed, Dec 02, 2015 at 12:45:50PM -0000, Simon Arlott wrote:
>> On Tue, December 1, 2015 22:16, Mark Brown wrote:
>
>> > Why are these in the DT, I would expect that if this is a driver for a
>> > specific SoC all these propert
On 01/12/15 10:41, Jonas Gorski wrote:
> On Sat, Nov 28, 2015 at 8:23 PM, Simon Arlott wrote:
>> +
>> + /* Go to start of buffer */
>> + buf -= FC_WORDS;
>> +
>> + /* Erased if all data bytes are 0xFF */
>> + buf_erased =
On 02/12/15 20:00, Brian Norris wrote:
> Hi,
>
> On Wed, Dec 02, 2015 at 07:41:07PM +0000, Simon Arlott wrote:
>> >> + nand0: nandcs@0 {
>> >> + compatible = "brcm,nandcs";
>> >> +
>> >> + #address-cells = <0>
On 02/12/15 19:38, Florian Fainelli wrote:
> 2015-12-02 11:05 GMT-08:00 Brian Norris :
>> + Broadcom list + Kamal
>>
>> On Tue, Nov 24, 2015 at 08:19:37PM -, Simon Arlott wrote:
>>> Add device tree binding for NAND on the BCM63268.
>>>
>>
On 02/12/15 19:18, Brian Norris wrote:
> + Broadcom list + Kamal
>
> Hi Simon,
>
> On Wed, Nov 25, 2015 at 07:49:13PM +0000, Simon Arlott wrote:
>> The BCM63268 has a NAND interrupt register with combined status and enable
>> registers. It also has a clock for the
On 02/12/15 19:05, Brian Norris wrote:
> + Broadcom list + Kamal
>
> On Tue, Nov 24, 2015 at 08:19:37PM -0000, Simon Arlott wrote:
>> Add device tree binding for NAND on the BCM63268.
>>
>> The BCM63268 has a NAND interrupt register with combined status and enable
>
On Tue, December 1, 2015 22:16, Mark Brown wrote:
> On Mon, Nov 30, 2015 at 08:30:07PM +0000, Simon Arlott wrote:
>
>> +- offset: register offset
>> +- mask: register enable mask
>> +- startup-delay-us: startup time in microseconds
>
> Why are t
On 02/12/15 19:18, Brian Norris wrote:
> + Broadcom list + Kamal
>
> Hi Simon,
>
> On Wed, Nov 25, 2015 at 07:49:13PM +0000, Simon Arlott wrote:
>> The BCM63268 has a NAND interrupt register with combined status and enable
>> registers. It also has a clock for the
On 01/12/15 10:41, Jonas Gorski wrote:
> On Sat, Nov 28, 2015 at 8:23 PM, Simon Arlott <si...@fire.lp0.eu> wrote:
>> +
>> + /* Go to start of buffer */
>> + buf -= FC_WORDS;
>> +
>> + /* Erased if all data bytes are 0xFF */
>> +
On 02/12/15 19:05, Brian Norris wrote:
> + Broadcom list + Kamal
>
> On Tue, Nov 24, 2015 at 08:19:37PM -0000, Simon Arlott wrote:
>> Add device tree binding for NAND on the BCM63268.
>>
>> The BCM63268 has a NAND interrupt register with combined status and enable
>
On 02/12/15 19:38, Florian Fainelli wrote:
> 2015-12-02 11:05 GMT-08:00 Brian Norris <computersforpe...@gmail.com>:
>> + Broadcom list + Kamal
>>
>> On Tue, Nov 24, 2015 at 08:19:37PM -, Simon Arlott wrote:
>>> Add device tree binding for NAND on the BCM63
On 02/12/15 12:53, Mark Brown wrote:
> On Wed, Dec 02, 2015 at 12:45:50PM -0000, Simon Arlott wrote:
>> On Tue, December 1, 2015 22:16, Mark Brown wrote:
>
>> > Why are these in the DT, I would expect that if this is a driver for a
>> > specific SoC all these propert
On 02/12/15 20:00, Brian Norris wrote:
> Hi,
>
> On Wed, Dec 02, 2015 at 07:41:07PM +0000, Simon Arlott wrote:
>> >> + nand0: nandcs@0 {
>> >> + compatible = "brcm,nandcs";
>> >> +
>> >> + #address-cells = <0>
On 02/12/15 20:21, Brian Norris wrote:
> Hi Simon,
>
> On Wed, Dec 02, 2015 at 08:12:32PM +0000, Simon Arlott wrote:
>> On 02/12/15 20:00, Brian Norris wrote:
>> > On Wed, Dec 02, 2015 at 07:41:07PM +, Simon Arlott wrote:
>> >> I've created a bcm963268part
On 02/12/15 18:03, Florian Fainelli wrote:
> 2015-11-30 12:58 GMT-08:00 Simon Arlott <si...@fire.lp0.eu>:
>> The BCM63xx contains a soft-reset controller activated by setting
>> a bit (that must previously have cleared).
>>
>> Signed-off-by: Simon Arlott <si...
Add device tree binding for the BCM6345 soft reset controller.
The BCM6345 contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
Renamed to bcm6345, removed "mask" property.
.../bin
The BCM6345 contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile
, then handle
the CTRL_READY interrupt.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
Renamed from BCM63268, moved clock to brcmnand.
drivers/mtd/nand/brcmnand/Makefile | 1 +
drivers/mtd/nand/brcmnand/bcm6368_nand.c | 145 +++
2 files change
Add device tree binding for NAND on the BCM6368.
The BCM6368 has a NAND interrupt register with combined status and enable
registers. It also requires a clock, so add an optional clock to the
common brcmnand binding.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
Renamed from BCM63268
Attempt to enable a clock named "nand" as some SoCs have a clock for the
controller that needs to be enabled.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
drivers/mtd/nand/brcmnand/brcmnand.c | 69
1 file changed, 54 insertions(
On Tue, December 1, 2015 22:16, Mark Brown wrote:
> On Mon, Nov 30, 2015 at 08:30:07PM +0000, Simon Arlott wrote:
>
>> +- offset: register offset
>> +- mask: register enable mask
>> +- startup-delay-us: startup time in microseconds
>
> Why are t
erased pages at all. I don't know if
the controller will still return an uncorrectable error if the page is
erased but has 1 or more bit flips.
--
Simon Arlott
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.ker
Add of_match_table for "brcm,bcm6345-wdt".
Use a NULL clock name when not on mach-bcm63xx so that the device tree
clock name does not have to be "periph".
Allow the watchdog to be selected on BMIPS_GENERIC and select the BCM6345
timer interrupt handler.
Signed-off-by: Simon
with the watchdog if an interrupt occurs) and remove its
exported functions.
Use the timer interrupt directly in bcm63xx_wdt.
Signed-off-by: Simon Arlott
---
arch/mips/bcm63xx/dev-wdt.c| 7 +
arch/mips/bcm63xx/timer.c | 181
machine types.
Signed-off-by: Simon Arlott
---
MAINTAINERS | 1 +
arch/mips/bcm63xx/prom.c | 1 +
arch/mips/bcm63xx/setup.c | 1 +
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 22
Warn when the device is registered if the hardware watchdog is currently
running and report the remaining time left.
Signed-off-by: Simon Arlott
---
drivers/watchdog/bcm63xx_wdt.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog
Return the remaining time from the hardware control register.
Signed-off-by: Simon Arlott
---
drivers/watchdog/bcm63xx_wdt.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
index 0a19731..ab4a794 100644
Instead of using a fixed clock HZ in the driver, obtain it from the
"periph" clk that the watchdog timer uses.
Signed-off-by: Simon Arlott
Reviewed-by: Florian Fainelli
---
drivers/watchdog/bcm63xx_wdt.c | 36 +++-
1 file changed, 31 insertions(+), 5
Convert bcm63xx_wdt to use WATCHDOG_CORE.
The default and maximum time constants that are only used once have been
moved to the initialisation of the struct watchdog_device.
Signed-off-by: Simon Arlott
---
drivers/watchdog/Kconfig | 1 +
drivers/watchdog/bcm63xx_wdt.c | 259
,
reducing the maximum timeout from 256 seconds to 85 seconds
(2^32 / WDT_HZ).
Signed-off-by: Simon Arlott
---
drivers/watchdog/bcm63xx_wdt.c | 125 -
1 file changed, 73 insertions(+), 52 deletions(-)
diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog
Add device tree binding for the BCM6345 watchdog.
This uses the BCM6345 timer for its warning interrupt.
Signed-off-by: Simon Arlott
Acked-by: Rob Herring
---
.../bindings/watchdog/brcm,bcm6345-wdt.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644
be added later if required without changing the device
tree binding.
Signed-off-by: Simon Arlott
---
drivers/irqchip/Kconfig| 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-bcm6345-l2-timer.c | 386 +
3 files changed, 392
Add device tree bindings for the BCM6345/BCM6318 timers. This is required
for the BCM6345 watchdog which needs to respond to one of the timer
interrupts.
Signed-off-by: Simon Arlott
Acked-by: Rob Herring
---
.../bindings/timer/brcm,bcm6318-timer.txt | 44
Return the remaining time from the hardware control register.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
drivers/watchdog/bcm63xx_wdt.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
index 0
Add of_match_table for "brcm,bcm6345-wdt".
Use a NULL clock name when not on mach-bcm63xx so that the device tree
clock name does not have to be "periph".
Allow the watchdog to be selected on BMIPS_GENERIC and select the BCM6345
timer interrupt handler.
Signed-off-
Convert bcm63xx_wdt to use WATCHDOG_CORE.
The default and maximum time constants that are only used once have been
moved to the initialisation of the struct watchdog_device.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
drivers/watchdog/Kconfig | 1 +
drivers/wa
Instead of using a fixed clock HZ in the driver, obtain it from the
"periph" clk that the watchdog timer uses.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
---
drivers/watchdog/bcm63xx_wdt.c | 36 ++
Add device tree binding for the BCM6345 watchdog.
This uses the BCM6345 timer for its warning interrupt.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
Acked-by: Rob Herring <r...@kernel.org>
---
.../bindings/watchdog/brcm,bcm6345-wdt.txt | 35 ++
1 file
Warn when the device is registered if the hardware watchdog is currently
running and report the remaining time left.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
drivers/watchdog/bcm63xx_wdt.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff
with the watchdog if an interrupt occurs) and remove its
exported functions.
Use the timer interrupt directly in bcm63xx_wdt.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
arch/mips/bcm63xx/dev-wdt.c| 7 +
arch/mips/bcm63xx/timer.c
machine types.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
MAINTAINERS | 1 +
arch/mips/bcm63xx/prom.c | 1 +
arch/mips/bcm63xx/setup.c | 1 +
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.
Add device tree bindings for the BCM6345/BCM6318 timers. This is required
for the BCM6345 watchdog which needs to respond to one of the timer
interrupts.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
Acked-by: Rob Herring <r...@kernel.org>
---
.../bindings/timer/brcm,bcm63
be added later if required without changing the device
tree binding.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
drivers/irqchip/Kconfig| 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-bcm6345-l2-timer.c | 386 ++
,
reducing the maximum timeout from 256 seconds to 85 seconds
(2^32 / WDT_HZ).
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
drivers/watchdog/bcm63xx_wdt.c | 125 -
1 file changed, 73 insertions(+), 52 deletions(-)
diff --git a/drivers/watchdog/bcm63xx_w
The BCM63xx contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile| 1 +
drivers/reset/reset-bcm63xx.c | 134
Add device tree binding for the BCM63xx soft reset controller.
The BCM63xx contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott
---
.../bindings/reset/brcm,bcm63xx-reset.txt | 37 ++
1 file
The BCM63xx contains clocks gated with a register. Clocks are indexed
by bits in the register and are active high. Clock gate bits are
interleaved with other status bits and configurable clocks in the same
register.
Enabled by default for BMIPS_GENERIC.
Signed-off-by: Simon Arlott
;nand",
+ "tbus", "robosw250";
+};
+
+timer_clk: timer_clk {
+ compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
+ regmap = <_cntl>;
+ offset = <0x4>;
+
+ #clock-cells = <1>
The BCM63xx has one or more registers with bits that act as regulators
to enable/disable power to individual chip peripherals.
Signed-off-by: Simon Arlott
---
On 30/11/15 20:30, Simon Arlott wrote:
> + /* Only status change is supported, regardless of DT init data */
> + ini
The BCM63xx has one or more registers with bits that act as regulators
to enable/disable power to individual chip peripherals.
Signed-off-by: Simon Arlott
---
MAINTAINERS | 1 +
drivers/regulator/Kconfig | 9 +++
drivers/regulator/Makefile
The BCM63xx has one or more registers with bits that act as regulators
to enable/disable power to individual chip peripherals.
Signed-off-by: Simon Arlott
---
.../bindings/regulator/brcm,bcm63xx-regulator.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644
The BCM63xx has one or more registers with bits that act as regulators
to enable/disable power to individual chip peripherals.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
.../bindings/regulator/brcm,bcm63xx-regulator.txt | 33 ++
1 file changed, 33 inse
The BCM63xx has one or more registers with bits that act as regulators
to enable/disable power to individual chip peripherals.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
MAINTAINERS | 1 +
drivers/regulator/Kconfig | 9 +++
drivers/reg
The BCM63xx has one or more registers with bits that act as regulators
to enable/disable power to individual chip peripherals.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
On 30/11/15 20:30, Simon Arlott wrote:
> + /* Only status change is supported, regardless of DT
t;gmac", "nand",
+ "tbus", "robosw250";
+};
+
+timer_clk: timer_clk {
+ compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
+ regmap = <_cntl>;
+ offset = <0x4>;
+
+ #clock-ce
The BCM63xx contains clocks gated with a register. Clocks are indexed
by bits in the register and are active high. Clock gate bits are
interleaved with other status bits and configurable clocks in the same
register.
Enabled by default for BMIPS_GENERIC.
Signed-off-by: Simon Arlott <
Add device tree binding for the BCM63xx soft reset controller.
The BCM63xx contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
.../bindings/reset/brcm,bcm63xx-reset.txt
The BCM63xx contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile| 1 +
drivers
return -ENODEV or -ENOSYS
as errors and -EPROBE_DEFER doesn't make sense for a register, the
specific error is never propagated.
This is required for Broadcom BCM63xx SoCs that enable power to
individual peripherals by clearing a bit in the miscIddqCtrl register.
Signed-off-by: Simon Arlott
in the miscIddqCtrl register.
Signed-off-by: Simon Arlott
---
.../bindings/regulator/fixed-regulator.txt | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
b/Documentation/devicetree/bindings
.
Signed-off-by: Simon Arlott
---
drivers/mtd/nand/brcmnand/brcmnand.c | 107 ++-
1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c
b/drivers/mtd/nand/brcmnand/brcmnand.c
index 5f26b8a..0857af7 100644
--- a/drivers
be added later if required without changing the device
tree binding.
Signed-off-by: Simon Arlott
---
On 27/11/15 08:37, Thomas Gleixner wrote:
> Instead of having that pile of conditionals you could just define two
> functions and have a function pointer in struct bcm6345_timer which
be added later if required without changing the device
tree binding.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
On 27/11/15 08:37, Thomas Gleixner wrote:
> Instead of having that pile of conditionals you could just define two
> functions and have a function pointer in struct b
.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
drivers/mtd/nand/brcmnand/brcmnand.c | 107 ++-
1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c
b/drivers/mtd/nand/brcmnand/brcmnand.c
index 5f26b8a..0
in the miscIddqCtrl register.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
.../bindings/regulator/fixed-regulator.txt | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
b/Documen
return -ENODEV or -ENOSYS
as errors and -EPROBE_DEFER doesn't make sense for a register, the
specific error is never propagated.
This is required for Broadcom BCM63xx SoCs that enable power to
individual peripherals by clearing a bit in the miscIddqCtrl register.
Signed-off-by: Simon Arlott <
be added later if required without changing the device
tree binding.
Signed-off-by: Simon Arlott
---
On 24/11/15 22:36, Florian Fainelli wrote:
> On 24/11/15 14:10, Simon Arlott wrote:
>> +static inline u32 bcm6345_timer_read_int_status(struct bcm6345_timer *timer)
>> +{
>>
be added later if required without changing the device
tree binding.
Signed-off-by: Simon Arlott <si...@fire.lp0.eu>
---
On 24/11/15 22:36, Florian Fainelli wrote:
> On 24/11/15 14:10, Simon Arlott wrote:
>> +static inline u32 bcm6345_timer_read_int_status(struct bcm63
Add of_match_table for "brcm,bcm6345-wdt".
Use a NULL clock name when not on mach-bcm63xx so that the device tree
clock name does not have to be "periph".
Allow the watchdog to be selected on BMIPS_GENERIC and select the BCM6345
timer interrupt handler.
Signed-off-by: Simon
101 - 200 of 698 matches
Mail list logo
