Re: [PATCH v6 2/4] ARM: dts: tegra: Fix unit_address_vs_reg DTC warnings for /memory

On 23.05.2018 11:56, Krzysztof Kozlowski wrote: > Add a generic /memory node in each Tegra DTSI (with empty reg property, > to be overidden by each DTS) and set proper unit address for /memory > nodes to fix the DTC warnings: > > arch/arm/boot/dts/tegra20-harmony.dtb: Warning

Re: [PATCH v6 1/4] ARM: dts: tegra: Remove usage of deprecated skeleton.dtsi

evice tree do not have it yet... That makes the split indeed a bit less appealing. Anyway, now we have it, and I think it is still nice to have a separate change. Reviewed-by: Stefan Agner <ste...@agner.ch> -- Stefan > > --- > > Changes since v5: > 1. New patch, split wit

Re: [PATCH v6 1/4] ARM: dts: tegra: Remove usage of deprecated skeleton.dtsi

it yet... That makes the split indeed a bit less appealing. Anyway, now we have it, and I think it is still nice to have a separate change. Reviewed-by: Stefan Agner -- Stefan > > --- > > Changes since v5: > 1. New patch, split with skeleton.dtsi removal (suggested by Stefan).

Re: [PATCH v3 3/3] ARM: dts: imx6ull-colibri-wifi: remove operating points

mmit so it is clear that frequencies moved to the base device tree. Also, add a comment that frequency selection is now handled in code, e.g.: "The valid frequencies for a particular SKU are now selected by the cpufreq driver according to ratings stored in OTP fuses." But the two device tree changes with the driver do what they should do here, so: Tested-by: Stefan Agner <ste...@agner.ch> Reviewed-by: Stefan Agner <ste...@agner.ch> -- Stefan

Re: [PATCH v3 3/3] ARM: dts: imx6ull-colibri-wifi: remove operating points

moved to the base device tree. Also, add a comment that frequency selection is now handled in code, e.g.: "The valid frequencies for a particular SKU are now selected by the cpufreq driver according to ratings stored in OTP fuses." But the two device tree changes with the driver do what they should do here, so: Tested-by: Stefan Agner Reviewed-by: Stefan Agner -- Stefan

Re: [PATCH v3 1/3] cpufreq: imx6q: check speed grades for i.MX6ULL

X 6ULL, looks good! Tested-by: Stefan Agner <ste...@agner.ch> Reviewed-by: Stefan Agner <ste...@agner.ch> -- Stefan > --- > > Changes for v3: > - none > > Changes for v2: > - none > > drivers/cpufreq/imx6q-cpufreq.c | 29 +

Re: [PATCH v3 1/3] cpufreq: imx6q: check speed grades for i.MX6ULL

On 22.05.2018 08:28, Sébastien Szymanski wrote: > Check the max speed supported from the fuses for i.MX6ULL and update the > operating points table accordingly. > > Signed-off-by: Sébastien Szymanski Tested with a 528MHz and 792MHz rated i.MX 6ULL, looks good! Tested-by: Stefan Agn

Re: [PATCH v5 1/3] ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory

On 23.05.2018 10:34, Krzysztof Kozlowski wrote: > On Wed, May 23, 2018 at 10:22 AM, Stefan Agner <ste...@agner.ch> wrote: >> On 23.05.2018 09:05, Krzysztof Kozlowski wrote: >>> On Thu, May 17, 2018 at 1:39 PM, Stefan Agner <ste...@agner.ch> wrote: >>>>

Re: [PATCH v5 1/3] ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory

On 23.05.2018 10:34, Krzysztof Kozlowski wrote: > On Wed, May 23, 2018 at 10:22 AM, Stefan Agner wrote: >> On 23.05.2018 09:05, Krzysztof Kozlowski wrote: >>> On Thu, May 17, 2018 at 1:39 PM, Stefan Agner wrote: >>>> On 17.05.2018 09:45, Krzysztof Kozlowsk

Re: [PATCH v5 1/3] ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory

On 23.05.2018 09:05, Krzysztof Kozlowski wrote: > On Thu, May 17, 2018 at 1:39 PM, Stefan Agner <ste...@agner.ch> wrote: >> On 17.05.2018 09:45, Krzysztof Kozlowski wrote: >>> Remove the usage of skeleton.dtsi and add necessary properties to /memory >>

Re: [PATCH v5 1/3] ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory

On 23.05.2018 09:05, Krzysztof Kozlowski wrote: > On Thu, May 17, 2018 at 1:39 PM, Stefan Agner wrote: >> On 17.05.2018 09:45, Krzysztof Kozlowski wrote: >>> Remove the usage of skeleton.dtsi and add necessary properties to /memory >>> node to fix the DTC warnings: &g

Re: [PATCH V2 3/3] ARM: dts: imx7: correct enet ipg clock

On 18.05.2018 03:01, Anson Huang wrote: > ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK > rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus > clock. > > Based on Andy Duan's patch from the NXP kernel tree. > > Signed-off-by: Anson Huang <anson.h

Re: [PATCH V2 3/3] ARM: dts: imx7: correct enet ipg clock

On 18.05.2018 03:01, Anson Huang wrote: > ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK > rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus > clock. > > Based on Andy Duan's patch from the NXP kernel tree. > > Signed-off-by: Anson Huang Review

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

Hi, I do have some questions for some areas I wanted to improve in the next revision. But I would like to make sure that the way I would like to implement aligns with the MTD subsystem. On 22.05.2018 14:07, Stefan Agner wrote: > Add support for the NAND flash controller found on NVIDIA > T

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

Hi, I do have some questions for some areas I wanted to improve in the next revision. But I would like to make sure that the way I would like to implement aligns with the MTD subsystem. On 22.05.2018 14:07, Stefan Agner wrote: > Add support for the NAND flash controller found on NVIDIA > T

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

On 22.05.2018 15:34, Dmitry Osipenko wrote: > On 22.05.2018 15:19, Stefan Agner wrote: >> [review sent to my first patch sent off-ml, moving to ml thread] >> >> On 21.05.2018 16:05, Dmitry Osipenko wrote: >>> Hello Stefan, >>> >>> I don't have ex

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

On 22.05.2018 15:34, Dmitry Osipenko wrote: > On 22.05.2018 15:19, Stefan Agner wrote: >> [review sent to my first patch sent off-ml, moving to ml thread] >> >> On 21.05.2018 16:05, Dmitry Osipenko wrote: >>> Hello Stefan, >>> >>> I don't have ex

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

ugh I've couple > minor > comments. > > On 21.05.2018 03:16, Stefan Agner wrote: >> Add support for the NAND flash controller found on NVIDIA >> Tegra 2 SoCs. This implementation does not make use of the >> command queue feature. Regular operations/data transfers are >&g

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

ugh I've couple > minor > comments. > > On 21.05.2018 03:16, Stefan Agner wrote: >> Add support for the NAND flash controller found on NVIDIA >> Tegra 2 SoCs. This implementation does not make use of the >> command queue feature. Regular operations/data transfers are >&g

[RESEND PATCH 5/5] ARM: tegra: enable NAND flash on Colibri T20

From: Lucas Stach <d...@lynxeye.de> This enables the on-module ONFI conformant NAND flash. Signed-off-by: Lucas Stach <d...@lynxeye.de> Signed-off-by: Stefan Agner <ste...@agner.ch> --- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 7 +++ 1 file changed, 7 insertions(+)

[RESEND PATCH 5/5] ARM: tegra: enable NAND flash on Colibri T20

From: Lucas Stach This enables the on-module ONFI conformant NAND flash. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner --- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm

[RESEND PATCH 0/5] mtd: rawnand: add NVIDIA Tegra NAND flash support

a20: init NDFLASH clock to sensible rate ARM: tegra: add Tegra20 NAND flash controller node ARM: tegra: enable NAND flash on Colibri T20 Stefan Agner (1): mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver .../bindings/mtd/nvidia,tegra20-nand.txt | 29 + MAINTAIN

[RESEND PATCH 0/5] mtd: rawnand: add NVIDIA Tegra NAND flash support

a20: init NDFLASH clock to sensible rate ARM: tegra: add Tegra20 NAND flash controller node ARM: tegra: enable NAND flash on Colibri T20 Stefan Agner (1): mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver .../bindings/mtd/nvidia,tegra20-nand.txt | 29 + MAINTAIN

[RESEND PATCH 4/5] ARM: tegra: add Tegra20 NAND flash controller node

From: Lucas Stach <d...@lynxeye.de> Add basic controller description to be extended by individual boards. Signed-off-by: Lucas Stach <d...@lynxeye.de> Signed-off-by: Stefan Agner <ste...@agner.ch> --- arch/arm/boot/dts/tegra20.dtsi | 13 + 1 file changed, 13 i

[RESEND PATCH 4/5] ARM: tegra: add Tegra20 NAND flash controller node

From: Lucas Stach Add basic controller description to be extended by individual boards. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner --- arch/arm/boot/dts/tegra20.dtsi | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot

[RESEND PATCH 1/5] mtd: rawnand: tegra: add devicetree binding

From: Lucas Stach <d...@lynxeye.de> This adds the devicetree binding for the Tegra 2 NAND flash controller. Signed-off-by: Lucas Stach <d...@lynxeye.de> Signed-off-by: Stefan Agner <ste...@agner.ch> --- .../bindings/mtd/nvidia,tegra20-nand.txt | 29 +++

[RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

<d...@lynxeye.de> Signed-off-by: Stefan Agner <ste...@agner.ch> --- MAINTAINERS | 7 + drivers/mtd/nand/raw/Kconfig | 6 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/tegra_nand.c | 915 ++ 4 files

[RESEND PATCH 1/5] mtd: rawnand: tegra: add devicetree binding

From: Lucas Stach This adds the devicetree binding for the Tegra 2 NAND flash controller. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner --- .../bindings/mtd/nvidia,tegra20-nand.txt | 29 +++ 1 file changed, 29 insertions(+) create mode 100644 Documentation

[RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

Signed-off-by: Stefan Agner --- MAINTAINERS | 7 + drivers/mtd/nand/raw/Kconfig | 6 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/tegra_nand.c | 915 ++ 4 files changed, 929 insertions(+) create mode 100644 drivers

[RESEND PATCH 3/5] clk: tegra20: init NDFLASH clock to sensible rate

From: Lucas Stach <d...@lynxeye.de> Set up the NAND Flash controller clock to run at 150MHz instead of the rate set by the bootloader. This is a conservative rate which also yields good performance. Signed-off-by: Lucas Stach <d...@lynxeye.de> Signed-off-by: Stefan Agner <

[RESEND PATCH 3/5] clk: tegra20: init NDFLASH clock to sensible rate

From: Lucas Stach Set up the NAND Flash controller clock to run at 150MHz instead of the rate set by the bootloader. This is a conservative rate which also yields good performance. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner --- drivers/clk/tegra/clk-tegra20.c | 1 + 1 file

Re: [PATCH V2 2/3] clk: imx7d: correct enet clock CCGR registers

On 21.05.2018 04:35, Anson Huang wrote: > Hi, Stefan > > Anson Huang > Best Regards! > > >> -Original Message----- >> From: Stefan Agner [mailto:ste...@agner.ch] >> Sent: Friday, May 18, 2018 9:02 PM >> To: Anson Huang <anson.hu...@nxp.com> &

Re: [PATCH V2 2/3] clk: imx7d: correct enet clock CCGR registers

On 21.05.2018 04:35, Anson Huang wrote: > Hi, Stefan > > Anson Huang > Best Regards! > > >> -Original Message----- >> From: Stefan Agner [mailto:ste...@agner.ch] >> Sent: Friday, May 18, 2018 9:02 PM >> To: Anson Huang >> Cc: shawn...@

Re: [PATCH V2 1/3] clk: imx7d: correct enet phy ref clock gates

On 18.05.2018 03:01, Anson Huang wrote: > IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly, > there is no clock gate after it, rename it to > IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change. > > Signed-off-by: Anson Huang <anson.hu...@nxp.com> Reviewed-

Re: [PATCH V2 1/3] clk: imx7d: correct enet phy ref clock gates

On 18.05.2018 03:01, Anson Huang wrote: > IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly, > there is no clock gate after it, rename it to > IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change. > > Signed-off-by: Anson Huang Reviewed-by: Stefan Ag

Re: [PATCH V2 2/3] clk: imx7d: correct enet clock CCGR registers

On 18.05.2018 03:01, Anson Huang wrote: > Correct enet clock gates as below: > > CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks) > CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK > CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK > > Just rename unused

Re: [PATCH V2 2/3] clk: imx7d: correct enet clock CCGR registers

On 18.05.2018 03:01, Anson Huang wrote: > Correct enet clock gates as below: > > CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks) > CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK > CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK > > Just rename unused

Re: [PATCH v5 3/3] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

On 17.05.2018 09:45, Krzysztof Kozlowski wrote: > Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM > (with 1024 MB NAND) flavors. Both of them will use the same DTSI > expecting the bootloader to do the fixup of /memory node. However in > case it does not happen, let's stay on

Re: [PATCH v5 3/3] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

On 17.05.2018 09:45, Krzysztof Kozlowski wrote: > Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM > (with 1024 MB NAND) flavors. Both of them will use the same DTSI > expecting the bootloader to do the fixup of /memory node. However in > case it does not happen, let's stay on

Re: [PATCH v5 1/3] ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory

On 17.05.2018 09:45, Krzysztof Kozlowski wrote: > Remove the usage of skeleton.dtsi and add necessary properties to /memory > node to fix the DTC warnings: > > arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg): > /memory: node has a reg or ranges property, but no

Re: [PATCH v5 1/3] ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory

On 17.05.2018 09:45, Krzysztof Kozlowski wrote: > Remove the usage of skeleton.dtsi and add necessary properties to /memory > node to fix the DTC warnings: > > arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg): > /memory: node has a reg or ranges property, but no

Re: [PATCH v5 2/3] ARM: dts: tegra: Fix unit_address_vs_reg and avoid_unnecessary_addr_size DTC warnings

> Signed-off-by: Krzysztof Kozlowski <k...@kernel.org> Looks good! Reviewed-by: Stefan Agner <ste...@agner.ch> > > --- > > Changes since v4: > 1. None > --- > arch/arm/boot/dts/tegra30-apalis.dtsi | 4 +--- > arch/arm/boot/dts/tegra30-beaver.dts | 3 --- >

Re: [PATCH v5 2/3] ARM: dts: tegra: Fix unit_address_vs_reg and avoid_unnecessary_addr_size DTC warnings

t; > Signed-off-by: Krzysztof Kozlowski Looks good! Reviewed-by: Stefan Agner > > --- > > Changes since v4: > 1. None > --- > arch/arm/boot/dts/tegra30-apalis.dtsi | 4 +--- > arch/arm/boot/dts/tegra30-beaver.dts | 3 --- > arch/arm/boot/dts/tegra30-colibri.dtsi |

Re: [PATCH 1/2] clk: imx7d: correct enet clock CCGR register offset

On 17.05.2018 10:40, Anson Huang wrote: > Correct enet clock CCGR register offset. > > CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks) > CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK > CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK > >

Re: [PATCH 1/2] clk: imx7d: correct enet clock CCGR register offset

On 17.05.2018 10:40, Anson Huang wrote: > Correct enet clock CCGR register offset. > > CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks) > CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK > CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK > >

Re: [PATCH] ARM: dts: vf610-zii-dev: enable vf610 builtin temp sensor

use > that ADC. That seems sensible. Acked-by: Stefan Agner <ste...@agner.ch> > > Signed-off-by: Nikita Yushchenko <nikita.yo...@cogentembedded.com> > --- > arch/arm/boot/dts/vf610-zii-dev.dtsi | 4 > arch/arm/boot/dts/vfxxx.dtsi | 2 +- > 2 files c

Re: [PATCH] ARM: dts: vf610-zii-dev: enable vf610 builtin temp sensor

use > that ADC. That seems sensible. Acked-by: Stefan Agner > > Signed-off-by: Nikita Yushchenko > --- > arch/arm/boot/dts/vf610-zii-dev.dtsi | 4 > arch/arm/boot/dts/vfxxx.dtsi | 2 +- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git

Re: [PATCH v4 3/3] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

On 15.05.2018 16:41, Krzysztof Kozlowski wrote: > Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM > (with 1024 MB NAND) flavors. Both of them will use the same DTSI > expecting the bootloader to do the fixup of /memory node. However in > case it does not happen, let's stay on

Re: [PATCH v4 3/3] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

On 15.05.2018 16:41, Krzysztof Kozlowski wrote: > Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM > (with 1024 MB NAND) flavors. Both of them will use the same DTSI > expecting the bootloader to do the fixup of /memory node. However in > case it does not happen, let's stay on

Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

On 09.05.2018 03:26, Jacky Bai wrote: >> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change >> >> Quoting Stefan Agner (2018-05-08 06:20:03) >> > On 08.05.2018 09:32, Jacky Bai wrote: >> > > >> > > I have tried two 6ULL board,

Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

On 09.05.2018 03:26, Jacky Bai wrote: >> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change >> >> Quoting Stefan Agner (2018-05-08 06:20:03) >> > On 08.05.2018 09:32, Jacky Bai wrote: >> > > >> > > I have tried two 6ULL board,

[PATCH v3] bus: arm-cci: remove unnecessary unreachable()

;li...@arm.linux.org.uk> Signed-off-by: Stefan Agner <ste...@agner.ch> Acked-by: Nicolas Pitre <n...@linaro.org> Reviewed-by: Robin Murphy <robin.mur...@arm.com> --- Changes in v3: - Fix subject and enhance commit message Changes in v2: - Don't add assembly ASM_UNREACHABLE, just drop unreachable()

[PATCH v3] bus: arm-cci: remove unnecessary unreachable()

return in asm. There is no need for the unreachable() call. GCC 7.2 generates identical object files before and after, other than (for obvious reasons) the line numbers generated by WANT_WARN_ON_SLOWPATH for all the WARN()s appearing later in the file. Suggested-by: Russell King Signed-off-by: Stefan

Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

_PLL3_USB_OTG. This only seems to appear since >> >> commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy >> >> divider and busy mux"), probably because the clock is now forced to >> >> be on. >> >> >> >> Fixes: 6f9

Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

_PLL3_USB_OTG. This only seems to appear since >> >> commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy >> >> divider and busy mux"), probably because the clock is now forced to >> >> be on. >> >> >> >>

Re: [RESEND PATCH v2] bus: arm-cci: use asm unreachable

On 08.05.2018 14:19, Robin Murphy wrote: > On 08/05/18 12:32, Stefan Agner wrote: >> Mixing asm and C code is not recommended in a naked function by >> gcc and leads to an error when using clang: >>drivers/bus/arm-cci.c:2107:2: error: non-ASM statement in naked >>

Re: [RESEND PATCH v2] bus: arm-cci: use asm unreachable

On 08.05.2018 14:19, Robin Murphy wrote: > On 08/05/18 12:32, Stefan Agner wrote: >> Mixing asm and C code is not recommended in a naked function by >> gcc and leads to an error when using clang: >>drivers/bus/arm-cci.c:2107:2: error: non-ASM statement in naked >>

[RESEND PATCH v2] bus: arm-cci: use asm unreachable

return in asm. There is no need for the unreachable() call. Suggested-by: Russell King <li...@arm.linux.org.uk> Signed-off-by: Stefan Agner <ste...@agner.ch> Acked-by: Nicolas Pitre <n...@linaro.org> --- drivers/bus/arm-cci.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drive

[RESEND PATCH v2] bus: arm-cci: use asm unreachable

return in asm. There is no need for the unreachable() call. Suggested-by: Russell King Signed-off-by: Stefan Agner Acked-by: Nicolas Pitre --- drivers/bus/arm-cci.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 443e4c3fd357..b8184a903583

Re: [PATCH 04/13] drm/kms/mode/fsl-dcu: using helper func drm_display_mode_to_videomode for calculating timing parameters

On 03.05.2018 10:44, Satendra Singh Thakur wrote: > To avoid duplicate logic for the same How about: Use drm_display_mode_to_videomode to avoid duplicate logic. > > Signed-off-by: Satendra Singh Thakur > Cc: Madhur Verma > Cc: Hemanshu

Re: [PATCH 04/13] drm/kms/mode/fsl-dcu: using helper func drm_display_mode_to_videomode for calculating timing parameters

On 03.05.2018 10:44, Satendra Singh Thakur wrote: > To avoid duplicate logic for the same How about: Use drm_display_mode_to_videomode to avoid duplicate logic. > > Signed-off-by: Satendra Singh Thakur > Cc: Madhur Verma > Cc: Hemanshu Srivastava > --- >

Re: [PATCH v2 0/6] ARM: clang support

On 25.03.2018 20:09, Stefan Agner wrote: > This patchset fixes some remaining issues when building the ARM > architecture using LLVM/clang. The patchset requires the following > kbuild change: > https://lkml.org/lkml/2018/3/19/1756 > > With that patch and this patchset

Re: [PATCH v2 0/6] ARM: clang support

On 25.03.2018 20:09, Stefan Agner wrote: > This patchset fixes some remaining issues when building the ARM > architecture using LLVM/clang. The patchset requires the following > kbuild change: > https://lkml.org/lkml/2018/3/19/1756 > > With that patch and this patchset

Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

mux"), probably because the clock is >> now forced to be on. >> >> Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and >> busy mux") >> Signed-off-by: Stefan Agner <ste...@agner.ch> >> --- >> This addresses a regression s

Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

mux"), probably because the clock is >> now forced to be on. >> >> Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and >> busy mux") >> Signed-off-by: Stefan Agner >> --- >> This addresses a regression ssen on v4.17-rc1 wher

Re: [PATCH v2] ARM: dts: tegra: Add support for 256 MB Colibri-T20 (plus such board on Iris)

On 03.05.2018 17:08, Krzysztof Kozlowski wrote: > Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM > (with 1024 MB NAND) flavors. Add support for the 256 MB version on Iris > evaluation board. To we really need to specify memory size these days? I think all common boot loaders

Re: [PATCH v2] ARM: dts: tegra: Add support for 256 MB Colibri-T20 (plus such board on Iris)

On 03.05.2018 17:08, Krzysztof Kozlowski wrote: > Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM > (with 1024 MB NAND) flavors. Add support for the 256 MB version on Iris > evaluation board. To we really need to specify memory size these days? I think all common boot loaders

[PATCH v2] serial: imx: fix cached UCR2 read on software reset

baudrate because the baud rate register got restored before reset completed in imx_flush_buffer. Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR") Signed-off-by: Stefan Agner <ste...@agner.ch> Reviewed-by: Fabio Estevam <fabio.este...@nxp.co

[PATCH v2] serial: imx: fix cached UCR2 read on software reset

baudrate because the baud rate register got restored before reset completed in imx_flush_buffer. Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR") Signed-off-by: Stefan Agner Reviewed-by: Fabio Estevam Reviewed-by: Uwe Kleine-König --- Hi Greg, Since

Re: [PATCH] treewide: use PHYS_ADDR_MAX to avoid type casting ULLONG_MAX

On 20.04.2018 13:15, Matthew Wilcox wrote: > On Thu, Apr 19, 2018 at 11:42:04PM +0200, Stefan Agner wrote: >> With PHYS_ADDR_MAX there is now a type safe variant for all >> bits set. Make use of it. > > There is? I don't see it in linux-next. The patch "mm/memblock: in

Re: [PATCH] treewide: use PHYS_ADDR_MAX to avoid type casting ULLONG_MAX

On 20.04.2018 13:15, Matthew Wilcox wrote: > On Thu, Apr 19, 2018 at 11:42:04PM +0200, Stefan Agner wrote: >> With PHYS_ADDR_MAX there is now a type safe variant for all >> bits set. Make use of it. > > There is? I don't see it in linux-next. The patch "mm/memblock: in

Re: [PATCH] serial: imx: fix cached UCR2 read on software reset

On 20.04.2018 08:03, Uwe Kleine-König wrote: > Hello Stefan, > > On Thu, Apr 19, 2018 at 11:37:23PM +0200, Stefan Agner wrote: >> On 16.04.2018 17:35, Stefan Agner wrote: >> > To reset the UART the SRST needs be cleared (low active). According >> > to the documen

Re: [PATCH] serial: imx: fix cached UCR2 read on software reset

On 20.04.2018 08:03, Uwe Kleine-König wrote: > Hello Stefan, > > On Thu, Apr 19, 2018 at 11:37:23PM +0200, Stefan Agner wrote: >> On 16.04.2018 17:35, Stefan Agner wrote: >> > To reset the UART the SRST needs be cleared (low active). According >> > to the documen

[PATCH] treewide: use PHYS_ADDR_MAX to avoid type casting ULLONG_MAX

With PHYS_ADDR_MAX there is now a type safe variant for all bits set. Make use of it. Patch created using a sematic patch as follows: // @@ typedef phys_addr_t; @@ -(phys_addr_t)ULLONG_MAX +PHYS_ADDR_MAX // Signed-off-by: Stefan Agner <ste...@agner.ch> --- arch/arm64/mm/

[PATCH] treewide: use PHYS_ADDR_MAX to avoid type casting ULLONG_MAX

With PHYS_ADDR_MAX there is now a type safe variant for all bits set. Make use of it. Patch created using a sematic patch as follows: // @@ typedef phys_addr_t; @@ -(phys_addr_t)ULLONG_MAX +PHYS_ADDR_MAX // Signed-off-by: Stefan Agner --- arch/arm64/mm/init.c | 6 +++--- arch

Re: [PATCH] serial: imx: fix cached UCR2 read on software reset

Hi Uwe, On 16.04.2018 17:35, Stefan Agner wrote: > To reset the UART the SRST needs be cleared (low active). According > to the documentation the bit will remain active for 4 module clocks > until it is cleared (set to 1). > > Hence the real register need to be read in case the

Re: [PATCH] serial: imx: fix cached UCR2 read on software reset

Hi Uwe, On 16.04.2018 17:35, Stefan Agner wrote: > To reset the UART the SRST needs be cleared (low active). According > to the documentation the bit will remain active for 4 module clocks > until it is cleared (set to 1). > > Hence the real register need to be read in case the

[PATCH v3] serial: imx: warn user when using unsupported configuration

the SER_RS485_RX_DURING_TX flag). Signed-off-by: Stefan Agner <ste...@agner.ch> --- drivers/tty/serial/imx.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 91f3a1a5cb7f..65d7a2bfb6d2 100644 --- a/drivers/tty/serial/imx.c

[PATCH v3] serial: imx: warn user when using unsupported configuration

the SER_RS485_RX_DURING_TX flag). Signed-off-by: Stefan Agner --- drivers/tty/serial/imx.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 91f3a1a5cb7f..65d7a2bfb6d2 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial

Re: [PATCH v2] serial: imx: warn user when using unsupported configuration

On 18.04.2018 16:53, Uwe Kleine-König wrote: > On Wed, Apr 18, 2018 at 04:06:38PM +0200, Stefan Agner wrote: >> When using half-duplex mode (which disables receiver during txing) >> the RTS signal cannot be driven low during transmission. This seems >> to be a limitatio

Re: [PATCH v2] serial: imx: warn user when using unsupported configuration

On 18.04.2018 16:53, Uwe Kleine-König wrote: > On Wed, Apr 18, 2018 at 04:06:38PM +0200, Stefan Agner wrote: >> When using half-duplex mode (which disables receiver during txing) >> the RTS signal cannot be driven low during transmission. This seems >> to be a limitatio

[PATCH v2] serial: imx: warn user when using unsupported configuration

-by: Stefan Agner <ste...@agner.ch> --- Changes since v1: - Consistently check for sport->have_rtscts && !(rs485conf->flags & SER_RS485_RTS_ON_SEND) - Don't break printed message drivers/tty/serial/imx.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/dr

[PATCH v2] serial: imx: warn user when using unsupported configuration

-by: Stefan Agner --- Changes since v1: - Consistently check for sport->have_rtscts && !(rs485conf->flags & SER_RS485_RTS_ON_SEND) - Don't break printed message drivers/tty/serial/imx.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/tty/serial/imx.c b/

[PATCH] serial: imx: warn user when using unsupported configuration

-by: Stefan Agner <ste...@agner.ch> --- drivers/tty/serial/imx.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 91f3a1a5cb7f..1ba7e98ddc76 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -1833,6 +1

[PATCH] serial: imx: warn user when using unsupported configuration

-by: Stefan Agner --- drivers/tty/serial/imx.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 91f3a1a5cb7f..1ba7e98ddc76 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -1833,6 +1833,10 @@ static int

[PATCH] clk: imx6ul: fix periph clk2 clock mux selection

According to the data sheet the 3rd choice is the bypass clock of pll2. This should not have any effect in practice as this selection is not used currently. Signed-off-by: Stefan Agner <ste...@agner.ch> --- drivers/clk/imx/clk-imx6ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH] clk: imx6ul: fix periph clk2 clock mux selection

According to the data sheet the 3rd choice is the bypass clock of pll2. This should not have any effect in practice as this selection is not used currently. Signed-off-by: Stefan Agner --- drivers/clk/imx/clk-imx6ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers

[PATCH] clk: imx6ull: use OSC clock during AXI rate change

55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux") Signed-off-by: Stefan Agner <ste...@agner.ch> --- This addresses a regression ssen on v4.17-rc1 where the kernel boots during clock initialization, see also: https://patchwork.kernel.org/patch/10295927/ dr

[PATCH] clk: imx6ull: use OSC clock during AXI rate change

55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux") Signed-off-by: Stefan Agner --- This addresses a regression ssen on v4.17-rc1 where the kernel boots during clock initialization, see also: https://patchwork.kernel.org/patch/10295927/ drivers/clk/imx/clk-imx

Re: [PATCH v2 3/6] ARM: trusted_foundations: do not use naked function

On 16.04.2018 18:08, Stephen Warren wrote: > On 04/16/2018 09:56 AM, Stefan Agner wrote: >> On 27.03.2018 14:16, Dmitry Osipenko wrote: >>> On 27.03.2018 14:54, Robin Murphy wrote: >>>> On 26/03/18 22:20, Dmitry Osipenko wrote: >>>>> On 25.03.2018 21

Re: [PATCH v2 3/6] ARM: trusted_foundations: do not use naked function

On 16.04.2018 18:08, Stephen Warren wrote: > On 04/16/2018 09:56 AM, Stefan Agner wrote: >> On 27.03.2018 14:16, Dmitry Osipenko wrote: >>> On 27.03.2018 14:54, Robin Murphy wrote: >>>> On 26/03/18 22:20, Dmitry Osipenko wrote: >>>>> On 25.03.2018 21

Re: [PATCH v2 1/6] bus: arm-cci: use asm unreachable

On 25.03.2018 20:09, Stefan Agner wrote: > Mixing asm and C code is not recommended in a naked function by > gcc and leads to an error when using clang: > drivers/bus/arm-cci.c:2107:2: error: non-ASM statement in naked > function is not supported > unreachable(); >

Re: [PATCH v2 1/6] bus: arm-cci: use asm unreachable

On 25.03.2018 20:09, Stefan Agner wrote: > Mixing asm and C code is not recommended in a naked function by > gcc and leads to an error when using clang: > drivers/bus/arm-cci.c:2107:2: error: non-ASM statement in naked > function is not supported > unreachable(); >

Re: [PATCH v2 3/6] ARM: trusted_foundations: do not use naked function

On 27.03.2018 14:16, Dmitry Osipenko wrote: > On 27.03.2018 14:54, Robin Murphy wrote: >> On 26/03/18 22:20, Dmitry Osipenko wrote: >>> On 25.03.2018 21:09, Stefan Agner wrote: >>>> As documented in GCC naked functions should only use Basic asm >>>> syntax

Re: [PATCH v2 3/6] ARM: trusted_foundations: do not use naked function

On 27.03.2018 14:16, Dmitry Osipenko wrote: > On 27.03.2018 14:54, Robin Murphy wrote: >> On 26/03/18 22:20, Dmitry Osipenko wrote: >>> On 25.03.2018 21:09, Stefan Agner wrote: >>>> As documented in GCC naked functions should only use Basic asm >>>> syntax

[PATCH] serial: imx: fix cached UCR2 read on software reset

baudrate because the baud rate register got restored before reset completed in imx_flush_buffer. Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR") Signed-off-by: Stefan Agner <ste...@agner.ch> --- drivers/tty/serial/imx.c | 2 +- 1 file changed, 1

[PATCH] serial: imx: fix cached UCR2 read on software reset

baudrate because the baud rate register got restored before reset completed in imx_flush_buffer. Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR") Signed-off-by: Stefan Agner --- drivers/tty/serial/imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletio

Re: [PATCH v2 1/2] mtd: rawnand: gpmi: add support for specific ECC strength

Han, On 15.03.2018 16:39, Stefan Agner wrote: > On March 15, 2018 4:36:20 PM GMT+01:00, Boris Brezillon > <boris.brezil...@bootlin.com> wrote: >>Hi, >> >>On Sun, 4 Mar 2018 21:06:01 +0100 >>Stefan Agner <ste...@agner.ch> wrote: >> >>> Add

Re: [PATCH v2 1/2] mtd: rawnand: gpmi: add support for specific ECC strength

Han, On 15.03.2018 16:39, Stefan Agner wrote: > On March 15, 2018 4:36:20 PM GMT+01:00, Boris Brezillon > wrote: >>Hi, >> >>On Sun, 4 Mar 2018 21:06:01 +0100 >>Stefan Agner wrote: >> >>> Add support for specified ECC strength/size using device t

[PATCH] mm/memblock: introduce PHYS_ADDR_MAX

Suggested-by: Linus Torvalds <torva...@linux-foundation.org> Signed-off-by: Stefan Agner <ste...@agner.ch> --- Hi, There are about a dozen other instances of (phys_addr_t)ULLONG_MAX accross the tree. Should I address them too? -- Stefan include/linux/kernel.h | 1 + mm/me

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