On 14.02.2018 20:05, Boris Brezillon wrote:
> On Wed, 14 Feb 2018 16:28:36 +
> Han Xu wrote:
>
>> On 02/06/2018 11:40 AM, Stefan Agner wrote:
>> > Add support for specified ECC strength/size using device tree
>> > properties nand-ecc-strength/nand-ec
Add Dong Aisheng, Fabio Estevam, Shawn Guo and myself as maintainer
and the Pengutronix kernel team as reviewer.
Signed-off-by: Stefan Agner <ste...@agner.ch>
Reviewed-by: Fabio Estevam <feste...@gmail.com>
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
Add Dong Aisheng, Fabio Estevam, Shawn Guo and myself as maintainer
and the Pengutronix kernel team as reviewer.
Signed-off-by: Stefan Agner
Reviewed-by: Fabio Estevam
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 82ad0eabce4f
On 12.02.2018 11:18, Rafael J. Wysocki wrote:
> On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner <ste...@agner.ch> wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>>
On 12.02.2018 11:18, Rafael J. Wysocki wrote:
> On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note: For higher operat
On 12.02.2018 12:34, Lucas Stach wrote:
> Am Montag, den 12.02.2018, 13:22 +0200 schrieb Baruch Siach:
>> Hi Lucas,
>>
>> On Mon, Feb 12, 2018 at 11:48:22AM +0100, Lucas Stach wrote:
>> > Am Samstag, den 10.02.2018, 16:32 +0100 schrieb Stefan Agner:
>> > &
On 12.02.2018 12:34, Lucas Stach wrote:
> Am Montag, den 12.02.2018, 13:22 +0200 schrieb Baruch Siach:
>> Hi Lucas,
>>
>> On Mon, Feb 12, 2018 at 11:48:22AM +0100, Lucas Stach wrote:
>> > Am Samstag, den 10.02.2018, 16:32 +0100 schrieb Stefan Agner:
>> > &
On 11.02.2018 02:42, Anson Huang wrote:
> Anson Huang
> Best Regards!
>
>
>> -Original Message-
>> From: Fabio Estevam [mailto:feste...@gmail.com]
>> Sent: Sunday, February 11, 2018 12:26 AM
>> To: Stefan Agner <ste...@agner.ch>;
On 11.02.2018 02:42, Anson Huang wrote:
> Anson Huang
> Best Regards!
>
>
>> -Original Message-
>> From: Fabio Estevam [mailto:feste...@gmail.com]
>> Sent: Sunday, February 11, 2018 12:26 AM
>> To: Stefan Agner ; Anson Huang
>> Cc: r
On 07.01.2018 14:49, Stefan Agner wrote:
> If power domain information are missing in the device tree, no
> power domains get initialized. However, imx_gpc_remove tries to
> remove power domains always in the old DT binding case. Only
> remove power domains when imx_gpc_probe init
On 07.01.2018 14:49, Stefan Agner wrote:
> If power domain information are missing in the device tree, no
> power domains get initialized. However, imx_gpc_remove tries to
> remove power domains always in the old DT binding case. Only
> remove power domains when imx_gpc_probe init
Add Dong Aisheng, Fabio Estevam, Shawn Guo and myself as maintainer
and Sascha as reviewer.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 82ad0eabce4f..fb672dfc519d
Add Dong Aisheng, Fabio Estevam, Shawn Guo and myself as maintainer
and Sascha as reviewer.
Signed-off-by: Stefan Agner
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 82ad0eabce4f..fb672dfc519d 100644
--- a/MAINTAINERS
+++ b
to work fine, thanks for fixing this!
For the complete patchset:
Reviewed-by: Stefan Agner <ste...@agner.ch>
--
Stefan
> ---
> drivers/mtd/nand/vf610_nfc.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers
anks for fixing this!
For the complete patchset:
Reviewed-by: Stefan Agner
--
Stefan
> ---
> drivers/mtd/nand/vf610_nfc.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
> index 9cc5992e88c8..64fed3
On 09.02.2018 12:52, Rafael J. Wysocki wrote:
> On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note:
On 09.02.2018 12:52, Rafael J. Wysocki wrote:
> On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note:
Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
.../devicetree/bindings/mtd/gpmi-nand.txt | 5
drivers/mtd/nand/gpmi-nand/gpmi-nand.c
Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.
Signed-off-by: Stefan Agner
---
.../devicetree/bindings/mtd/gpmi-nand.txt | 5
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 29 ++
2 files
.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
Documentation/devicetree/bindings/mtd/gpmi-nand.txt | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
index b289ef
.
Signed-off-by: Stefan Agner
---
Documentation/devicetree/bindings/mtd/gpmi-nand.txt | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
index b289ef3c1b7e..eb2d9919d063
.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
This depends on the following patchsets work:
- https://lkml.org/lkml/2018/1/6/129 (applied)
- https://lkml.org/lkml/2018/1/10/998 (applied)
- https://www.spinics.net/lists/arm-kernel/msg632671.html (pending, required)
- https://lkml.org/lkm
.
Signed-off-by: Stefan Agner
---
This depends on the following patchsets work:
- https://lkml.org/lkml/2018/1/6/129 (applied)
- https://lkml.org/lkml/2018/1/10/998 (applied)
- https://www.spinics.net/lists/arm-kernel/msg632671.html (pending, required)
- https://lkml.org/lkml/2018/1/18/850 (only
ECC scheme."
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 50f8d4a1b9
ECC scheme."
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 50f8d4a1b983..7b8e8c629
.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
This depends on the following patchsets work:
- https://lkml.org/lkml/2018/1/6/129 (applied)
- https://lkml.org/lkml/2018/1/10/998 (pending, required)
- https://lkml.org/lkml/2018/1/18/850 (only for highest CPU frequency)
--
Stefan
arch/ar
.
Signed-off-by: Stefan Agner
---
This depends on the following patchsets work:
- https://lkml.org/lkml/2018/1/6/129 (applied)
- https://lkml.org/lkml/2018/1/10/998 (pending, required)
- https://lkml.org/lkml/2018/1/18/850 (only for highest CPU frequency)
--
Stefan
arch/arm/boot/dts/Makefile
an external DC regulator which needs
adjustment. The regulator adjustment is not covered with this
change.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
drivers/cpufreq/imx6q-cpufreq.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufr
an external DC regulator which needs
adjustment. The regulator adjustment is not covered with this
change.
Signed-off-by: Stefan Agner
---
drivers/cpufreq/imx6q-cpufreq.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq
already set it back high, which is not long enouth.
Make sure reset is asserted for at least 100us by inserting a
delay after initializing the reset pin during probe.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
drivers/usb/misc/usb3503.c | 2 ++
1 file changed, 2 insertions(+)
diff
already set it back high, which is not long enouth.
Make sure reset is asserted for at least 100us by inserting a
delay after initializing the reset pin during probe.
Signed-off-by: Stefan Agner
---
drivers/usb/misc/usb3503.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/misc
Add per-core ARM architected timer. Unfortunately bootloaders (U-Boot)
currently do not make the necessary initialization. Also specifing the
clock manually using the clock-frequency property seems not to help.
Therefor leave the timer disabled by default for now.
Signed-off-by: Stefan Agner <
Add per-core ARM architected timer. Unfortunately bootloaders (U-Boot)
currently do not make the necessary initialization. Also specifing the
clock manually using the clock-frequency property seems not to help.
Therefor leave the timer disabled by default for now.
Signed-off-by: Stefan Agner
From: Bai Ping <ping@nxp.com>
On i.MX 6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
pins are available through IOMUXC_SNVS. Add additional pinfunc defines.
Signed-off-by: Bai Ping <ping@nxp.com>
Signed-off-by: Stefan Agner <ste...@agner.ch>
Reviewed-
From: Bai Ping
On i.MX 6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
pins are available through IOMUXC_SNVS. Add additional pinfunc defines.
Signed-off-by: Bai Ping
Signed-off-by: Stefan Agner
Reviewed-by: Rob Herring
Acked-by: Dong Aisheng
---
arch/arm/boot/dts/imx6ull
From: Fugang Duan <fugang.d...@nxp.com>
Add previously missing daisy chain configurations and several
additional pinmux options.
Synchronized with NXP Linux 4.9.11_1.0.0 release.
Signed-off-by: Fugang Duan <fugang.d...@nxp.com>
Signed-off-by: Stefan Agner <ste...@agner.ch>
The Cortex-A7 and its GIC support virtualization extensions. To
make use of them the CPU private interrupt needs to be specified.
Signed-off-by: Stefan Agner <ste...@agner.ch>
Reviewed-by: Rob Herring <r...@kernel.org>
---
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
1 file changed,
The Cortex-A7 and its GIC support virtualization extensions. To
make use of them the CPU private interrupt needs to be specified.
Signed-off-by: Stefan Agner
Reviewed-by: Rob Herring
---
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts
From: Fugang Duan
Add previously missing daisy chain configurations and several
additional pinmux options.
Synchronized with NXP Linux 4.9.11_1.0.0 release.
Signed-off-by: Fugang Duan
Signed-off-by: Stefan Agner
Reviewed-by: Rob Herring
---
arch/arm/boot/dts/imx6ul-pinfunc.h | 169
The i.MX 6ULL features another IOMUX Controller called IOMUXC
SNVS which allows to control BOOT_MODE and TAMPER pins. Add the
controller to the i.MX 6ULL specific imx6ull.dtsi device tree.
Signed-off-by: Stefan Agner <ste...@agner.ch>
Reviewed-by: Rob Herring <r...@kernel.org>
Ac
.
Note: The default timer on i.MX6SX is the i.MX GPT timer which is
not disabled during CPU idle. However, the timer is not affected
by the CPUIDLE_FLAG_TIMER_STOP flag. The flag only affects CPU
local timers.
Cc: Anson Huang <anson.hu...@nxp.com>
Signed-off-by: Stefan Agner <ste...@agner.ch&
The i.MX 6ULL features another IOMUX Controller called IOMUXC
SNVS which allows to control BOOT_MODE and TAMPER pins. Add the
controller to the i.MX 6ULL specific imx6ull.dtsi device tree.
Signed-off-by: Stefan Agner
Reviewed-by: Rob Herring
Acked-by: Dong Aisheng
---
arch/arm/boot/dts
.
Note: The default timer on i.MX6SX is the i.MX GPT timer which is
not disabled during CPU idle. However, the timer is not affected
by the CPUIDLE_FLAG_TIMER_STOP flag. The flag only affects CPU
local timers.
Cc: Anson Huang
Signed-off-by: Stefan Agner
Reviewed-by: Lucas Stach
---
arch/arm/mach
In i.MX 6ULL UART8 is part of the AIPS-3 memory map instead of
AIPS-1. Clocks and interrupts remain the same.
Signed-off-by: Stefan Agner <ste...@agner.ch>
Reviewed-by: Rob Herring <r...@kernel.org>
Acked-by: Dong Aisheng <aisheng.d...@nxp.com>
---
arch/arm/boot/dts
In i.MX 6ULL UART8 is part of the AIPS-3 memory map instead of
AIPS-1. Clocks and interrupts remain the same.
Signed-off-by: Stefan Agner
Reviewed-by: Rob Herring
Acked-by: Dong Aisheng
---
arch/arm/boot/dts/imx6ull.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch
sysfs: cannot create duplicate filename
'/devices/soc0/soc/200.aips-bus/20dc000.gpc/imx-pgc-power-domain.0'
>
> The problem can be reproduced by artificially enabling the error path
> of platform_device_add() call (around line 452).
>
> Cc: Shawn Guo <shawn...@kernel.o
sysfs: cannot create duplicate filename
'/devices/soc0/soc/200.aips-bus/20dc000.gpc/imx-pgc-power-domain.0'
>
> The problem can be reproduced by artificially enabling the error path
> of platform_device_add() call (around line 452).
>
> Cc: Shawn Guo
> Cc: Stefan Agner
On 2018-01-09 15:04, Lucas Stach wrote:
> Am Dienstag, den 09.01.2018, 14:37 +0100 schrieb Stefan Agner:
>> On 2018-01-09 11:13, Lucas Stach wrote:
>> > Am Dienstag, den 09.01.2018, 09:25 + schrieb Anson Huang:
>> > >
>> > > Best Regards!
>> >
On 2018-01-09 15:04, Lucas Stach wrote:
> Am Dienstag, den 09.01.2018, 14:37 +0100 schrieb Stefan Agner:
>> On 2018-01-09 11:13, Lucas Stach wrote:
>> > Am Dienstag, den 09.01.2018, 09:25 + schrieb Anson Huang:
>> > >
>> > > Best Regards!
>> >
On 2018-01-09 11:13, Lucas Stach wrote:
> Am Dienstag, den 09.01.2018, 09:25 + schrieb Anson Huang:
>>
>> Best Regards!
>> Anson Huang
>>
>>
>> > -Original Message-
>> > From: Dong Aisheng [mailto:donga...@gmail.com]
>> > Sen
On 2018-01-09 11:13, Lucas Stach wrote:
> Am Dienstag, den 09.01.2018, 09:25 + schrieb Anson Huang:
>>
>> Best Regards!
>> Anson Huang
>>
>>
>> > -Original Message-
>> > From: Dong Aisheng [mailto:donga...@gmail.com]
>> > Se
On 2018-01-09 10:22, Dong Aisheng wrote:
> On Tue, Jan 02, 2018 at 05:42:17PM +0100, Stefan Agner wrote:
>> When the CPU is in ARM power off state the ARM architected
>> timers are stopped. The flag is already present in the higher
>> power WAIT mode.
>>
>> This al
On 2018-01-09 10:22, Dong Aisheng wrote:
> On Tue, Jan 02, 2018 at 05:42:17PM +0100, Stefan Agner wrote:
>> When the CPU is in ARM power off state the ARM architected
>> timers are stopped. The flag is already present in the higher
>> power WAIT mode.
>>
>> This al
On 2018-01-09 10:34, Dong Aisheng wrote:
> Hi Stefan,
>
> On Tue, Jan 02, 2018 at 05:42:21PM +0100, Stefan Agner wrote:
>> Add per-core ARM architected timer. Unfortunately bootloaders (U-Boot)
>> currently do not make the necessary initialization. Also specifing the
&g
On 2018-01-09 10:34, Dong Aisheng wrote:
> Hi Stefan,
>
> On Tue, Jan 02, 2018 at 05:42:21PM +0100, Stefan Agner wrote:
>> Add per-core ARM architected timer. Unfortunately bootloaders (U-Boot)
>> currently do not make the necessary initialization. Also specifing the
&g
On 2018-01-08 11:51, Lucas Stach wrote:
> Am Montag, den 08.01.2018, 18:28 +0800 schrieb Dong Aisheng:
>> On Sun, Jan 07, 2018 at 02:49:05PM +0100, Stefan Agner wrote:
>> > If power domain information are missing in the device tree, no
>> > power domains get initializ
On 2018-01-08 11:51, Lucas Stach wrote:
> Am Montag, den 08.01.2018, 18:28 +0800 schrieb Dong Aisheng:
>> On Sun, Jan 07, 2018 at 02:49:05PM +0100, Stefan Agner wrote:
>> > If power domain information are missing in the device tree, no
>> > power domains get initializ
On 2018-01-08 17:48, Gary Bisson wrote:
> Hi Stefan,
>
> On Sat, Jan 06, 2018 at 03:25:49PM +0100, Stefan Agner wrote:
>> For some SoCs the struct imx_pinctrl_soc_info is passed through
>> of_device_id.data which is const. Most variables are already const
>> or oth
On 2018-01-08 17:48, Gary Bisson wrote:
> Hi Stefan,
>
> On Sat, Jan 06, 2018 at 03:25:49PM +0100, Stefan Agner wrote:
>> For some SoCs the struct imx_pinctrl_soc_info is passed through
>> of_device_id.data which is const. Most variables are already const
>> or oth
nable the clocks when we start to
transfer a message")
Cc: Philippe De Muyter <p...@macqel.be>
Cc: Huang Shijie <shijie.hu...@arm.com>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
drivers/spi/spi-imx.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(
nable the clocks when we start to
transfer a message")
Cc: Philippe De Muyter
Cc: Huang Shijie
Signed-off-by: Stefan Agner
---
drivers/spi/spi-imx.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 79
move PGC handling to a new GPC driver")
Cc: Lucas Stach <l.st...@pengutronix.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
drivers/soc/imx/gpc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gp
move PGC handling to a new GPC driver")
Cc: Lucas Stach
Signed-off-by: Stefan Agner
---
drivers/soc/imx/gpc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c
index 53f7275d6cbd..62bb724726d9 100644
--- a/drivers/soc
On 2018-01-05 17:49, Rob Herring wrote:
> On Tue, Jan 02, 2018 at 05:42:19PM +0100, Stefan Agner wrote:
>> From: Bai Ping <ping@nxp.com>
>>
>> On i.MX 6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
>> pins are available through IOMUXC_SNV
On 2018-01-05 17:49, Rob Herring wrote:
> On Tue, Jan 02, 2018 at 05:42:19PM +0100, Stefan Agner wrote:
>> From: Bai Ping
>>
>> On i.MX 6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
>> pins are available through IOMUXC_SNVS. Add additional pinfunc define
Now that imx_pinctrl_probe accepts const struct imx_pinctrl_soc_info
we can constify all declarations of struct imx_pinctrl_soc_info.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
drivers/pinctrl/freescale/pinctrl-imx25.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx35.c | 2 +-
d
("pinctrl: freescale: imx7d: make of_device_ids const")
Cc: Shawn Guo <shawn...@kernel.org>
Cc: Arvind Yadav <arvind.yadav...@gmail.com>
Cc: Dong Aisheng <aisheng.d...@nxp.com>
Cc: Gary Bisson <gary.bis...@boundarydevices.com>
Signed-off-by: Stefan Agner <ste...@agn
Using of_device_get_match_data in imx7d_pinctrl_probe simplifies
the function. Also get rid of the void pointer cast since
imx_pinctrl_probe now accepts const struct imx_pinctrl_soc_info.
Cc: Arvind Yadav <arvind.yadav...@gmail.com>
Signed-off-by: Stefan Agner <ste...@agner.ch>
Using of_device_get_match_data in imx7d_pinctrl_probe simplifies
the function. Also get rid of the void pointer cast since
imx_pinctrl_probe now accepts const struct imx_pinctrl_soc_info.
Cc: Arvind Yadav
Signed-off-by: Stefan Agner
---
drivers/pinctrl/freescale/pinctrl-imx7d.c | 10
Now that imx_pinctrl_probe accepts const struct imx_pinctrl_soc_info
we can constify all declarations of struct imx_pinctrl_soc_info.
Signed-off-by: Stefan Agner
---
drivers/pinctrl/freescale/pinctrl-imx25.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx35.c | 2 +-
drivers/pinctrl/freescale
("pinctrl: freescale: imx7d: make of_device_ids const")
Cc: Shawn Guo
Cc: Arvind Yadav
Cc: Dong Aisheng
Cc: Gary Bisson
Signed-off-by: Stefan Agner
---
drivers/pinctrl/freescale/pinctrl-imx.c | 79 ++---
drivers/pinctrl/freescale/pinctrl-imx.h | 11 ++-
From: Bai Ping <ping@nxp.com>
On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
are available in a separate IOMUXC_SNVS module. Add support for the
IOMUXC_SNVS module to the i.MX 6UL pinctrl driver.
Signed-off-by: Bai Ping <ping@nxp.com>
Signed-off-by: Stefa
The decode parameters are constant mark them const.
Cc: Dong Aisheng <aisheng.d...@nxp.com>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx.h | 2 +-
drivers/pinctrl/freescale/pinctrl-i
From: Bai Ping
On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
are available in a separate IOMUXC_SNVS module. Add support for the
IOMUXC_SNVS module to the i.MX 6UL pinctrl driver.
Signed-off-by: Bai Ping
Signed-off-by: Stefan Agner
Reviewed-by: Rob Herring
The decode parameters are constant mark them const.
Cc: Dong Aisheng
Signed-off-by: Stefan Agner
---
drivers/pinctrl/freescale/pinctrl-imx.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx.h | 2 +-
drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 2 +-
3 files changed, 3 insertions(+), 3
_device_id. It is also helpful for all other
SoCs since it decreases the .data section for all drivers by 1276
bytes.
Bai Ping (1):
pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL
Stefan Agner (4):
pinctrl: imx: use struct imx_pinctrl_soc_info as a const
pinctrl: imx7d
_device_id. It is also helpful for all other
SoCs since it decreases the .data section for all drivers by 1276
bytes.
Bai Ping (1):
pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL
Stefan Agner (4):
pinctrl: imx: use struct imx_pinctrl_soc_info as a const
pinctrl: imx7d
On 2018-01-06 12:14, Stefan Agner wrote:
> On 2018-01-03 09:09, Linus Walleij wrote:
>> On Tue, Jan 2, 2018 at 5:40 PM, Stefan Agner <ste...@agner.ch> wrote:
>>
>>> From: Bai Ping <ping@nxp.com>
>>>
>>> On i.MX 6ULL, the BOOT_MODEx an
On 2018-01-06 12:14, Stefan Agner wrote:
> On 2018-01-03 09:09, Linus Walleij wrote:
>> On Tue, Jan 2, 2018 at 5:40 PM, Stefan Agner wrote:
>>
>>> From: Bai Ping
>>>
>>> On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
>>>
On 2018-01-03 09:09, Linus Walleij wrote:
> On Tue, Jan 2, 2018 at 5:40 PM, Stefan Agner <ste...@agner.ch> wrote:
>
>> From: Bai Ping <ping@nxp.com>
>>
>> On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
>> are available in
On 2018-01-03 09:09, Linus Walleij wrote:
> On Tue, Jan 2, 2018 at 5:40 PM, Stefan Agner wrote:
>
>> From: Bai Ping
>>
>> On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
>> are available in a separate IOMUXC_SNVS module. Add support for the
>
On 2018-01-05 17:45, Rob Herring wrote:
> On Tue, Jan 02, 2018 at 05:42:18PM +0100, Stefan Agner wrote:
>> From: Fugang Duan <fugang.d...@nxp.com>
>>
>> Update i.MX 6UltraLite IOMUXC pin defines.
>
> That's obvious reading the diff. The commit message should te
On 2018-01-05 17:45, Rob Herring wrote:
> On Tue, Jan 02, 2018 at 05:42:18PM +0100, Stefan Agner wrote:
>> From: Fugang Duan
>>
>> Update i.MX 6UltraLite IOMUXC pin defines.
>
> That's obvious reading the diff. The commit message should tell me why.
> They we
From: Bai Ping <ping@nxp.com>
On i.MX 6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
pins are available through IOMUXC_SNVS. Add additional pinfunc defines.
Signed-off-by: Bai Ping <ping@nxp.com>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
arch/ar
From: Bai Ping
On i.MX 6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
pins are available through IOMUXC_SNVS. Add additional pinfunc defines.
Signed-off-by: Bai Ping
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6ull-pinfunc-snvs.h | 29
: Anson Huang <anson.hu...@nxp.com>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
arch/arm/mach-imx/cpuidle-imx6sx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c
b/arch/arm/mach-imx/cpuidle-imx6sx.c
index c5a5c3a70ab1..d0f14b761ff7 10064
: Anson Huang
Signed-off-by: Stefan Agner
---
arch/arm/mach-imx/cpuidle-imx6sx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c
b/arch/arm/mach-imx/cpuidle-imx6sx.c
index c5a5c3a70ab1..d0f14b761ff7 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sx.c
+++ b/arch
Add per-core ARM architected timer. Unfortunately bootloaders (U-Boot)
currently do not make the necessary initialization. Also specifing the
clock manually using the clock-frequency property seems not to help.
Therefor leave the timer disabled by default for now.
Signed-off-by: Stefan Agner <
Add per-core ARM architected timer. Unfortunately bootloaders (U-Boot)
currently do not make the necessary initialization. Also specifing the
clock manually using the clock-frequency property seems not to help.
Therefor leave the timer disabled by default for now.
Signed-off-by: Stefan Agner
From: Fugang Duan <fugang.d...@nxp.com>
Update i.MX 6UltraLite IOMUXC pin defines.
Signed-off-by: Fugang Duan <fugang.d...@nxp.com>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
arch/arm/boot/dts/imx6ul-pinfunc.h | 169 +
1 file chan
From: Fugang Duan
Update i.MX 6UltraLite IOMUXC pin defines.
Signed-off-by: Fugang Duan
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6ul-pinfunc.h | 169 +
1 file changed, 97 insertions(+), 72 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul
The Cortex-A7 and its GIC support virtualization extensions. To
make use of them the CPU private interrupt needs to be specified.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.
The Cortex-A7 and its GIC support virtualization extensions. To
make use of them the CPU private interrupt needs to be specified.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts
The i.MX 6ULL features another IOMUX Controller called IOMUXC
SNVS which allows to control BOOT_MODE and TAMPER pins. Add the
controller to the i.MX 6ULL specific imx6ull.dtsi device tree.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
arch/arm/boot/dts/imx6ull.dtsi | 17 ++
The i.MX 6ULL features another IOMUX Controller called IOMUXC
SNVS which allows to control BOOT_MODE and TAMPER pins. Add the
controller to the i.MX 6ULL specific imx6ull.dtsi device tree.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6ull.dtsi | 17 +
1 file changed, 17
In i.MX 6ULL UART8 is part of the AIPS-3 memory map instead of
AIPS-1. Clocks and interrupts remain the same.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
arch/arm/boot/dts/imx6ull.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi
In i.MX 6ULL UART8 is part of the AIPS-3 memory map instead of
AIPS-1. Clocks and interrupts remain the same.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6ull.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts
From: Bai Ping <ping@nxp.com>
On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
are available in a separate IOMUXC_SNVS module. Add support for the
IOMUXC_SNVS module to the i.MX 6UL pinctrl driver.
Signed-off-by: Bai Ping <ping@nxp.com>
Signed-off-by: Stefa
From: Bai Ping
On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
are available in a separate IOMUXC_SNVS module. Add support for the
IOMUXC_SNVS module to the i.MX 6UL pinctrl driver.
Signed-off-by: Bai Ping
Signed-off-by: Stefan Agner
---
.../bindings/pinctrl/fsl,imx6ul
Specify CPU supply using the "cpu-supply" property instead of
the invalid "arm-supply" property.
Signed-off-by: Stefan Agner <ste...@agner.ch>
Reviewed-by: Fabio Estevam <fabio.este...@nxp.com>
---
arch/arm/boot/dts/imx7-colibri.dtsi | 2 +-
1 file changed, 1 i
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