Quoting abhin...@codeaurora.org (2020-11-17 12:34:56)
> On 2020-11-17 09:26, Stephen Boyd wrote:
> > I don't know what this debug print is for but it is super chatty,
> > throwing 8 lines of debug prints in the logs every time we update a
> > plane. It looks like it has
I don't know what this debug print is for but it is super chatty,
throwing 8 lines of debug prints in the logs every time we update a
plane. It looks like it has no value. Let's nuke it so we can get
better logs.
Cc: Sean Paul
Cc: Abhinav Kumar
Signed-off-by: Stephen Boyd
---
drive
Quoting Kuogee Hsieh (2020-11-13 14:26:39)
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index 27e7e27b8b90..4e84f500b721 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -279,13 +279,25 @@ static voi
Quoting Dmitry Osipenko (2020-11-04 05:48:10)
> The 600MHz is a too high clock rate for some SoC versions for the video
> decoder hardware and this may cause stability issues. Use 300MHz for the
> video decoder by default, which is supported by all hardware versions.
>
> Fixes: ed1a2459e20c ("clk:
Quoting Claudiu Beznea (2020-11-06 01:46:23)
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c
> b/drivers/clk/at91/clk-sam9x60-pll.c
> index 78f458a7b2ef..6fe5d8530a0c 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -225,8 +225,51 @@ static int sa
Quoting Dmitry Baryshkov (2020-10-23 06:19:25)
> On SM8250 MMCX power domain is required to access MMDS_GDSC registers.
> This power domain is expressed as mmcx-supply regulator property. Use
> this regulator as MDSS_GDSC supply.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Applied to clk-next
Quoting Jerome Brunet (2020-10-21 09:38:45)
> This patchset adds memory managed variant of clk_notifier_register and
> a first usage of it the amlogic clock controller of the g12 SoC family.
>
> Jerome Brunet (2):
> clk: add devm variant of clk_notifier_register
I'm not sure if we want to docum
Quoting Jerome Brunet (2020-10-21 09:38:47)
> Until now, nothing was done to unregister the dvfs clock notifiers of the
> Amlogic g12 SoC family. This is not great but this driver was not really
> expected to be unloaded. With the ongoing effort to build everything as
> module for this platform, th
Quoting Jerome Brunet (2020-10-21 09:38:46)
> Add a memory managed variant of clk_notifier_register() to make life easier
> on clock consumers using notifiers
>
> Signed-off-by: Jerome Brunet
> ---
Applied to clk-next
Quoting Jerome Brunet (2020-10-21 09:21:46)
> clk_register() is deprecated. Using 'clk' member of struct clk_hw is
> discouraged. With this constraint, it is difficult for driver to
> register clocks using the clk_hw API and then use the clock with
> the consumer API
>
> This adds a simple helper,
Quoting Jerome Brunet (2020-10-21 09:21:45)
> In clk-devres.c, devm_clk_release() is used to call clk_put() memory
> managed clock. In clk.c the same name, in a different scope is used to call
> clk_unregister().
>
> As it stands, it is not really a problem but it does not readability,
> especiall
Quoting Jerome Brunet (2020-10-21 09:21:47)
> g12 clock controller used __clk_lookup() to get struct clk from a
> struct clk_hw. This type of hack is no longer required as CCF now provides
> the necessary functions to get this.
>
> Signed-off-by: Jerome Brunet
> ---
Applied to clk-next
Quoting Vinod Koul (2020-11-06 01:38:19)
> On 05-11-20, 16:18, Manivannan Sadhasivam wrote:
> > +#include "reset.h"
> > +
> > +enum {
> > + P_BI_TCXO,
> > + P_CORE_BI_PLL_TEST_SE,
>
> This is for test and we removed this for upstream, so can you do that as
> well (not parent will decrease
Quoting Lukas Bulwahn (2020-11-06 01:48:20)
> make clang-analyzer on x86_64 defconfig caught my attention with:
>
> drivers/clk/clk.c:423:19:
> warning: Value stored to 'parent' during its initialization is never read
> [clang-analyzer-deadcode.DeadStores]
> struct clk_core *parent
The following changes since commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec:
Linux 5.10-rc1 (2020-10-25 15:14:11 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
tags/clk-fixes-for-linus
for you to fetch changes up to c277ca155d2f
eported-by: Randy Dunlap
Reported-by: Geert Uytterhoeven
Cc: Nathan Chancellor
Cc: Stephen Rothwell
Cc: Taniya Das
Cc: "Rafael J. Wysocki"
Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for
SC7180")
Signed-off-by: Stephen Boyd
---
driver
Quoting Dan Carpenter (2020-11-13 02:14:19)
> Clean up the first driver if the second driver can't be registered.
>
> Fixes: 4ee9fe3e292b ("clk: qcom: lpass-sc7180: Disentangle the two clock
> devices")
> Signed-off-by: Dan Carpenter
> ---
Applied to clk-next
ut-set-variable]
> 548 | int dummy;
> | ^
>
> As the dummy var isn't needed, remove it.
>
> Reviewed-by: Stephen Boyd
> Signed-off-by: Mauro Carvalho Chehab
> ---
Applied. Thanks!
Quoting Mauro Carvalho Chehab (2020-09-28 23:22:13)
> While preparing to port the HiSilicon 6421v600 SPMI driver,
> I noticed some coding style issues at the SPMI core.
>
> Address them.
>
> Reviewed-by: Stephen Boyd
> Signed-off-by: Mauro Carvalho Chehab
> ---
Applied. Thanks!
Quoting Hsin-Hsiung Wang (2020-10-15 05:59:08)
> add spmi support for MT6873/8192.
Capitalize Add please.
>
> Signed-off-by: Hsin-Hsiung Wang
> ---
> drivers/spmi/Kconfig | 9 +
> drivers/spmi/Makefile| 1 +
> drivers/spmi/spmi-mtk-pmif.c | 474 +
SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spmi/spmi-mtk-pmif.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek SPMI Controller Device Tree Bindings
> +
> +maintainers:
Quoting Dmitry Osipenko (2020-11-04 08:56:31)
> Add "enable state" column to the clk summary. It's handy to know actual
> hardware state of all clocks for debugging purposes. In conjunction with
> clk_ignore_unused, this tells us what unused clocks are left on after
> bootloader without disabling t
"Fix" is a little strong. Maybe the subject should just be "Make
mtk_clk_register_mux() a static function".
Quoting Weiyi Lu (2020-11-10 18:33:56)
> mtk_clk_register_mux() should be a static function
>
> Fixes: a3ae549917f16 ("clk: mediatek: Add new clkmux register API")
Quoting Mike Looijmans (2020-11-05 01:06:54)
> On 05-11-2020 02:48, Stephen Boyd wrote:
> > Quoting Mike Looijmans (2020-11-03 06:17:41)
> >> Export an attribute program_nvm_bank that when read reports the current
> >> bank value. To program the chip's current stat
Quoting Manivannan Sadhasivam (2020-11-05 00:51:48)
> On Wed, Nov 04, 2020 at 06:23:37PM -0800, Stephen Boyd wrote:
> > > diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c
> > > new file mode 100644
> > > index ..75831c829202
&
Quoting Tian Tao (2020-11-10 23:57:56)
> linux/rational.h is included more than once, Remove the one that isn't
> necessary.
>
> Signed-off-by: Tian Tao
> ---
Reviewed-by: Stephen Boyd
Reading the EDID of this panel shows that these flags should be set. Set
them so that we match what is in the EDID.
Cc: Douglas Anderson
Cc: Bjorn Andersson
Fixes: b0c664cc80e8 ("panel: simple: Add BOE NV133FHM-N61")
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/panel/panel-si
Quoting Leo Yan (2020-02-19 21:26:52)
> This patch series adds support for thread stack and callchain; this patch
> set depends on the instruction sample fix patch set [1].
>
> This patch set get more complex, so before divide into small groups, I'd
> like to use this patch set version to include
Quoting Kuogee Hsieh (2020-11-03 12:49:02)
> Some dongles require link training done at irq_hpd request instead
> of plugin request. This patch promote irq_hpd handler to handle link
> training and setup hpd_state correctly.
>
> Fixes: fdaf9a5e3c15 (drm/msm/dp: fixes wrong connection state caused
Quoting Zong Li (2020-10-16 02:18:26)
> Refactor code by using DEFINE_PRCI_CLOCK to define each clock
> and reduce duplicate code.
What is duplicate?
>
> Signed-off-by: Zong Li
> ---
> drivers/clk/sifive/fu540-prci.c | 38 ++--
> drivers/clk/sifive/fu540-prci.h | 2 +-
> drivers
Quoting Zong Li (2020-10-16 02:18:24)
> Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
> patch is prepared for fu740 support.
>
> Signed-off-by: Zong Li
> ---
Looks ok but needs an ack from riscv maintainers to go through clk
tree. I was worried it would break defconfigs
Quoting Zong Li (2020-10-16 02:18:23)
> Extract common core of prci driver to an independent file, it could
> allow other chips to reuse it. Separate SoCs-dependent code 'fu540'
> from prci core, then we can easily add 'fu740' later.
Please indicate if there are any functional changes or this is j
Quoting Dmitry Baryshkov (2020-10-23 06:19:25)
> On SM8250 MMCX power domain is required to access MMDS_GDSC registers.
> This power domain is expressed as mmcx-supply regulator property. Use
> this regulator as MDSS_GDSC supply.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/clk/qcom/dispc
Quoting Srinivas Kandagatla (2020-10-26 05:02:21)
> LPASS Always ON Clock controller has one GFM mux to control VA
> and TX clocks to codec macro on LPASS.
> This patch adds support to this mux.
>
> Signed-off-by: Srinivas Kandagatla
> ---
Applied to clk-next
Quoting Srinivas Kandagatla (2020-10-26 05:02:18)
> Audio Clock controller is a block inside LPASS which controls
> 2 Glitch free muxes to LPASS codec Macros.
>
> Signed-off-by: Srinivas Kandagatla
> ---
Applied to clk-next
Quoting Srinivas Kandagatla (2020-10-26 05:02:21)
> LPASS Always ON Clock controller has one GFM mux to control VA
> and TX clocks to codec macro on LPASS.
> This patch adds support to this mux.
>
> Signed-off-by: Srinivas Kandagatla
> ---
Applied to clk-next
Quoting Srinivas Kandagatla (2020-10-26 05:02:20)
> GFM Muxes in AUDIO_CC control clocks to LPASS WSA and RX Codec Macros.
> This patch adds support to these muxes.
>
> Signed-off-by: Srinivas Kandagatla
> ---
Applied to clk-next
Quoting Srinivas Kandagatla (2020-10-26 05:02:19)
> Always ON Clock controller is a block inside LPASS which controls
> 1 Glitch free muxes to LPASS codec Macros.
>
> Signed-off-by: Srinivas Kandagatla
> ---
Applied to clk-next
Quoting Douglas Anderson (2020-10-19 15:49:35)
> The sc7180 lpass clock driver manages two different devices. These
> two devices were tangled together, using one probe and a lookup to
> figure out the real probe. I think it's cleaner to really separate
> the probe for these two devices since the
Quoting Douglas Anderson (2020-10-19 15:49:34)
> Let's convert the lpass clock control driver to use devm. This is a
> few more lines of code, but it will be useful in a later patch which
> disentangles the two devices handled by this driver.
>
> Signed-off-by: Douglas Anderson
> ---
This patte
Quoting Taniya Das (2020-10-16 11:43:33)
> Add programming sequence support for managing the Agera PLLs.
>
> Signed-off-by: Taniya Das
> ---
Applied to clk-next
Quoting Taniya Das (2020-10-16 11:43:32)
> Introduce clk_alpha_pll_write_config and alpha_pll_check_rate_margin
> helper functions to be across PLL configure functions and PLL set rate
> functions.
>
> Signed-off-by: Taniya Das
> ---
Applied to clk-next
Quoting Taniya Das (2020-10-16 11:43:35)
> Add support for the camera clock controller found on SC7180 based devices.
> This would allow camera drivers to probe and control their clocks.
>
> Signed-off-by: Taniya Das
> ---
Applied to clk-next with some minor fixups.
Quoting Taniya Das (2020-10-16 11:43:34)
> The Camera Subsystem clock provider have a bunch of generic properties
> that are needed in a device tree. Add a YAML schemas for those.
>
> Add clock ids for camera clocks which are required to bring the camera
> subsystem out of reset.
>
> Signed-off-b
Quoting Manivannan Sadhasivam (2020-10-28 00:42:32)
> Add support for clocks maintained by RPMh in SDX55 SoCs.
>
> Signed-off-by: Manivannan Sadhasivam
> ---
> drivers/clk/qcom/clk-rpmh.c | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-rpmh.c
Quoting Manivannan Sadhasivam (2020-10-28 00:42:30)
> From: Naveen Yadav
>
> Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm.
>
> Signed-off-by: Naveen Yadav
> [mani: converted to parent_data, commented critical clocks, cleanups]
> Signed-off-by: Manivannan Sadhasivam
>
Quoting Manivannan Sadhasivam (2020-10-30 20:29:44)
> Hi Rob,
>
> On Fri, Oct 30, 2020 at 02:22:25PM -0500, Rob Herring wrote:
> > On Wed, Oct 28, 2020 at 01:12:29PM +0530, Manivannan Sadhasivam wrote:
> > > From: Vinod Koul
> > >
> > > Add device tree bindings for global clock controller on SDX
Quoting Mauro Carvalho Chehab (2020-10-23 09:33:25)
> clk_get_duty_cycle -> clk_get_scaled_duty_cycle
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
Applied to clk-next
Quoting Mike Looijmans (2020-11-03 06:17:41)
> Export an attribute program_nvm_bank that when read reports the current
> bank value. To program the chip's current state into NVM, write the
> magic value 0xC7 into this attribute.
>
> Signed-off-by: Mike Looijmans
> ---
Any chance this can be done
Quoting Zou Wei (2020-11-04 03:19:31)
> Fix the following sparse warning:
>
> ./clk-scu.c:23:20: warning: symbol 'pd_np' was not declared. Should it be
> static?
>
> Reported-by: Hulk Robot
> Signed-off-by: Zou Wei
> ---
Reviewed-by: Stephen Boyd
Quoting Zou Wei (2020-11-03 03:32:14)
> This patch fixes below warning reported by coccicheck:
>
> ./clk-gate2.c:57:5-8: Unneeded variable: "ret". Return "0" on line 68
>
> Reported-by: Hulk Robot
> Signed-off-by: Zou Wei
> ---
Reviewed-by: Stephen Boyd
Quoting peng@nxp.com (2020-11-01 03:23:54)
> From: Peng Fan
>
> noc/axi/ahb are bus clk, not peripheral clk.
> Since peripheral clk has a limitation that for peripheral clock slice,
> IP clock slices must be stopped to change the clock source.
>
> However if the bus clk is marked as critical
pile warning (!CONFIG_OF && !CONFIG_MODULES):
>
> drivers/clk/imx/clk-imx8mp.c:751:34: warning:
> ‘imx8mp_clk_of_match’ defined but not used [-Wunused-const-variable=]
>
> Reported-by: kernel test robot
> Signed-off-by: Krzysztof Kozlowski
> ---
Acked-by: Stephen Boyd
pile warning (!CONFIG_OF && !CONFIG_MODULES):
>
> drivers/clk/imx/clk-imx8mq.c:626:34: warning:
> ‘imx8mq_clk_of_match’ defined but not used [-Wunused-const-variable=]
>
> Signed-off-by: Krzysztof Kozlowski
> ---
Acked-by: Stephen Boyd
pile warning (!CONFIG_OF && !CONFIG_MODULES):
>
> drivers/clk/imx/clk-imx8mm.c:641:34: warning:
> ‘imx8mm_clk_of_match’ defined but not used [-Wunused-const-variable=]
>
> Signed-off-by: Krzysztof Kozlowski
> ---
Acked-by: Stephen Boyd
pile warning (!CONFIG_OF && !CONFIG_MODULES):
>
> drivers/clk/imx/clk-imx8mn.c:592:34: warning:
> ‘imx8mn_clk_of_match’ defined but not used [-Wunused-const-variable=]
>
> Signed-off-by: Krzysztof Kozlowski
> ---
Acked-by: Stephen Boyd
Quoting Abel Vesa (2020-11-03 03:18:23)
> This driver is intended to work with the following BLK_CTL IPs found in
> i.MX8MP:
> - Audio
> - Media
> - HDMI
>
> Signed-off-by: Abel Vesa
> ---
Reviewed-by: Stephen Boyd
Quoting Abel Vesa (2020-11-03 03:18:21)
> Document the i.MX BLK_CTL with its devicetree properties.
>
> Signed-off-by: Abel Vesa
> Reviewed-by: Dong Aisheng
> Reviewed-by: Rob Herring
> ---
Acked-by: Stephen Boyd
> diff --git a/Documentation/devicetree/bindings/clock
Quoting Abel Vesa (2020-11-03 03:18:19)
> These will be used imx8mp for blk_ctl driver.
>
> Signed-off-by: Abel Vesa
> Acked-by: Rob Herring
> Reviewed-by: Dong Aisheng
> ---
Acked-by: Stephen Boyd
t;
> Signed-off-by: Abel Vesa
> Reviewed-by: Dong Aisheng
> ---
Acked-by: Stephen Boyd
Quoting Abel Vesa (2020-11-03 03:18:18)
> These will be used by the imx8mp for blk_ctl driver.
>
> Signed-off-by: Abel Vesa
> Acked-by: Rob Herring
> Reviewed-by: Dong Aisheng
> ---
Acked-by: Stephen Boyd
Quoting Abel Vesa (2020-11-03 03:18:15)
> All these IDs are for one single HW gate (CCGR101) that is shared
> between these root clocks.
>
> Signed-off-by: Abel Vesa
> Acked-by: Rob Herring
> Reviewed-by: Dong Aisheng
> ---
Acked-by: Stephen Boyd
Quoting Abel Vesa (2020-11-03 03:18:13)
> In the reference manual the actual name is Audio BLK_CTL.
> Lets make it more obvious here by renaming from audiomix to audio_blk_ctl.
>
> Signed-off-by: Abel Vesa
> Acked-by: Rob Herring
> Reviewed-by: Dong Aisheng
> ---
Acked-by: Stephen Boyd
Quoting Abel Vesa (2020-11-03 03:18:14)
> These will be used by the imx8mp for blk_ctl driver.
>
> Signed-off-by: Abel Vesa
> Acked-by: Rob Herring
> Reviewed-by: Dong Aisheng
> ---
Acked-by: Stephen Boyd
Quoting Abel Vesa (2020-11-03 03:18:17)
> These will be used by the imx8mp for blk_ctl driver.
>
> Signed-off-by: Abel Vesa
> Acked-by: Rob Herring
> Reviewed-by: Dong Aisheng
> ---
Acked-by: Stephen Boyd
Quoting Abel Vesa (2020-11-03 03:18:16)
> These will be used by the imx8mp for blk_ctl driver.
>
> Signed-off-by: Abel Vesa
> Acked-by: Rob Herring
> Reviewed-by: Dong Aisheng
> ---
Acked-by: Stephen Boyd
Quoting Abel Vesa (2020-11-03 03:18:22)
> diff --git a/drivers/clk/imx/clk-blk-ctl.c b/drivers/clk/imx/clk-blk-ctl.c
> new file mode 100644
> index ..9ac0ed0
> --- /dev/null
> +++ b/drivers/clk/imx/clk-blk-ctl.c
> @@ -0,0 +1,302 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Cop
Quoting Michael Walle (2020-11-01 10:48:18)
> diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
> index 0221180a4dd7..1e81c8d8a6fd 100644
> --- a/drivers/clk/clk-fsl-sai.c
> +++ b/drivers/clk/clk-fsl-sai.c
> @@ -68,9 +68,20 @@ static int fsl_sai_clk_probe(struct platform_device *pd
tells the guest this mapping:
0 is SPECTRE_MITIGATED
1 is SPECTRE_UNAFFECTED
SMCCC_RET_NOT_SUPPORTED is SPECTRE_VULNERABLE
Note: SMCCC_RET_NOT_AFFECTED is 1 but isn't part of the SMCCC spec
Fixes: c118bbb52743 ("arm64: KVM: Propagate full Spectre v2 workaround state to
KVM guests")
Sig
tells the guest this mapping:
0 is SPECTRE_MITIGATED
1 is SPECTRE_UNAFFECTED
SMCCC_RET_NOT_SUPPORTED is SPECTRE_VULNERABLE
Note: SMCCC_RET_NOT_AFFECTED is 1 but isn't part of the SMCCC spec
Fixes: c118bbb52743 ("arm64: KVM: Propagate full Spectre v2 workaround state to
KVM guests")
Sig
Quoting Stephen Boyd (2020-11-02 17:15:24)
> Quoting Sam Ravnborg (2020-11-01 09:37:41)
> > Hi Stephen.
> >
> > On Thu, Oct 29, 2020 at 06:17:34PM -0700, Stephen Boyd wrote:
> > > This patch series cleans up the DDC code a little bit so that
> > > it i
Quoting Sam Ravnborg (2020-11-01 09:37:41)
> Hi Stephen.
>
> On Thu, Oct 29, 2020 at 06:17:34PM -0700, Stephen Boyd wrote:
> > This patch series cleans up the DDC code a little bit so that
> > it is more efficient time wise and supports grabbing the EDID
> > of the eDP
Quoting Kuogee Hsieh (2020-10-30 16:22:53)
> DP compo phy have to be enable to start link training. When
> link training failed phy need to be disabled so that next
> link trainng can be proceed smoothly at next plug in. This
s/trainng/training/
> patch de initialize mainlink to disable phy if li
Quoting Kuogee Hsieh (2020-10-30 16:23:10)
> Some dongle will not clear LINK_STATUS_UPDATED bit after
> DPCD read which cause link training failed. This patch
$ git grep 'this patch' -- Documentation/process/submitting-patches.rst
> just read 6 bytes of DPCD link status from sink and return
> wit
Subject has a typo in "training".
Quoting Kuogee Hsieh (2020-10-30 16:23:24)
> Some dongles, such as Apple, required link training done at irq_hpd
s/required/require/
> request instead of plugin request. This patch promote irq_hpd hanlder
s/hanlder/handler/
> to handle link training and setup
2:
- Move WRITE_STATUS_UPDATE check from case to assignment
Changes in v2:
- Handle WRITE_STATUS_UPDATE properly
Reviewed-by: Douglas Anderson
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Acked-by: Sam Ravnborg
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-s
chart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Acked-by: Sam Ravnborg
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 50 ---
1 file changed, 22 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
b/driver
ected properly instead of
treating them as some sort of error that can't be discerned.
Stephen Boyd (4):
drm/bridge: ti-sn65dsi86: Combine register accesses in
ti_sn_aux_transfer()
drm/bridge: ti-sn65dsi86: Make polling a busy loop
drm/bridge: ti-sn65dsi86: Read EDID blob over DDC
drm/
Use the DDC connection to read the EDID from the eDP panel instead of
relying on the panel to tell us the modes.
Reviewed-by: Douglas Anderson
Reviewed-by: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Acked-by: Sam Ravnborg
Signed-off-by: Stephen Boyd
---
drivers
adding any sort of delay here in the bridge driver.
Reviewed-by: Douglas Anderson
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Acked-by: Sam Ravnborg
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4 ++--
1 file changed, 2 insertions(+), 2
Quoting Doug Anderson (2020-11-02 08:06:14)
> On Sun, Nov 1, 2020 at 11:21 AM Laurent Pinchart
> wrote:
> > On Thu, Oct 29, 2020 at 06:17:37PM -0700, Stephen Boyd wrote:
> > > @@ -265,6 +267,23 @@ connector_to_ti_sn_bridge(struct drm_connector
> > >
Quoting Doug Anderson (2020-11-02 08:37:21)
> Hi,
>
> On Sun, Nov 1, 2020 at 9:37 AM Sam Ravnborg wrote:
> >
> > Hi Stephen.
> >
> > On Thu, Oct 29, 2020 at 06:17:34PM -0700, Stephen Boyd wrote:
> > > This patch series cleans up the DDC code a little b
Quoting Doug Anderson (2020-11-02 08:18:47)
> Hi,
>
> On Thu, Oct 29, 2020 at 6:17 PM Stephen Boyd wrote:
> >
> > These register reads and writes are sometimes directly next to each
> > other in the register address space. Let's use regmap bulk read/write
&
Quoting Viresh Kumar (2020-10-29 21:20:00)
> On 29-10-20, 09:40, Viresh Kumar wrote:
> > Thanks a lot. I was a bit worried about the crazy idea I had to solve
> > this :)
>
> Hmm, I thought this is the other patch where I had that crazy idea.
> This one was quite straight forward :)
>
What's the
i
Cc:
Signed-off-by: Stephen Boyd
---
I wonder if it makes more sense to look for certain events and treat
them as wakeup sources? It may be that most of the time an EC event
can be pm_relax()ed too and only need to be held active until the
processing is over? I haven't looked beyond this
Quoting Stephen Boyd (2020-10-28 18:11:51)
> @@ -72,6 +74,7 @@
> #define SN_AUX_ADDR_19_16_REG 0x74
> #define SN_AUX_ADDR_15_8_REG 0x75
> #define SN_AUX_ADDR_7_0_REG0x76
> +#define SN_AUX_ADDR_MASK
- Handle WRITE_STATUS_UPDATE properly
Cc: Douglas Anderson
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 36 ---
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/d
adding any sort of delay here in the bridge driver.
Reviewed-by: Douglas Anderson
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
di
Use the DDC connection to read the EDID from the eDP panel instead of
relying on the panel to tell us the modes.
Reviewed-by: Douglas Anderson
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 20
Sean Paul
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 52 ---
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index ecdf9b01340f..a1ebfa95088c 100644
ected properly instead of
treating them as some sort of error that can't be discerned.
Stephen Boyd (4):
drm/bridge: ti-sn65dsi86: Combine register accesses in
ti_sn_aux_transfer()
drm/bridge: ti-sn65dsi86: Make polling a busy loop
drm/bridge: ti-sn65dsi86: Read EDID blob over DDC
drm/
Quoting Doug Anderson (2020-10-29 09:22:55)
> Hi,
>
> On Wed, Oct 28, 2020 at 6:12 PM Stephen Boyd wrote:
> >
> > We should be setting the drm_dp_aux_msg::reply field if a NACK or a
> > SHORT reply happens.
>
> I don't think you update the "reply&qu
ading an EDID where we read in blocks of 16 bytes at a
time and the last for loop here is sending an i2c transfer for each of
those 16 bytes, one at a time. Ouch!
Cc: Douglas Anderson
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Signed-off-by: Stephen Boyd
---
driver
Use the DDC connection to read the EDID from the eDP panel instead of
relying on the panel to tell us the modes.
Cc: Douglas Anderson
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 20
to shorten the read length if the panel isn't
able to handle the longest read possible.
Cc: Douglas Anderson
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 31 +++
1
adding any sort of delay here in the bridge driver.
Cc: Douglas Anderson
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Sean Paul
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drive
o implement
the bridge func get_edid() function in the future if the DDC is
implemented and we're using the new bridge connector code.
Stephen Boyd (4):
drm/bridge: ti-sn65dsi86: Combine register accesses in
ti_sn_aux_transfer()
drm/bridge: ti-sn65dsi86: Make polling a busy loop
drm/
Quoting Arnd Bergmann (2020-10-26 09:13:57)
> From: Arnd Bergmann
>
> Nesting container_of() causes warnings with W=2, which is
> annoying if it happens in headers and fills the build log
> like:
>
> In file included from drivers/clk/qcom/clk-alpha-pll.c:6:
> drivers/clk/qcom/clk-alpha-pll.c: In
Osipenko
> Signed-off-by: Viresh Kumar
> ---
Any Fixes tag?
Reviewed-by: Stephen Boyd
Quoting Will Deacon (2020-10-26 06:25:33)
> On Fri, Oct 23, 2020 at 08:47:50AM -0700, Stephen Boyd wrote:
> > diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
> > index 15c706fb0a37..0e50ba3e88d7 100644
> > --- a/include/linux/arm-smccc.h
> > +++
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