[PATCH v2 2/4] ARM: dts: exynos: Add high speed I2C ports for exynos5260

From: Stuart Menefy Most of the work to support the high speed I2C ports on the Exynos 5260 was added in commit 218e1496135e ("i2c: exynos5: add support for HSI2C on Exynos5260 SoC") and the pinctrl nodes have always been available. All that is missing to get them working is the addi

[PATCH v2 4/4] ARM: dts: exynos: Fix interrupt for shared EINTs on Exynos5260

From: Stuart Menefy Fix the interrupt information for the GPIO lines with a shared EINT interrupt. Signed-off-by: Stuart Menefy --- arch/arm/boot/dts/exynos5260.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts

[PATCH v2 3/4] ARM: dts: exynos: Add interrupts for dedicated EINTs on Exynos5260

From: Stuart Menefy Add the missing interrupt information for the GPIO lines with dedicated EINT interrupts. Signed-off-by: Stuart Menefy --- arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/exynos5260

[PATCH v2 0/4] Devicetree updates for Exynos 5260

260" - Expanded patch comments Stuart Menefy (4): ARM: dts: exynos: Use bustop PLL as the source for MMC clocks on Exynos5260 ARM: dts: exynos: Add high speed I2C ports for exynos5260 ARM: dts: exynos: Add interrupts for dedicated EINTs on Exynos5260 ARM: dts: exynos: Fix interrupt

[PATCH v2 1/4] ARM: dts: exynos: Use bustop PLL as the source for MMC clocks on Exynos5260

From: Stuart Menefy By default the MMC clock will be derived from mediatop PLL, which usually runs at 666MHz. However as most SD and MMC clocks are multiples or fractions of 100MHz, it makes more sense to use the bustop PLL which runs at 800MHz. This matches the behaviour of the Samsung vendor

[PATCH v3 1/2] mfd: sec: Put one element structure initialisation on one line

Change the layout of the initialisation of structures with one element to a single line of code. This keeps the coding style consistent. Signed-off-by: Stuart Menefy --- drivers/mfd/sec-core.c | 58 +- 1 file changed, 19 insertions(+), 39

[PATCH v3 0/2] mfd: sec: Add support for the RTC on S2MPA01

existing one element structure initialisation - Rebase patch 2/2 Changes since v1: - Remove the duplicated code and simply declare the RTC to be the same as that on the S2MPS14. Stuart Menefy (2): mfd: sec: Put one element structure initialisation on one line mfd: sec: Add support for the

[PATCH v3 2/2] mfd: sec: Add support for the RTC on S2MPA01

The RTC portion of the S2MPA01 appears to have the same register layout as the S2MPS14. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stuart Menefy --- drivers/mfd/sec-core.c | 1 + drivers/mfd/sec-irq.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/mfd/sec-core.c b

[PATCH v2] regulator: s2mpa01: Fix step values for some LDOs

The step values for some of the LDOs appears to be incorrect, resulting in incorrect voltages (or at least, ones which are different from the Samsung 3.4 vendor kernel). Signed-off-by: Stuart Menefy Reviewed-by: Krzysztof Kozlowski --- drivers/regulator/s2mpa01.c | 10 +- 1 file

[PATCH v2] mfd: sec: Add support for the RTC on S2MPA01

The RTC portion of the S2MPA01 appears to have the same register layout as the S2MPS14. Signed-off-by: Stuart Menefy --- drivers/mfd/sec-core.c | 2 ++ drivers/mfd/sec-irq.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c index

[PATCH] tty: serial: samsung: Enable baud clock during initialisation

e possible baud clock sources _and_ requires the correct baud clock to be enabled before accessing any of the serial port registers (in particular the register which selects which clock to use as the baud clock). As far as I know such hardware doesn't exist. Signed-off-by: Stuart Menefy ---

[PATCH 2/2] clocksource: exynos_mct: Clear timer interrupt when shutdown

when the wfi is executed. Signed-off-by: Stuart Menefy --- drivers/clocksource/exynos_mct.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 1e325f89d408..d55c30f6981d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b

[PATCH 0/2] Subject: [PATCH 0/2] clocksource: exynos_mct: Clear timer interrupt when shutting down

upt flag. Once this has been done simply call exynos4_mct_tick_clear() from set_state_shutdown(). Stuart Menefy (2): clocksource: exynos_mct: Move one-shot check from tick clear to ISR clocksource: exynos_mct: Clear timer interrupt when shutdown drivers/clocksource/ex

[PATCH 1/2] clocksource: exynos_mct: Move one-shot check from tick clear to ISR

exynos4_mct_tick_clear() just doing what its name suggests it should. Signed-off-by: Stuart Menefy --- drivers/clocksource/exynos_mct.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 7a244b681876

Re: [PATCH 1/4] clocksource: arm_global_timer: Switch to sched_clock_register()

Looks good, thanks. Acked-by: Stuart Menefy On 15/11/13 23:48, Stephen Boyd wrote: > The 32 bit sched_clock interface now supports 64 bits. Upgrade to > the 64 bit function to allow us to remove the 32 bit registration > interface. While we're here increase the number of bits that

Re: [RFC 2/8] ARM:global_timer: Add ARM global timer support.

On 08/05/13 15:26, Rob Herring wrote: > On 05/08/2013 09:11 AM, Srinivas KANDAGATLA wrote: >> From: Stuart Menefy >> >> This is a simple driver for the global timer module found in the Cortex >> A9-MP cores from revision r1p0 onwards. This should be able to perform >