Hi Jerome,
On 2018/12/13 17:28, Jerome Brunet wrote:
On Thu, 2018-12-13 at 09:55 +0100, Neil Armstrong wrote:
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
config SPI_MESON_SPICC
tristate "Amlogic Meson SPICC controller"
- depends on ARCH_MESON || COMPILE_TEST
+
Hi Jerome,
On 2018/12/13 17:04, Jerome Brunet wrote:
On Thu, 2018-12-13 at 16:39 +0800, Sunny Luo wrote:
The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating
Hi Neil,
On 2018/12/13 16:55, Neil Armstrong wrote:
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
The SPICC controller in Meson-AXG SoC is capable of using
a linear clock divider to reach a much fine tuned range of clocks,
while the old controller only use a power of two clock divider
Hi Neil,
On 2018/12/13 16:53, Neil Armstrong wrote:
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in unexpected
Hi Mark,
On 2018/12/13 19:53, Mark Brown wrote:
On Thu, Dec 13, 2018 at 10:04:56AM +0100, Jerome Brunet wrote:
On Thu, 2018-12-13 at 16:39 +0800, Sunny Luo wrote:
writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
+ meson_spicc_oen_enable(spicc);
+
Any speci
Hi Neil,
On 2018/12/13 16:49, Neil Armstrong wrote:
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
The SPICC controller in Meson-AXG is capable of running at 80M clock.
The ASIC IP is improved and the clock is actually running higher than
previous old SoCs.
Signed-off-by: Sunny Luo
Signed
The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in unexpected state.
Signed-off-by: Sunny Luo
Signed-off-by: Yixun Lan
---
drivers/spi/spi-meson-spicc.c | 28
.
Signed-off-by: Sunny Luo
Signed-off-by: Yixun Lan
---
drivers/spi/Kconfig | 2 +-
drivers/spi/spi-meson-spicc.c | 209 ++
2 files changed, 170 insertions(+), 41 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9f89cb1
error.
[1] https://lore.kernel.org/lkml/20180503213645.20694-1-yixun@amlogic.com
Sunny Luo (3):
spi: meson-axg: support MAX 80M clock
spi: meson-axg: enhance output enable feature
spi: meson-axg: add a linear clock divider support
drivers/spi/Kconfig | 2 +-
drivers/spi/spi
The SPICC controller in Meson-AXG is capable of running at 80M clock.
The ASIC IP is improved and the clock is actually running higher than
previous old SoCs.
Signed-off-by: Sunny Luo
Signed-off-by: Yixun Lan
---
drivers/spi/spi-meson-spicc.c | 37 +
1 file
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