We use a stop_machine call for each available capability to
enable it on all the CPUs available at boot time. Instead
we could batch the cpu_enable callbacks to a single stop_machine()
call to save us some time.
Cc: Vladimir Murzin
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm
Remove duplicate entries for Qualcomm erratum 1003. Since the entries
are not purely based on generic MIDR checks, use the multi_cap_entry
type to merge the entries.
Cc: Christopher Covington
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/cpu_errata.c | 25
Make use of the sorted capability list to access the capability
entry in this_cpu_has_cap() to avoid iterating over the two
tables.
Cc: Vladimir Murzin
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/cpufeature.c | 31 +--
1 file changed, 9 insertions(+), 22
Merge duplicate entries for a single capability using the midr
range list for Cavium errata 30115 and 27456.
Cc: Andrew Pinski
Cc: David Daney
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cputype.h | 2 ++
arch/arm64/kernel/cpu_errata.c
Przywara
Cc: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/cpu_errata.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index a509e351..c825bc0 100644
--- a/arch/arm64
ere's some problem.
Thanks,
Chunyan
----
Suzuki K Poulose (1):
arm64: dts: sc9836/sc9860: Update coresight bindings for hardware
ports
arch/arm64/boot/dts/sprd/sc9836.dtsi | 78 +++--
arch/arm64/boot/dts/sprd/s
e before use")
Cc: Suzuki Poulose
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Robert Walker
Signed-off-by: Leo Yan
Reviewed-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/co
; add AA64ISAR1.API HWCAP_CAP; use
sysreg_clear_set]
Signed-off-by: Kristina Martsenko
Tested-by: Adam Wallis
Cc: Catalin Marinas
Cc: Ramana Radhakrishnan
Cc: Suzuki K Poulose
Cc: Will Deacon
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 0dd171c7d71e
Hi Ganapatrao,
On 11/10/18 07:39, Ganapatrao Kulkarni wrote:
+
+/*
+ * We must NOT create groups containing events from multiple hardware PMUs,
+ * although mixing different software and hardware PMUs is allowed.
+ */
+static bool thunderx2_uncore_validate_event_group(struct perf_event *event)
+
When there is a mismatch in the CTR_EL0 field, we trap
access to CTR from EL0 on all CPUs to expose the safe
value. However, we could skip trapping on a CPU which
matches the safe value.
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64
the system in an inconsistent state, where
the system assumes it has IDC/DIC feature, while the new CPU
doesn't.
Fixes: commit 6ae4b6e0578886eb36 ("arm64: Add support for new control bits
CTR_EL0.DIC and CTR_EL0.IDC")
Cc: Philip Elcan
Cc: Shanker Donthineni
Cc: Mark Rutland
Cc:
rk Rutland
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cache.h | 40 ++
arch/arm64/kernel/cpu_errata.c | 27 ---
arch/arm64/kernel/cpufeature.c | 15 -
arch/arm64/kernel/cpuinfo.c| 10 -
4 files changed, 87 i
with raw CTR_EL0.IDC = 0 and effective
CTR_EL0.IDC = 1, to boot on a system without IDC available.
Suzuki K Poulose (3):
arm64: cpufeature: ctr: Fix cpu capability check for late CPUs
arm64: cpufeature: Fix handling of CTR_EL0.IDC field
arm64: cpufeature: Trap CTR_EL0 access only where it
with raw CTR_EL0.IDC = 0 and effective
CTR_EL0.IDC = 1, to boot on a system without IDC available.
Suzuki K Poulose (3):
arm64: cpufeature: ctr: Fix cpu capability check for late CPUs
arm64: cpufeature: Fix handling of CTR_EL0.IDC field
arm64: cpufeature: Trap CTR_EL0 access only where it
Hi,
On 04/10/18 09:33, Suzuki K Poulose wrote:
CTR_EL0.IDC reports the data cache clean requirements for instruction
to data coherence. However, if the field is 0, we need to check the
CLIDR_EL1 fields to detect the status of the feature. Currently we
don't do this and generate a warning
rk Rutland
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cache.h | 40 ++
arch/arm64/kernel/cpu_errata.c | 10 +++--
arch/arm64/kernel/cpufeature.c | 17 +--
arch/arm64/kernel/cpuinfo.c| 10 -
4 files changed, 72 insertions(+), 5
This series makes sure that we handle the CTR_EL0 field mismatches
properly, especially for the IDC field. Also, skip trapping CTR
accesses on a CPU if it matches the safe value.
Applies on arm64 for-next/core
Suzuki K Poulose (3):
arm64: cpufeature: ctr: Fix cpu capability check for late CPUs
the system in an inconsistent state, where
the system assumes it has IDC/DIC feature, while the new CPU
doesn't.
Fixes: commit 6ae4b6e0578886eb36 ("arm64: Add support for new control bits
CTR_EL0.DIC and CTR_EL0.IDC")
Cc: Philip Elcan
Cc: Shanker Donthineni
Cc: Mark Rutland
Cc:
When there is a mismatch in the CTR_EL0 field, we trap
access to CTR from EL0 on all CPUs to expose the safe
value. However, we could skip trapping on a CPU which
matches the safe value.
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64
On 03/10/18 12:10, Anshuman Khandual wrote:
On 10/03/2018 03:52 PM, Suzuki K Poulose wrote:
On 02/10/18 13:56, Anshuman Khandual wrote:
On 10/02/2018 06:08 PM, Suzuki K Poulose wrote:
Hi Anshuman
On 02/10/18 13:15, Anshuman Khandual wrote:
Architectures like arm64 have PUD level
On 02/10/18 13:56, Anshuman Khandual wrote:
On 10/02/2018 06:08 PM, Suzuki K Poulose wrote:
Hi Anshuman
On 02/10/18 13:15, Anshuman Khandual wrote:
Architectures like arm64 have PUD level HugeTLB pages for certain configs
(1GB huge page is PUD based on ARM64_4K_PAGES base page size) that
Hi Anshuman
On 02/10/18 13:15, Anshuman Khandual wrote:
Architectures like arm64 have PUD level HugeTLB pages for certain configs
(1GB huge page is PUD based on ARM64_4K_PAGES base page size) that can be
enabled for migration. It can be achieved through checking for PUD_SHIFT
order based HugeTLB
On 09/26/2018 01:12 PM, Maciej Slodczyk wrote:
Fix checkpatch issues in moved arm uprobes code.
Again the patch doesn't have anything to do with arm64, so wrong tag.
Otherwise looks fine.
Suzuki
On 09/26/2018 01:11 PM, Maciej Slodczyk wrote:
Move ARM32 uprobes code from arch/arm/probes/ to a more common location -
lib/probes/arm/. This code will be used by ARM64 code when uprobing 32-bit
applications.
The patch looks OK to me, with the following nit:
The subject tag looks incorrect. S
+To: Chunyan Zhang
Chunyan Zhang,
On 09/12/2018 02:53 PM, Suzuki K Poulose wrote:
Switch to the new coresight bindings for hw ports
How can we push this patch ? Do you generally send the spreadtrum
specific changes to ARM soc folks ? Or would you like me to post
this directly to ARM soc
Hi Andy
On 09/12/2018 02:53 PM, Suzuki K Poulose wrote:
Switch to updated coresight bindings for hw ports
Cc: Andy Gross
Cc: David Brown
Cc: Ivan T. Ivanov
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v1:
- Fixed TPIU port direction
- Use better subject tag
On 09/25/2018 11:00 AM, Auger Eric wrote:
Hi Suzuki,
On 9/17/18 12:41 PM, Suzuki K Poulose wrote:
Since we are about to remove the lower limit on the IPA size,
make sure that we do not go to 1 level page table (e.g, with
32bit IPA on 64K host with concatenation) to avoid splitting
the host PMD
On 24/09/18 11:50, Julien Thierry wrote:
Hi,
On 24/09/18 11:33, Suzuki K Poulose wrote:
Hi Marc,
On 21/09/18 20:59, Marc Zyngier wrote:
LPI_PENDING_SZ is always used in conjunction with a max(). Let's
factor this in the definition of the macro, and simplify the rest
of the code.
S
Hi Marc,
On 21/09/18 20:59, Marc Zyngier wrote:
LPI_PENDING_SZ is always used in conjunction with a max(). Let's
factor this in the definition of the macro, and simplify the rest
of the code.
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 12
1 file changed,
Linus,
On 20/09/18 23:02, Linus Walleij wrote:
On Wed, Sep 12, 2018 at 6:54 AM Suzuki K Poulose wrote:
Switch to the new coresight bindings
Cc: Linus Walleij
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Applied to the ux500 tree.
Thanks !
Suzuki
IMPORTANT NOTICE: The contents
Hi Linus,
On 14/09/18 09:43, Linus Walleij wrote:
On Wed, Sep 12, 2018 at 3:54 PM Suzuki K Poulose wrote:
Switch to the new coresight bindings
Cc: Linus Walleij
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Acked-by: Linus Walleij
Thanks.
I guess you will merge this with
Hi Greg,
On 12/09/18 20:38, Greg KH wrote:
On Tue, Sep 04, 2018 at 10:10:09AM +0100, Suzuki K Poulose wrote:
commit 4c4a39dd5fe2d13e2d2fa5fceb8ef95d19fc389a upstream
If there is a mismatch in the I/D min line size, we must
always use the system wide safe value both in applications
and in the
While we updated the coresight DT bindings, some of the
new examples were not updated due to the order in which they
were merged. Let us update all the missed out ones to the
new bindings to avoid confusion.
Cc: Mathieu Poirier
Cc: Rob Herring
Cc: Frank Rowand
Signed-off-by: Suzuki K Poulose
Switch to the new hardware port bindings for coresight
Cc: Andy Gross
Cc: David Brown
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 71 ++-
arch/arm/boot/dts/qcom-msm8974.dtsi | 104 +++-
2 files changed
Switch to the new the hardware port bindings.
Cc: Wei Xu
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/hip04.dtsi | 346 ++-
1 file changed, 176 insertions(+), 170 deletions(-)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm
Switch to the new coresight bindings for hardware ports
Cc: Nicolas Ferre
Cc: Alexandre Belloni
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/sama5d2.dtsi | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts
Switch to the new coresight bindings for hardware ports
Cc: linux-o...@vger.kernel.org
Cc: "Benoît Cousson"
Cc: Tony Lindgren
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/omap3-beagle-xm.dts | 17 ++---
arch/arm/boot/dts/omap3-beagle.d
Switch to the new coresight bindings
Cc: Linus Walleij
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/ste-dbx5x0.dtsi | 65 ---
1 file changed, 33 insertions(+), 32 deletions(-)
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi
b/arch/arm
Switch to updated coresight bindings for hw ports
Cc: Andy Gross
Cc: David Brown
Cc: Ivan T. Ivanov
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v1:
- Fixed TPIU port direction
- Use better subject tag for the patch
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 95
Switch to the updated coresight bindings.
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/imx7d.dtsi | 14 +++---
arch/arm/boot/dts/imx7s.dtsi | 82
2
Switch to the new coresight bindings for hw ports
Cc: orsonz...@gmail.com
Cc: zhang.l...@gmail.com
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/boot/dts/sprd/sc9836.dtsi | 82 +-
arch/arm64/boot/dts/sprd/sc9860.dtsi | 215 ++-
2 files
TPIU component has an input port. The example uses out-ports
which is wrong. Let us fix it.
Reported-by: Leo Yan
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Documentation/devicetree/bindings/arm/coresight.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Switch to updated coresight bindings for hw ports.
Cc: xuw...@hisilicon.com
Cc: lipengche...@huawei.com
Cc: Mathieu Poirier
Tested-by: Leo Yan
Signed-off-by: Suzuki K Poulose
---
.../boot/dts/hisilicon/hi6220-coresight.dtsi | 181 +-
1 file changed, 86 insertions(+), 95
y Lindgren
Cc: Wei Xu
Cc: xuw...@hisilicon.com
Cc: zhang.l...@gmail.com
Cc: a...@kernel.org
Suzuki K Poulose (11):
coresight: dts: binding: Fix example for TPIU component
coresight: dts: binding: Update coresight binding examples
arm64: dts: hi6220: Update coresight bindings for hard
Hi Leo,
On 12/09/18 11:47, leo@linaro.org wrote:
On Tue, Sep 11, 2018 at 11:17:03AM +0100, Suzuki K Poulose wrote:
Switch to updated coresight bindings for hw ports.
As Shawn suggested, please change subject as "arm64: dts: hi6220:
"
Sure, will do.
Cc: xuw...@hisili
On 12/09/18 11:28, James Morse wrote:
Hi Julien,
On 28/08/18 16:51, Julien Thierry wrote:
The cpu_enable callback for VHE feature requires all alternatives to have
been applied. This prevents applying VHE alternative separately from the
rest.
Use an alternative depending on VHE feature to know
Hi Leo,
On 12/09/18 11:17, leo@linaro.org wrote:
Hi Suzuki,
On Tue, Sep 11, 2018 at 11:17:05AM +0100, Suzuki K Poulose wrote:
Switch to updated coresight bindings for hw ports
Cc: Andy Gross
Cc: David Brown
Cc: Ivan T. Ivanov
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
On 12/09/18 03:21, Shawn Guo wrote:
On Tue, Sep 11, 2018 at 11:17:07AM +0100, Suzuki K Poulose wrote:
Switch to the updated coresight bindings.
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
As per the
On 09/11/2018 11:17 AM, Suzuki K Poulose wrote:
Coresight DT bindings have been updated to obey the DTS rules
for label/address matching for graph nodes. The changes are in
coresight/next tree scheduled for v4.20. This series updates the
in kernel dts to match the new bindings along with
On 09/11/2018 06:23 PM, Sudeep Holla wrote:
On 11/09/18 18:15, Suzuki K Poulose wrote:
On 09/11/2018 06:01 PM, Sudeep Holla wrote:
On Tue, Sep 11, 2018 at 11:17:12AM +0100, Suzuki K Poulose wrote:
Switch to the new coresight bindings
I still see the below warnings:
vexpress-v2p-ca15_a7
On 09/11/2018 06:01 PM, Sudeep Holla wrote:
On Tue, Sep 11, 2018 at 11:17:12AM +0100, Suzuki K Poulose wrote:
Switch to the new coresight bindings
I still see the below warnings:
vexpress-v2p-ca15_a7.dtb: Warning (graph_child_address):
/replicator/in-ports: graph node has single
While we updated the coresight DT bindings, some of the
new examples were not updated due to the order in which they
were merged. Let us update all the missed out ones to the
new bindings to avoid confusion.
Cc: Mathieu Poirier
Cc: Rob Herring
Cc: Frank Rowand
Signed-off-by: Suzuki K Poulose
Switch to the new the hardware port bindings.
Cc: Wei Xu
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/hip04.dtsi | 322 ---
1 file changed, 183 insertions(+), 139 deletions(-)
diff --git a/arch/arm/boot/dts/hip04.dtsi b
Switch to the new coresight bindings
Cc: Liviu Dudau
Cc: Sudeep Holla
Cc: Lorenzo Pieralisi
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 90 +-
1 file changed, 51 insertions(+), 39 deletions(-)
diff --git a
Switch to the updated coresight bindings.
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/imx7d.dtsi | 11 ---
arch/arm/boot/dts/imx7s.dtsi | 78
Switch to the new coresight bindings
Cc: Linus Walleij
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/ste-dbx5x0.dtsi | 61 ++-
1 file changed, 35 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi
b
Switch to the new coresight bindings for hardware ports
Cc: Nicolas Ferre
Cc: Alexandre Belloni
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/sama5d2.dtsi | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts
Switch to the new hardware port bindings for coresight
Cc: Andy Gross
Cc: David Brown
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 75 +++--
arch/arm/boot/dts/qcom-msm8974.dtsi | 108 +++-
2
Switch to the new coresight bindings for hardware ports
Cc: linux-o...@vger.kernel.org
Cc: "Benoît Cousson"
Cc: Tony Lindgren
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/omap3-beagle-xm.dts | 17 ++---
arch/arm/boot/dts/omap3-beagle.d
: zhang.l...@gmail.com
Cc: a...@kernel.org
Suzuki K Poulose (11):
Documentation: dts: Update coresight binding examples
dts: hisilicon: Update coresight bindings for hardware ports
dts: spreadtrum: Update coresight bindings for hardware ports
dts: qcom: Update coresight bindings for hardware
Switch to updated coresight bindings for hw ports.
Cc: xuw...@hisilicon.com
Cc: lipengche...@huawei.com
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 147 -
1 file changed, 85 insertions(+), 62 deletions
Switch to the new coresight bindings for hw ports
Cc: orsonz...@gmail.com
Cc: zhang.l...@gmail.com
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/boot/dts/sprd/sc9836.dtsi | 74 --
arch/arm64/boot/dts/sprd/sc9860.dtsi | 183
Switch to updated coresight bindings for hw ports
Cc: Andy Gross
Cc: David Brown
Cc: Ivan T. Ivanov
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 98 ++-
1 file changed, 63 insertions(+), 35 deletions(-)
diff
is safe to use the mode.
All revisions of Juno have a proper ETR connection and hence
white list them.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Sudeep Holla
Cc: Liviu Dudau
Cc: Lorenzo Pierlisi
Signed-off-by: Suzuki K Poulose
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 1 +
1 file changed, 1
Prepare to handle errors in enabling the hardware and
report it back to the core driver.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v1:
- Fix return code for tmc_enable_etf_link (Mathieu Poirier)
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 73
mply ignoring them.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresig
Make sure we honor the errors in CATU device and abort the operation.
While at it, delay setting the etr_buf for the session until we are
sure that we are indeed enabling the ETR.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 19
Prepare the etb10 driver to return errors in enabling
the device.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v1:
- Rebased to the coresight/next
---
drivers/hwtracing/coresight/coresight-etb10.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions
Use the CLAIM tags to grab the device for self-hosted usage.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm3x.c | 16 +---
drivers/hwtracing/coresight/coresight-etm4x.c | 14 +++---
2 files changed, 24 insertions(+), 6
unaffected, except that some
unwanted traffic may be pushed to the paths (if the Trace-IDs
are not far enough), which is still fine and can be filtered
out while processing rather than silently blocking the data.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresig
iver,
but this makes the operation much simpler.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-priv.h | 7 +++
drivers/hwtracing/coresight/coresight.c | 86
include/linux/coresight.h| 20 ++
Use the CLAIM protocol to grab the ownership of the component when
in use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c
b/drivers
Use the CLAIM protocol to grab the ownership of the component.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-funnel.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight
Use CLAIM protocol to make sure the device is available for use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-dynamic-replicator.c | 23 +-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight
Use CLAIM tags to make sure the device is available for use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 22 +++---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 4
2 files changed, 23 insertions(+), 3
Add support for handling errors in enabling the component.
The ETM is enabled via cross call to owner CPU. Make
necessary changes to report the error back from the cross
call.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x.c | 39
also avoids turning the CATU on/off
during a sysfs read session.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 67 -
1 file changed, 43 insertions(+), 24 deletions(-)
diff --git a/drivers/hwtracing/coresight
Add support for reporting errors back from the SMP cross
function call for enabling ETM.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v1:
- Fix build break, missing ;. (Mathieu Poirier)
---
drivers/hwtracing/coresight/coresight-etm3x.c | 42
V1:
- Handle errors is enabling path and disable only the components
that were enabled in the iteration.
- Fix build break on arm32 (etm3x)
- Update commit description for "coresight: Add support for CLAIM tag protocol"
Suzuki K Poulose (14):
coresight: Handle failures in enabling
utland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/kernel/cpu_errata.c | 17 ++---
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/i
: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
Cc: # v4.9
Cc: Mark Rutland
Cc: Catalin Marinas
Reported-by: Will Deacon
Signed-off-by: Suzuki K Poulose
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/cachetype.h | 5 +
arch/arm64/kernel/cpu_errata
: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
Cc: # v4.14
Cc: Mark Rutland
Cc: Catalin Marinas
Reported-by: Will Deacon
Signed-off-by: Suzuki K Poulose
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/cache.h | 5 +
arch/arm64/kernel/cpu_errata.c | 6 ++
utland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/kernel/cpu_errata.c | 17 ++---
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/c
Hi Rahul,
On 04/07/18 17:57, Rahul Ramasubramanian wrote:
Measuring DDR bandwidth allows for an accurate measurement
of memory throughput achieved for a given workload. It also
breaks down the traffic measurement on a per DDR channel basis.
The commit description doesn't help much for someone
On 08/20/2018 04:25 PM, Kim Phillips wrote:
On Mon, 20 Aug 2018 15:36:47 +0100
Suzuki K Poulose wrote:
On 08/20/2018 03:22 PM, Kim Phillips wrote:
On Mon, 20 Aug 2018 11:03:03 +0100
Suzuki K Poulose wrote:
On 08/16/2018 08:28 PM, Mathieu Poirier wrote:
On Wed, 15 Aug 2018 at 09:28, Kim
On 08/20/2018 03:22 PM, Kim Phillips wrote:
On Mon, 20 Aug 2018 11:03:03 +0100
Suzuki K Poulose wrote:
On 08/16/2018 08:28 PM, Mathieu Poirier wrote:
On Wed, 15 Aug 2018 at 09:28, Kim Phillips wrote:
On Wed, 15 Aug 2018 10:39:13 +0100
Will Deacon wrote:
On Tue, Aug 14, 2018 at 01:42
On 08/16/2018 08:28 PM, Mathieu Poirier wrote:
On Wed, 15 Aug 2018 at 09:28, Kim Phillips wrote:
On Wed, 15 Aug 2018 10:39:13 +0100
Will Deacon wrote:
On Tue, Aug 14, 2018 at 01:42:27PM -0600, Mathieu Poirier wrote:
On Tue, 14 Aug 2018 at 11:09, Kim Phillips wrote:
The other thing that's
On 16/08/18 16:48, Mathieu Poirier wrote:
On Thu, Aug 16, 2018 at 04:13:03PM +0100, Suzuki K Poulose wrote:
Hi Mathieu,
The patch looks good to me. One minor nit below.
You have not included any comment - did you change your mind?
Sorry, yes I did. It was about folding the checks where
On 15/08/18 00:20, Mathieu Poirier wrote:
On Mon, Aug 06, 2018 at 02:41:50PM +0100, Suzuki K Poulose wrote:
Add support for the CLAIM tag protocol for negotiating the
device ownership with other agents trying to use the coresight
component (internal vs. external). The Coresight architecture
On 15/08/18 20:38, Mathieu Poirier wrote:
On Mon, Aug 06, 2018 at 02:41:48PM +0100, Suzuki K Poulose wrote:
Prepare the etb10 driver to return errors in enabling
the device.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etb10.c | 18
On 15/08/18 20:34, Mathieu Poirier wrote:
On Mon, Aug 06, 2018 at 02:41:47PM +0100, Suzuki K Poulose wrote:
Add support for reporting errors back from the SMP cross
function call for enabling ETM.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight
eak;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret)
+ return ret;
+
+ dev_dbg(drvdata->dev, "ETB enabled\n");
+ return 0;
+}
+
Looks good.
Reviewed-by: Suzuki K Poulose
pinlock, flags);
- if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
+ if (drvdata->mode == CS_MODE_SYSFS) {
etb_disable_hw(drvdata);
etb_dump_hw(drvdata);
etb_enable_hw(drvdata);
Looks good to me.
Reviewed-by : Suzuki K Poulose
On 15/08/18 20:22, Mathieu Poirier wrote:
On Mon, Aug 06, 2018 at 02:41:45PM +0100, Suzuki K Poulose wrote:
Prepare to handle errors in enabling the hardware and
report it back to the core driver.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight
Prepare to handle errors in enabling the hardware and
report it back to the core driver.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 71 +++--
1 file changed, 44 insertions(+), 27 deletions(-)
diff --git a
Use the CLAIM tags to grab the device for self-hosted usage.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm3x.c | 18 +++---
drivers/hwtracing/coresight/coresight-etm4x.c | 15 ---
2 files changed, 27 insertions(+), 6
Use the CLAIM protocol to grab the ownership of the component when
in use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c
b/drivers
Use CLAIM tags to make sure the device is available for use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 22 +++---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 4
2 files changed, 23 insertions(+), 3
recommends the
reservation of the bits in CLAIM tags for self-hosted and external
debug use. This patch implements the protocol for claiming
the devices before they are actually used.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-priv.h | 7
Make sure we honor the errors in CATU device and abort the operation.
While at it, delay setting the etr_buf for the session until we are
sure that we are indeed enabling the ETR.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 19
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