> From: Jason Gunthorpe
> Sent: Wednesday, October 30, 2024 12:05 AM
>
> On Tue, Oct 29, 2024 at 08:22:43AM +, Tian, Kevin wrote:
> > > From: Nicolin Chen
> > > Sent: Saturday, October 26, 2024 7:51 AM
> > >
> > > @@ -302,7 +
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> With the introduction of the new object and its infrastructure, update the
> doc and the vIOMMU graph to reflect that.
>
> Reviewed-by: Jason Gunthorpe
> Signed-off-by: Nicolin Chen
Reviewed-by: Kevin Tian
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> Add a vdevice_alloc op to the viommu mock_viommu_ops for the coverage
> of
> IOMMU_VIOMMU_TYPE_SELFTEST allocations. Then, add a vdevice_alloc
> TEST_F
> to cover the IOMMU_VDEVICE_ALLOC ioctl.
>
> Signed-off-by: Nicolin Chen
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> This per-vIOMMU cache_invalidate op is like the cache_invalidate_user op
> in struct iommu_domain_ops, but wider, supporting device cache (e.g. PCI
> ATC invaldiations).
>
> Reviewed-by: Jason Gunthorpe
> Signed-off-by: Nicolin
> From: Jason Gunthorpe
> Sent: Monday, October 28, 2024 10:17 PM
>
> > > to
> > > a Context Table. This virt_id helps IOMMU drivers to link the vID to a pID
> > > of the device against the physical IOMMU instance. This is essential for a
> > > vIOMMU-based invalidation, where the request contain
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> Implement the vIOMMU's cache_invalidate op for user space to invalidate
> the
> IOTLB entries, Device ATS and CD entries that are still cached by hardware.
>
> Add struct iommu_viommu_arm_smmuv3_invalidate defining invalidation
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> Similar to IOMMU_TEST_OP_MD_CHECK_IOTLB verifying a mock_domain's
> iotlb,
> IOMMU_TEST_OP_DEV_CHECK_CACHE will be used to verify a mock_dev's
> cache.
>
> Signed-off-by: Nicolin Chen
Reviewed-by: Kevin Tian
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> With a vIOMMU object, use space can flush any IOMMU related cache that
> can
> be directed via a vIOMMU object. It is similar to the
> IOMMU_HWPT_INVALIDATE
> uAPI, but can cover a wider range than IOTLB, e.g. device/desciprtor c
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> Add a viommu_cache test function to cover vIOMMU invalidations using the
> updated IOMMU_HWPT_INVALIDATE ioctl, which now allows passing in a
> vIOMMU
> via its hwpt_id field.
>
> Signed-off-by: Nicolin Chen
Reviewed-by: Kevin
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> Similar to the coverage of cache_invalidate_user for iotlb invalidation,
> add a device cache and a viommu_cache_invalidate function to test it out.
>
> Signed-off-by: Nicolin Chen
Reviewed-by: Kevin Tian
> From: Nicolin Chen
> Sent: Monday, October 28, 2024 6:49 AM
>
> On Sun, Oct 27, 2024 at 11:02:31PM +0800, Zhangfei Gao wrote:
> > On Sat, 26 Oct 2024 at 07:51, Nicolin Chen wrote:
> > > +/* Caller should xa_lock(&viommu->vdevs) to protect the return value
> */
> > > +struct device *iommufd_vio
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> From: Jason Gunthorpe
>
> The iommu_copy_struct_from_user_array helper can be used to copy a
> single
> entry from a user array which might not be efficient if the array is big.
>
> Add a new iommu_copy_struct_from_full_user_a
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> @@ -302,7 +302,9 @@ iommufd_viommu_alloc_hwpt_nested(struct
> iommufd_viommu *viommu, u32 flags,
> }
> hwpt->domain->owner = viommu->iommu_dev->ops;
>
> - if (WARN_ON_ONCE(hwpt->domain->type !=
> IOMMU_DOMAIN_NES
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> Add a new iommufd_viommu FIXTURE and setup it up with a vIOMMU object.
>
> Any new vIOMMU feature will be added as a TEST_F under that.
>
> Signed-off-by: Nicolin Chen
Reviewed-by: Kevin Tian
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> Add a new driver-type for ARM SMMUv3 to enum iommu_viommu_type.
> Implement
> an arm_vsmmu_alloc() with its viommu op
> arm_vsmmu_domain_alloc_nested(),
> to replace arm_smmu_domain_alloc_nesting(). As an initial step, copy the
>
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:51 AM
>
> +
> +/**
> + * struct iommu_vdevice_alloc - ioctl(IOMMU_VDEVICE_ALLOC)
> + * @size: sizeof(struct iommu_vdevice_alloc)
> + * @viommu_id: vIOMMU ID to associate with the virtual device
> + * @dev_id: The pyhsical device to allocat
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> Following the previous vIOMMU series, this adds another vDEVICE structure,
> representing the association from an iommufd_device to an
> iommufd_viommu.
> This gives the whole architecture a new "v" layer:
>
> __
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> Implement the viommu alloc/free functions to increase/reduce refcount of
> its dependent mock iommu device. User space can verify this loop via the
> IOMMU_VIOMMU_TYPE_SELFTEST.
>
> Signed-off-by: Nicolin Chen
Reviewed-by: Kev
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> For an iommu_dev that can unplug (so far only this selftest does so), the
> viommu->iommu_dev pointer has no guarantee of its life cycle after it is
> copied from the idev->dev->iommu->iommu_dev.
>
> Track the user count of the
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> A nested domain now can be allocated for a parent domain for a vIOMMU
> object. Rework the existing allocators to prepare for the latter case.
>
> Signed-off-by: Nicolin Chen
Reviewed-by: Kevin Tian
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> Use these inline helpers to shorten those container_of lines.
>
> Note that one of them goes back and forth between iommu_domain and
> mock_iommu_domain, which isn't necessary. So drop its container_of.
>
> Signed-off-by: Nicol
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> Now a vIOMMU holds a shareable nesting parent HWPT. So, it can act like
> that nesting parent HWPT to allocate a nested HWPT.
>
> Support that in the IOMMU_HWPT_ALLOC ioctl handler, and update its kdoc.
>
> Also, add an iommufd
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> Add a new ioctl for user space to do a vIOMMU allocation. It must be based
> on a nesting parent HWPT, so take its refcount.
>
> IOMMU driver wanting to support vIOMMUs must define its
> IOMMU_VIOMMU_TYPE_
> in the uAPI header a
> From: Nicolin Chen
> Sent: Saturday, October 26, 2024 7:50 AM
>
> + * @viommu_alloc: Allocate an iommufd_viommu on a physical IOMMU
> instance behind
> + *the @dev, as the set of virtualization resources
> shared/passed
> + *to user space IOMMU instance. And asso
> From: Jason Gunthorpe
> Sent: Friday, October 25, 2024 11:43 PM
>
> On Fri, Oct 25, 2024 at 08:34:05AM +, Tian, Kevin wrote:
> > > The vIOMMU object should be seen as a slice of a physical IOMMU
> instance
> > > that is passed to or shared with a VM. T
> From: Jason Gunthorpe
> Sent: Friday, October 25, 2024 11:24 PM
>
> On Fri, Oct 25, 2024 at 08:47:40AM +, Tian, Kevin wrote:
> > > From: Jason Gunthorpe
> > > Sent: Tuesday, October 22, 2024 9:16 PM
> > >
> > > On Tue, Oct 22, 2024 at 04:59
> From: Nicolin Chen
> Sent: Tuesday, October 22, 2024 8:20 AM
>
> Add a new driver-type for ARM SMMUv3 to enum iommu_viommu_type.
> Implement
> an arm_vsmmu_alloc() with its viommu op
> arm_vsmmu_domain_alloc_nested(),
> to replace arm_smmu_domain_alloc_nesting(). As an initial step, copy the
>
> From: Nicolin Chen
> Sent: Tuesday, October 22, 2024 8:20 AM
>
> With the introduction of the new object and its infrastructure, update the
> doc to reflect that and add a new graph.
>
> Reviewed-by: Jason Gunthorpe
> Signed-off-by: Nicolin Chen
Reviewed-by: Kevin Tian
> From: Nicolin Chen
> Sent: Tuesday, October 22, 2024 8:19 AM
> +
> + viommu->type = cmd->type;
> + viommu->ictx = ucmd->ictx;
> + viommu->hwpt = hwpt_paging;
> + /* Assume physical IOMMUs are unpluggable (the most likely case)
> */
> + viommu->iommu_dev = __iommu_get_iommu_de
> From: Nicolin Chen
> Sent: Tuesday, October 22, 2024 8:19 AM
>
> +static struct iommufd_hwpt_nested *
> +iommufd_hwpt_nested_alloc_for_viommu(struct iommufd_viommu
> *viommu,
> + const struct iommu_user_data *user_data)
probably "_for" can be skipped to reduce t
> From: Nicolin Chen
> Sent: Tuesday, October 22, 2024 8:19 AM
>
> Allow IOMMU driver to use a vIOMMU object that holds a nesting parent
> hwpt/domain to allocate a nested domain.
>
> Suggested-by: Jason Gunthorpe
> Signed-off-by: Nicolin Chen
Reviewed-by: Kevin Tian
> From: Nicolin Chen
> Sent: Tuesday, October 22, 2024 8:19 AM
>
> Add a new ioctl for user space to do a vIOMMU allocation. It must be based
> on a nesting parent HWPT, so take its refcount.
>
> If an IOMMU driver supports a driver-managed vIOMMU object, it must
> define
why highlight 'driver-
> From: Jason Gunthorpe
> Sent: Tuesday, October 22, 2024 9:16 PM
>
> On Tue, Oct 22, 2024 at 04:59:07PM +0800, Baolu Lu wrote:
>
> > Is it feasible to make vIOMMU object more generic, rather than strictly
> > tying it to nested translation? For example, a normal paging domain that
> > translate
> From: Nicolin Chen
> Sent: Tuesday, October 22, 2024 8:19 AM
>
> To support driver-allocated vIOMMU objects, it's suggested to call the
> allocator helper in IOMMU dirvers. However, there is no guarantee that
> drivers will all use it and allocate objects properly.
>
> Add a helper for iommufd
> From: Nicolin Chen
> Sent: Tuesday, October 22, 2024 8:19 AM
>
> Prepare for an embedded structure design for driver-level iommufd_viommu
> objects:
> // include/linux/iommufd.h
> struct iommufd_viommu {
> struct iommufd_object obj;
>
> };
>
> // Some IOMMU
> From: Nicolin Chen
> Sent: Tuesday, October 22, 2024 8:19 AM
>
> This series introduces a new vIOMMU infrastructure and related ioctls.
>
> IOMMUFD has been using the HWPT infrastructure for all cases, including a
> nested IO page table support. Yet, there're limitations for an HWPT-based
> st
> From: Nicolin Chen
> Sent: Friday, September 27, 2024 9:26 AM
>
> On Fri, Sep 27, 2024 at 12:43:16AM +, Tian, Kevin wrote:
> > > From: Nicolin Chen
> > > Sent: Friday, September 27, 2024 4:11 AM
> > >
> > > On Thu, Sep 26, 2024 at 04:50:46PM
> From: Nicolin Chen
> Sent: Friday, September 27, 2024 4:11 AM
>
> On Thu, Sep 26, 2024 at 04:50:46PM +0800, Yi Liu wrote:
> > On 2024/8/28 00:59, Nicolin Chen wrote:
> > > Now a VIOMMU can wrap a shareable nested parent HWPT. So, it can act
> like
> > > a nested parent HWPT to allocate a nested
> From: Jason Gunthorpe
> Sent: Saturday, September 14, 2024 10:51 PM
>
> On Fri, Sep 13, 2024 at 02:33:59AM +, Tian, Kevin wrote:
> > > From: Jason Gunthorpe
> > > Sent: Thursday, September 12, 2024 7:08 AM
> > >
> > > On Wed, Sep
> From: Jason Gunthorpe
> Sent: Thursday, September 12, 2024 7:08 AM
>
> On Wed, Sep 11, 2024 at 08:13:01AM +, Tian, Kevin wrote:
>
> > Probably there is a good reason e.g. for simplification or better
> > aligned with hw accel stuff. But it's not explained c
> From: Baolu Lu
> Sent: Wednesday, September 11, 2024 3:51 PM
>
> On 2024/9/11 15:20, Nicolin Chen wrote:
> > On Wed, Sep 11, 2024 at 06:25:16AM +, Tian, Kevin wrote:
> >>> From: Jason Gunthorpe
> >>> Sent: Friday, September 6, 2024 2:22 AM
>
> From: Nicolin Chen
> Sent: Wednesday, September 11, 2024 3:21 PM
>
> On Wed, Sep 11, 2024 at 06:25:16AM +, Tian, Kevin wrote:
> > > From: Jason Gunthorpe
> > > Sent: Friday, September 6, 2024 2:22 AM
> > >
> > > On Thu, Sep 05, 2024 at 11:0
> From: Nicolin Chen
> Sent: Wednesday, September 11, 2024 3:41 PM
>
> On Wed, Sep 11, 2024 at 07:18:10AM +, Tian, Kevin wrote:
> > > From: Nicolin Chen
> > > Sent: Wednesday, September 11, 2024 3:08 PM
> > >
> > > On Wed, Sep 11, 2024 at 06:
> From: Nicolin Chen
> Sent: Wednesday, September 11, 2024 3:12 PM
>
> On Wed, Sep 11, 2024 at 06:19:10AM +, Tian, Kevin wrote:
> > > From: Nicolin Chen
> > > Sent: Friday, September 6, 2024 4:15 AM
> > >
> > > On Thu, Sep 05, 2024 at 02:43:2
> From: Nicolin Chen
> Sent: Wednesday, September 11, 2024 3:08 PM
>
> On Wed, Sep 11, 2024 at 06:12:21AM +, Tian, Kevin wrote:
> > > From: Nicolin Chen
> > > Sent: Wednesday, August 28, 2024 1:00 AM
> > >
> > [...]
> > > On a multi-I
> From: Jason Gunthorpe
> Sent: Friday, September 6, 2024 2:22 AM
>
> On Thu, Sep 05, 2024 at 11:00:49AM -0700, Nicolin Chen wrote:
> > On Thu, Sep 05, 2024 at 01:20:39PM -0300, Jason Gunthorpe wrote:
> > > On Tue, Aug 27, 2024 at 09:59:54AM -0700, Nicolin Chen wrote:
> > >
> > > > +static int ar
> From: Nicolin Chen
> Sent: Friday, September 6, 2024 4:15 AM
>
> On Thu, Sep 05, 2024 at 02:43:26PM -0300, Jason Gunthorpe wrote:
> > On Thu, Sep 05, 2024 at 10:37:45AM -0700, Nicolin Chen wrote:
> > > That being said, if we have a clear picture that in the long term
> > > we would extend it to
> From: Nicolin Chen
> Sent: Wednesday, August 28, 2024 1:00 AM
>
[...]
> On a multi-IOMMU system, the VIOMMU object can be instanced to the
> number
> of vIOMMUs in a guest VM, while holding the same parent HWPT to share
> the
Is there restriction that multiple vIOMMU objects can be only create
> From: ank...@nvidia.com
> Sent: Friday, February 16, 2024 11:01 AM
>
> From: Ankit Agrawal
>
> NVIDIA's upcoming Grace Hopper Superchip provides a PCI-like device
> for the on-chip GPU that is the logical OS representation of the
> internal proprietary chip-to-chip cache coherent interconnect
> From: Ankit Agrawal
> Sent: Thursday, February 8, 2024 3:13 PM
> >> > + * Determine how many bytes to be actually read from the
> >> > device memory.
> >> > + * Read request beyond the actual device memory size is
> >> > filled with ~0,
> >> > + * while those beyond the actual reported
> From: ank...@nvidia.com
> Sent: Tuesday, February 6, 2024 7:01 AM
>
> Note that the usemem memory is added by the VM Nvidia device driver [5]
> to the VM kernel as memblocks. Hence make the usable memory size
> memblock
> aligned.
Is memblock size defined in spec or purely a guest implementati
> From: ank...@nvidia.com
> Sent: Tuesday, February 6, 2024 7:01 AM
>
> From: Ankit Agrawal
>
> do_io_rw() is used to read/write to the device MMIO. The grace hopper
> VFIO PCI variant driver require this functionality to read/write to
> its memory.
>
> Rename this as vfio_pci_core functions a
> From: ank...@nvidia.com
> Sent: Tuesday, February 6, 2024 7:01 AM
>
> From: Ankit Agrawal
>
> range_intesect_range determines an overlap between two ranges. If an
s/intesect/intersect/
> overlap, the helper function returns the overlapping offset and size.
>
> The VFIO PCI variant driver e
> From: Arnd Bergmann
> Sent: Tuesday, January 9, 2024 3:57 PM
>
> From: Arnd Bergmann
>
> The new vfio-virtio driver already has a dependency on
> VIRTIO_PCI_ADMIN_LEGACY,
> but that is a bool symbol and allows vfio-virtio to be built-in even if
> virtio-pci itself is a loadable module. This l
> From: Jason Gunthorpe
> Sent: Wednesday, April 7, 2021 8:21 PM
>
> On Wed, Apr 07, 2021 at 02:08:33AM +, Tian, Kevin wrote:
>
> > > Because if you don't then we enter insane world where a PASID is being
> > > created under /dev/ioasid but it
> From: Jason Gunthorpe
> Sent: Tuesday, April 6, 2021 8:43 PM
>
> On Tue, Apr 06, 2021 at 09:35:17AM +0800, Jason Wang wrote:
>
> > > VFIO and VDPA has no buisness having map/unmap interfaces once we
> have
> > > /dev/ioasid. That all belongs in the iosaid side.
> > >
> > > I know they have thos
> From: Jason Gunthorpe
> Sent: Tuesday, April 6, 2021 8:21 PM
>
> On Tue, Apr 06, 2021 at 01:02:05AM +, Tian, Kevin wrote:
> > > From: Jason Gunthorpe
> > > Sent: Tuesday, April 6, 2021 7:40 AM
> > >
> > > On Fri, Apr 02, 2021 at 07:58:02AM
> From: Jason Gunthorpe
> Sent: Tuesday, April 6, 2021 8:35 PM
>
> On Tue, Apr 06, 2021 at 01:27:15AM +, Tian, Kevin wrote:
> >
> > and here is one example why using existing VFIO/VDPA interface makes
> > sense. say dev1 (w/ sva) and dev2 (w/o sva) are placed
> From: Tian, Kevin
> Sent: Tuesday, April 6, 2021 9:02 AM
>
> > From: Jason Gunthorpe
> > Sent: Tuesday, April 6, 2021 7:40 AM
> >
> > On Fri, Apr 02, 2021 at 07:58:02AM +, Tian, Kevin wrote:
> > > > From: Jason Gunthorpe
> > > > Sen
> From: Jason Gunthorpe
> Sent: Tuesday, April 6, 2021 7:43 AM
>
> On Fri, Apr 02, 2021 at 08:22:28AM +, Tian, Kevin wrote:
> > > From: Jason Gunthorpe
> > > Sent: Tuesday, March 30, 2021 9:29 PM
> > >
> > > >
> > > > First,
> From: Jason Gunthorpe
> Sent: Tuesday, April 6, 2021 7:40 AM
>
> On Fri, Apr 02, 2021 at 07:58:02AM +, Tian, Kevin wrote:
> > > From: Jason Gunthorpe
> > > Sent: Thursday, April 1, 2021 9:47 PM
> > >
> > > On Thu, Apr 01, 2021 at 01:43:36
> From: Jason Gunthorpe
> Sent: Tuesday, April 6, 2021 7:35 AM
>
> On Fri, Apr 02, 2021 at 07:30:23AM +, Tian, Kevin wrote:
> > > From: Jason Gunthorpe
> > > Sent: Friday, April 2, 2021 12:04 AM
> > >
> > > On Thu, Apr 01, 2021 at 02:08:17P
> From: Tian, Kevin
> Sent: Friday, April 2, 2021 3:58 PM
>
> > From: Jason Gunthorpe
> > Sent: Thursday, April 1, 2021 9:47 PM
> >
> > On Thu, Apr 01, 2021 at 01:43:36PM +, Liu, Yi L wrote:
> > > > From: Jason Gunthorpe
> > > > Sen
> From: Jason Gunthorpe
> Sent: Tuesday, March 30, 2021 9:29 PM
>
> >
> > First, userspace may use ioasid in a non-SVA scenario where ioasid is
> > bound to specific security context (e.g. a control vq in vDPA) instead of
> > tying to mm. In this case there is no pgtable binding initiated from us
> From: Jason Gunthorpe
> Sent: Thursday, April 1, 2021 9:47 PM
>
> On Thu, Apr 01, 2021 at 01:43:36PM +, Liu, Yi L wrote:
> > > From: Jason Gunthorpe
> > > Sent: Thursday, April 1, 2021 9:16 PM
> > >
> > > On Thu, Apr 01, 2021 at 01:10:48PM +, Liu, Yi L wrote:
> > > > > From: Jason Gunt
> From: Jason Gunthorpe
> Sent: Friday, April 2, 2021 12:04 AM
>
> On Thu, Apr 01, 2021 at 02:08:17PM +, Liu, Yi L wrote:
>
> > DMA page faults are delivered to root-complex via page request message
> and
> > it is per-device according to PCIe spec. Page request handling flow is:
> >
> > 1)
> From: Tian, Kevin
> Sent: Tuesday, March 30, 2021 10:24 AM
>
> > From: Jason Gunthorpe
> > Sent: Tuesday, March 30, 2021 12:32 AM
> > > In terms of usage for guest SVA, an ioasid_set is mostly tied to a host
> > > mm,
> > > the use case is as th
> From: Jason Gunthorpe
> Sent: Tuesday, March 30, 2021 12:32 AM
> > In terms of usage for guest SVA, an ioasid_set is mostly tied to a host mm,
> > the use case is as the following:
>
> From that doc:
>
> It is imperative to enforce
> VM-IOASID ownership such that a malicious guest cannot t
> From: Jason Gunthorpe
> Sent: Tuesday, March 30, 2021 12:32 AM
>
> On Wed, Mar 24, 2021 at 12:05:28PM -0700, Jacob Pan wrote:
>
> > > IMHO a use created PASID is either bound to a mm (current) at creation
> > > time, or it will never be bound to a mm and its page table is under
> > > user cont
> From: Shenming Lu
> Sent: Thursday, March 18, 2021 7:54 PM
>
> On 2021/3/18 17:07, Tian, Kevin wrote:
> >> From: Shenming Lu
> >> Sent: Thursday, March 18, 2021 3:53 PM
> >>
> >> On 2021/2/4 14:52, Tian, Kevin wrote:>>> In reality,
> From: Shenming Lu
> Sent: Thursday, March 18, 2021 3:53 PM
>
> On 2021/2/4 14:52, Tian, Kevin wrote:>>> In reality, many
> >>> devices allow I/O faulting only in selective contexts. However, there
> >>> is no standard way (e.g. PCISIG) for the devic
> From: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
>
> > -Original Message-
> > From: Tian, Kevin [mailto:kevin.t...@intel.com]
> > Sent: Thursday, March 18, 2021 4:27 PM
> > To: Longpeng (Mike, Cloud Infrastructure Service Produc
> From: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
>
>
> > -Original Message-----
> > From: Tian, Kevin [mailto:kevin.t...@intel.com]
> > Sent: Thursday, March 18, 2021 4:27 PM
> > To: Longpeng (Mike, Cloud Infrastructure Service Pro
> From: iommu On Behalf Of
> Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> > 2. Consider ensuring that the problem is not somehow related to queued
> > invalidations. Try to use __iommu_flush_iotlb() instead of qi_flush_iotlb().
> >
>
> I tried to force to use __iommu_flush_iot
> From: Jacob Pan
> Sent: Thursday, March 4, 2021 2:29 AM
>
> Hi Vivek,
>
> On Fri, 15 Jan 2021 17:43:39 +0530, Vivek Gautam
> wrote:
>
> > From: Jean-Philippe Brucker
> >
> > Add support for tlb invalidation ops that can send invalidation
> > requests to back-end virtio-iommu when stage-1 pa
> From: Jacob Pan
> Sent: Saturday, February 20, 2021 1:09 AM
>
> Hi Kevin,
>
> On Fri, 19 Feb 2021 06:19:04 +, "Tian, Kevin"
> wrote:
>
> > > From: Jacob Pan
> > > Sent: Friday, February 19, 2021 5:31 AM
> > >
> > &g
> From: Jacob Pan
> Sent: Friday, February 19, 2021 5:31 AM
>
> Write protect bit, when set, inhibits supervisor writes to the read-only
> pages. In guest supervisor shared virtual addressing (SVA), write-protect
> should be honored upon guest bind supervisor PASID request.
>
> This patch extend
> From: Jason Gunthorpe
> Sent: Wednesday, February 17, 2021 5:33 AM
>
> On Tue, Feb 16, 2021 at 12:04:55PM -0700, Dave Jiang wrote:
>
> > > > + return remap_pfn_range(vma, vma->vm_start, pgoff, req_size,
> pg_prot);
> > > Nothing validated req_size - did you copy this from the Intel RDMA
Hi, Max,
> From: Max Gurtovoy
> Sent: Tuesday, February 2, 2021 12:28 AM
>
> Hi Alex and Cornelia,
>
> This series split the vfio_pci driver into 2 parts: pci driver and a
> subsystem driver that will also be library of code. The pci driver,
> vfio_pci.ko will be used as before and it will bind
> From: Jean-Philippe Brucker
> Sent: Friday, February 5, 2021 6:37 PM
>
> Hi,
>
> On Thu, Feb 04, 2021 at 06:52:10AM +, Tian, Kevin wrote:
> > > >>> The static pinning and mapping problem in VFIO and possible
> solutions
> > > >>>
> From: Shenming Lu
> Sent: Tuesday, February 2, 2021 2:42 PM
>
> On 2021/2/1 15:56, Tian, Kevin wrote:
> >> From: Alex Williamson
> >> Sent: Saturday, January 30, 2021 6:58 AM
> >>
> >> On Mon, 25 Jan 2021 17:03:58 +0800
> >> Shenming
> From: Lu Baolu
> Sent: Wednesday, February 3, 2021 5:33 PM
>
> From: Yian Chen
>
> Starting from Intel VT-d v3.2, Intel platform BIOS can provide a new SATC
> table structure. SATC table lists a set of SoC integrated devices that
> require ATC to work (VT-d specification v3.2, section 8.8). Fu
> From: Jason Gunthorpe
> Sent: Tuesday, February 2, 2021 7:44 AM
>
> On Fri, Jan 29, 2021 at 10:09:03AM +, Tian, Kevin wrote:
> > > SVA is not doom to work with IO page fault only. If we have SVA+pin,
> > > we would get both sharing address and stable I/O la
> From: Alex Williamson
> Sent: Saturday, January 30, 2021 6:58 AM
>
> On Mon, 25 Jan 2021 17:03:58 +0800
> Shenming Lu wrote:
>
> > Hi,
> >
> > The static pinning and mapping problem in VFIO and possible solutions
> > have been discussed a lot [1, 2]. One of the solutions is to add I/O
> > pag
> From: Lu Baolu
> Sent: Monday, January 25, 2021 2:29 PM
>
> Hi Kevin,
>
> On 2021/1/22 14:38, Tian, Kevin wrote:
> >> From: Lu Baolu
> >> Sent: Thursday, January 21, 2021 9:45 AM
> >>
> >> So that the uses could get chances to
> From: Lu Baolu
> Sent: Thursday, January 21, 2021 9:45 AM
>
> So that the uses could get chances to know what happened.
>
> Suggested-by: Ashok Raj
> Signed-off-by: Lu Baolu
> ---
> drivers/iommu/intel/svm.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git
> From: Lu Baolu
> Sent: Thursday, January 14, 2021 9:30 AM
>
> The pci_subdevice_msi_create_irq_domain() should fail if the underlying
> platform is not able to support IMS (Interrupt Message Storage). Otherwise,
> the isolation of interrupt is not guaranteed.
>
> For x86, IMS is only supported
> From: Leon Romanovsky
> Sent: Tuesday, January 12, 2021 1:53 PM
>
> On Tue, Jan 12, 2021 at 01:17:11PM +0800, Lu Baolu wrote:
> > Hi,
> >
> > On 1/7/21 3:16 PM, Leon Romanovsky wrote:
> > > On Thu, Jan 07, 2021 at 06:55:16AM +, Tian, Kevin
> From: David Woodhouse
> Sent: Thursday, December 10, 2020 4:23 PM
>
> On Thu, 2020-12-10 at 08:46 +0800, Lu Baolu wrote:
> > +/*
> > + * We want to figure out which context we are running in. But the
> hardware
> > + * does not introduce a reliable way (instruction, CPUID leaf, MSR,
> whatever)
> From: Leon Romanovsky
> Sent: Thursday, January 7, 2021 2:09 PM
>
> On Thu, Jan 07, 2021 at 02:04:29AM +, Tian, Kevin wrote:
> > > From: Leon Romanovsky
> > > Sent: Thursday, January 7, 2021 12:02 AM
> > >
> > > On Wed, Jan 06, 2021 at 11:
> From: Leon Romanovsky
> Sent: Thursday, January 7, 2021 12:02 AM
>
> On Wed, Jan 06, 2021 at 11:23:39AM -0400, Jason Gunthorpe wrote:
> > On Wed, Jan 06, 2021 at 12:40:17PM +0200, Leon Romanovsky wrote:
> >
> > > I asked what will you do when QEMU will gain needed functionality?
> > > Will you
> From: Jason Gunthorpe
> Sent: Tuesday, November 17, 2020 2:03 AM
>
> On Mon, Nov 16, 2020 at 06:56:33PM +0100, Thomas Gleixner wrote:
> > On Mon, Nov 16 2020 at 11:46, Jason Gunthorpe wrote:
> >
> > > On Mon, Nov 16, 2020 at 07:31:49AM +, Tian, Kevin wro
> From: Raj, Ashok
> Sent: Monday, November 16, 2020 8:23 AM
>
> On Sun, Nov 15, 2020 at 11:11:27PM +0100, Thomas Gleixner wrote:
> > On Sun, Nov 15 2020 at 11:31, Ashok Raj wrote:
> > > On Sun, Nov 15, 2020 at 12:26:22PM +0100, Thomas Gleixner wrote:
> > >> > opt-in by device or kernel? The way
> From: Thomas Gleixner
> Sent: Friday, November 13, 2020 6:43 AM
>
> On Thu, Nov 12 2020 at 14:32, Konrad Rzeszutek Wilk wrote:
> >> 4. Using CPUID to detect running as guest. But as Thomas pointed out, this
> >> approach is less reliable as not all hypervisors do this way.
> >
> > Is that truly
> From: Raj, Ashok
> Sent: Tuesday, November 10, 2020 10:13 PM
>
> Thomas,
>
> With all these interrupt message storms ;-), I'm missing how to move
> towards
> an end goal.
>
> On Tue, Nov 10, 2020 at 11:27:29AM +0100, Thomas Gleixner wrote:
> > Ashok,
> >
> > On Mon, Nov 09 2020 at 21:14, Asho
> From: Jason Gunthorpe
> Sent: Tuesday, November 10, 2020 10:19 PM
> On Mon, Nov 09, 2020 at 09:14:12PM -0800, Raj, Ashok wrote:
>
> > was used for interrupt message storage (on the wire they follow the
> > same format), and also to ensure interoperability of devices
> > supporting IMS across CP
> From: Jason Gunthorpe
> Sent: Tuesday, November 10, 2020 10:24 PM
>
> On Tue, Nov 10, 2020 at 06:13:23AM -0800, Raj, Ashok wrote:
>
> > This isn't just for idxd, as I mentioned earlier, there are vendors other
> > than Intel already working on this. In all cases the need for guest direct
> > m
> From: Raj, Ashok
> Sent: Monday, November 9, 2020 7:59 AM
>
> Hi Thomas,
>
> [-] Jing, She isn't working at Intel anymore.
>
> Now this is getting compiled as a book :-).. Thanks a ton!
>
> One question on the hypercall case that isn't immediately
> clear to me.
>
> On Sun, Nov 08, 2020 at
> From: Jason Gunthorpe
> Sent: Monday, November 9, 2020 7:24 AM
>
> On Sun, Nov 08, 2020 at 07:47:24PM +0100, Thomas Gleixner wrote:
> >
> > That means the guest needs a way to ask the hypervisor for a proper
> > translation, i.e. a hypercall. Now where to do that? Looking at the
> > above remap
> -Original Message-
> From: Thomas Gleixner
> Sent: Saturday, November 7, 2020 8:32 AM
> To: Tian, Kevin ; Jason Gunthorpe
> Cc: Jiang, Dave ; Bjorn Helgaas ;
> vk...@kernel.org; Dey, Megha ; m...@kernel.org;
> bhelg...@google.com; alex.william...@redhat.com; P
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