> -Original Mail-
> Sender : Alan Stern
> Time : 2020/7/24 0:39
> Receiver : Alex Williamson
> CC : Weitao Wang(BJ-RD) ; Greg KH
> ; WeitaoWang-oc
> ; mathias.ny...@linux.intel.com;
> ulf.hans...@linaro.org; vk...@kernel.org; hsleste...@gmail.com;
> linux-...@vger.kernel.org; linux-kerne
kernel that the TSC is usable, so it
will select it over HPET. The effect of this is that reading time stamps (from
kernel
or userspace) will be faster and more efficient.
Signed-off-by: TimGuo
---
arch/x86/kernel/cpu/centaur.c | 4
drivers/acpi/processor_idle.c | 1 +
2 files changed, 5
>From 812522018b0f1d9501fbdda4018be9a6fc9c21bf Mon Sep 17 00:00:00 2001
From: TimGuo
Date: Wed, 10 Jan 2018 18:16:33 +0800
Subject: [PATCH] x86/centaur: Mark TSC invariant
Centaur CPU has a constant frequency TSC and that TSC
does not stop in C-States. But because the flags are not set for t
Unuseful cache flush operations which will be executed by ucode when entering
C3 will
cause larger C3 enter latency. And the bus master disable operation is not need
for
centaur platforms.
Signed-off-by: TimGuo
---
arch/x86/kernel/acpi/cstate.c | 12
1 file changed, 12 insertions
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