[...]
Hi Mathieu
On 16/08/24 20:06, Mathieu Poirier wrote:
>>> +/*
>>> + * Attach to a running M4 remote processor (IPC-only mode)
>>> + *
>>> + * The remote processor is already booted, so there is no need to issue any
>>> + * TI-SCI commands to boot the M4 core. This callback is used only in
>
Hi Colin King,
On Thu, 25 Mar 2021 17:45:14 +, Colin King wrote:
> The variable timeo is being initialized with a value that is never read
> and it is being updated later with a new value. The initialization is
> redundant and can be removed.
Fixed up $subject prefix to match existing conven
Hi.
On 4/8/21 6:26 PM, Li Huafei wrote:
> pm_runtime_get_sync will increment pm usage counter even it failed.
> Forgetting to putting operation will result in reference leak here. Fix
> it by replacing it with pm_runtime_resume_and_get to keep usage counter
> balanced.
>
> Reported-by: Hulk Robot
Hi,
On 4/7/21 11:57 AM, Tony Lindgren wrote:
> * Vignesh Raghavendra [210407 06:20]:
>> Do we need a Fixes: tag to enable stable backports?
>
> Well pm_runtime_resume_and_get() was introduced quite recently, and
> we already handle the error and bail out. And likely after a
runtime
> PM counter on error.
>
> Signed-off-by: Dinghao Liu
> ---
Do we need a Fixes: tag to enable stable backports?
Reviewed-by: Vignesh Raghavendra
> drivers/i2c/busses/i2c-omap.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers
On 4/6/21 2:17 PM, Michael Walle wrote:
> Hi,
>
> Am 2021-04-06 09:56, schrieb Vignesh Raghavendra:
>> Hi,
>>
>> On 3/18/21 2:54 PM, Michael Walle wrote:
>>> Add support to show the name and JEDEC identifier as well as to dump the
>>> SFDP table. N
Hi,
On 3/18/21 2:54 PM, Michael Walle wrote:
> Add support to show the name and JEDEC identifier as well as to dump the
> SFDP table. Not all flashes list their SFDP table contents in their
> datasheet. So having that is useful. It might also be helpful in bug
> reports from users.
>
Sorry for t
On 3/29/21 11:52 PM, Pratyush Yadav wrote:
>>> + cdns,fifo-depth:
>>> +description:
>>> + Size of the data FIFO in words.
>>> +$ref: "/schemas/types.yaml#/definitions/uint32"
>>> +enum: [ 128, 256 ]
>>> +default: 128
>>> +
>>> + cdns,fifo-width:
>>> +$ref: /schemas/typ
On 3/26/21 6:30 PM, Pratyush Yadav wrote:
> The TI specific compatible should be followed by the generic
> "cdns,qspi-nor" compatible.
>
> Signed-off-by: Pratyush Yadav
> ---
Reviewed-by: Vignesh Raghavendra
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 +-
&g
On 3/26/21 6:30 PM, Pratyush Yadav wrote:
> The TI specific compatible should be followed by the generic
> "cdns,qspi-nor" compatible.
>
> Signed-off-by: Pratyush Yadav
> ---
Reviewed-by: Vignesh Raghavendra
> arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi |
On 3/26/21 6:30 PM, Pratyush Yadav wrote:
> The TI specific compatible should be followed by the generic
> "cdns,qspi-nor" compatible.
>
> Signed-off-by: Pratyush Yadav
> ---
Reviewed-by: Vignesh Raghavendra
> arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
Both AM64 EVM and SK have a 512Mb S28HS512T Octal SPI NOR flash.
Add DT node for the same.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Pratyush Yadav
---
Boot logs:
https://pastebin.ubuntu.com/p/VsMmyWk5SX/
https://pastebin.ubuntu.com/p/KFcMwSGxr5/
Resend:
Rebase onto latest -next
There
AM64 SoC has a single Octal SPI (OSPI) instance under Flash SubSystem
(FSS). Add DT entry for the same.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Pratyush Yadav
---
Rebase onto latest k3-dts-next
v1: lore.kernel.org/r/20210309130514.11740-1-vigne...@ti.com
arch/arm64/boot/dts/ti/k3
k3-am642-sk.dts file.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Lokesh Vutla
---
Rebase onto latest k3-dts-next:
v1: lore.kernel.org/r/20210309130708.12391-1-vigne...@ti.com
Do note that dtbs_check warns about having the bindings converted to
YAML which is in my future TODO list.
arch
On 3/17/21 2:35 PM, Pratyush Yadav wrote:
> On 17/03/21 06:09AM, tudor.amba...@microchip.com wrote:
>> On 3/15/21 8:23 AM, Vignesh Raghavendra wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>>> content is safe
>>>
Both AM64 EVM and SK have a 512Mb S28HS512T Octal SPI NOR flash.
Add DT node for the same.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Pratyush Yadav
---
Boot logs:
https://pastebin.ubuntu.com/p/mNG7ryv3w6/
https://pastebin.ubuntu.com/p/TZf9ZwSqqM/
Resend:
Rebase onto latest -next
There
AM64 SoC has a single Octal SPI (OSPI) instance under Flash SubSystem
(FSS). Add DT entry for the same.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Pratyush Yadav
---
Resend:
Rebase onto latest -next
v1: lore.kernel.org/r/20210309130514.11740-1-vigne...@ti.com
arch/arm64/boot/dts/ti/k3
On 3/9/21 12:58 PM, tudor.amba...@microchip.com wrote:
> On 3/8/21 7:28 PM, Vignesh Raghavendra wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> On 3/6/21 3:20 PM, Tudor Ambarus wrote:
>>> It m
.com/KSPP/linux/issues/115
> Signed-off-by: Gustavo A. R. Silva
> ---
Acked-by: Vignesh Raghavendra
Miquel,
Feel free to queue this via mtd/next
Regards
Vignesh
[...]
Hi Nishanth
On 3/9/21 6:35 PM, Vignesh Raghavendra wrote:
> AM64 SoC has a single Octal SPI (OSPI) instance under Flash SubSystem
> (FSS). Add DT entry for the same.
>
> Signed-off-by: Vignesh Raghavendra
> ---
Please ignore the series. I see some instabilities in my testing
On 3/1/21 11:35 AM, Aswath Govindraju wrote:
> Add pinmux details and device tree node for the EEPROM attached to SPI0
> module in main domain.
>
> Signed-off-by: Aswath Govindraju
> ---
Reviewed-by: Vignesh Raghavendra
Regards
Vignesh
>
> This patc
k3-am642-sk.dts file.
Signed-off-by: Vignesh Raghavendra
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 17 +
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 5 +
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 4
3 files changed, 26 insertions(+)
diff --git a/arch/arm64/boot
Both AM64 EVM and SK have a 512Mb S28HS512T Octal SPI NOR flash.
Add DT node for the same.
Signed-off-by: Vignesh Raghavendra
---
Bootlog:
SK: https://pastebin.ubuntu.com/p/gvxg7cFrXH/
EVM: https://pastebin.ubuntu.com/p/jb39GqkB78/
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 36
AM64 SoC has a single Octal SPI (OSPI) instance under Flash SubSystem
(FSS). Add DT entry for the same.
Signed-off-by: Vignesh Raghavendra
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 25
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64
On 3/6/21 3:20 PM, Tudor Ambarus wrote:
> It makes the core file a bit smaller and provides better separation
> between the Software Write Protection features and the core logic.
> All the next generic software write protection features (e.g. Individual
> Block Protection) will reside in swp.c.
l argument follows the OTPLOCK style.
>
> Signed-off-by: Michael Walle
> ---
Acked-by: Vignesh Raghavendra
[...]
Regards
Vignesh
On 3/8/21 2:53 PM, Tudor Ambarus wrote:
> It's already been the case for some time that Michael and Pratyush
> are reviewing SPI NOR patches. Update MAINTAINERS to reflect reality.
>
> Signed-off-by: Tudor Ambarus
> ---
Acked-by: Vignesh Raghavendra
> Michael, Pra
dor may be able
to fix it locally while applying.
Apart from that
Reviewed-by: Vignesh Raghavendra
Regards
Vignesh
> drivers/mtd/spi-nor/controllers/intel-spi.c | 1 -
> drivers/mtd/spi-nor/controllers/intel-spi.h | 2 +-
> include/linux/mfd/lpc_ich.h
On 3/5/21 9:09 PM, Pratyush Yadav wrote:
> TI J7200 has the Cadence OSPI controller for interfacing with OSPI
> flashes. Add its node to allow using SPI flashes.
>
> Signed-off-by: Pratyush Yadav
> ---
Reviewed-by: Vignesh Raghavendra
>
> Notes:
> Changes in
D-8D-8D mode should be at least twice as fast as
> 1S-1S-8S mode.
>
> Signed-off-by: Pratyush Yadav
> ---
>
Reviewed-by: Vignesh Raghavendra
> Notes:
> No changes in v2.
>
> arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++--
> 1 file changed, 2 inser
D-8D-8D mode should be at least twice as fast as
> 1S-1S-8S mode.
>
> Signed-off-by: Pratyush Yadav
> ---
>
Reviewed-by: Vignesh Raghavendra
> Notes:
> No changes in v2.
>
> arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++--
> 1 file changed, 2 insertions
emens/meta-iot2050
> Signed-off-by: Jan Kiszka
Reviewed-by: Vignesh Raghavendra
Few minor comments below:
[...]
> +
> +&mcu_i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_i2c0_pins_default>;
> + clock-frequency = <40>;
On 2/12/21 1:02 AM, Jan Kiszka wrote:
> From: Jan Kiszka
>
> These boards are based on AM6528 GP and AM6548 HS SOCs.
>
> Signed-off-by: Jan Kiszka
Reviewed-by: Vignesh Raghavendra
> ---
> Documentation/devicetree/bindings/arm/ti/k3.yaml | 2 ++
> 1 fi
On 3/2/21 9:49 PM, Michael Walle wrote:
> Am 2021-03-02 16:30, schrieb Vignesh Raghavendra:
>> Hi,
>>
>> On 3/2/21 4:39 PM, Michael Walle wrote:
>>> This may sound like a contradiction but some SPI-NOR flashes really
>>> support erasing their OTP region
Hi,
On 3/2/21 4:39 PM, Michael Walle wrote:
> This may sound like a contradiction but some SPI-NOR flashes really
> support erasing their OTP region until it is finally locked. Having the
> possibility to erase an OTP region might come in handy during
> development.
>
> The ioctl argument follows
On 3/2/21 1:28 AM, Pratyush Yadav wrote:
> +
> + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
> + pinctrl-single,pins = <
> + J721E_WKUP_IOPAD(0x, PIN_OUTPUT, 0) /*
> MCU_OSPI0_CLK */
> + J721E_WKUP_IOPAD(0x002c, PIN_OUTP
Hi,
On 2/12/21 8:10 PM, Vladimir Oltean wrote:
> On Fri, Feb 12, 2021 at 08:01:33PM +0530, Vignesh Raghavendra wrote:
>> Hi Vladimir,
>>
>> On 2/12/21 7:47 PM, Grygorii Strashko wrote:
>>>
>>>
>>> On 12/02/2021 03:05, Vladimir Oltean wrote:
>>
ash these when you post new version:
Sorry for not noticing earlier.
-- >8 --
>From 69f3a1ff1ea0777f5deceefdb0e79ce625e6488a Mon Sep 17 00:00:00 2001
From: Vignesh Raghavendra
Date: Fri, 12 Feb 2021 19:34:46 +0530
Subject: [PATCH 1/2] fixup! net: switchdev: propagate extack to port
attributes
J721e, J7200 and AM64 have multi port switches which can work in multi
mac mode and in switch mode. Add documentation explaining how to use
different modes.
Borrowed from:
Documentation/networking/device_drivers/ethernet/ti/cpsw_switchdev.rst
Signed-off-by: Vignesh Raghavendra
This series adds switchdev support for AM65 CPSW NUSS driver to support
multi port CPSW present on J721e and AM64 SoCs.
It adds devlink hook to switch b/w switch mode and multi mac mode.
v2:
Rebased on latest net-next
Update patch 1/4 with rationale for using devlink
Vignesh Raghavendra (4
FLAGS
- SWITCHDEV_ATTR_ID_PORT_STP_STATE
- SWITCHDEV_OBJ_ID_PORT_VLAN
- SWITCHDEV_OBJ_ID_PORT_MDB
- SWITCHDEV_OBJ_ID_HOST_MDB
Hence AM65 CPSW switchdev driver supports:
- FDB offloading
- MDB offloading
- VLAN filtering and offloading
- STP
Signed-off-by: Vignesh Raghav
reconfiguration, therefore is easier to be made as part of mode change
devlink hooks. It also allows to keep user interface similar to what
was implemented for the previous generation of TI CPSW IP
(on AM33/AM43/AM57 SoCs).
Signed-off-by: Vignesh Raghavendra
---
.../devlink/am65-nuss-cpsw-switch.rst
Register netdevice notifiers in order to receive notification when
individual MAC ports are added to the HW bridge.
Signed-off-by: Vignesh Raghavendra
---
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 130 ++-
drivers/net/ethernet/ti/am65-cpsw-nuss.h | 4 +
2 files changed
annel TPL
handling")
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 298460438bb4..a1af59d901be 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
On 1/7/21 10:09 PM, Aswath Govindraju wrote:
> Fix module autoprobe by correcting module alias to match the string from
> /sys/class/.../spi1.0/modalias content.
>
> Fixes: 06b4501e88ad ("misc/eeprom: add driver for microwire 93xx46 EEPROMs")
> Signed-off-by: Aswath Govindraju
> ---
> drivers
ed, 157 insertions(+), 44 deletions(-)
>
For the series:
Reviewed-by: Vignesh Raghavendra
Regards
Vignesh
On 12/8/20 6:53 AM, Xiaoming Ni wrote:
> On 2020/12/8 2:59, Vignesh Raghavendra wrote:
>> Hi Xiaoming,
>>
[...]
>>>>> ---
>>>>> drivers/mtd/chips/cfi_cmdset_0002.c | 16
>>>>> 1 file changed, 16 insertions(+)
her
parameter tables are parsed.
Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table")
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/sfdp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/sfdp.c
m/lit/er/sprz360i/sprz360i.pdf
> Fixes: 61929cf0169d ("tty: serial: Add 8250-core based omap driver")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Alexander Sverdlin
Thanks for the fix.
Reviewed-by: Vignesh Raghavendra
> ---
> drivers/tty/serial/8250/8250_omap.c | 5 -
Hi Michael,
On Thu, 3 Dec 2020 17:29:52 +0100, Michael Walle wrote:
> I bundled this as a series, because otherwise there will be conflicts
> because the "remove global protection flag" patches modify the same lines
> as the main patch.
>
> There are now two more patches:
> mtd: spi-nor: sst: f
On 12/1/20 3:57 PM, Pratyush Yadav wrote:
> The S28 flash family uses 2-bit ECC by default with each ECC block being
> 16 bytes. Under this scheme multi-pass programming to an ECC block is
> not allowed. Set the writesize to make sure multi-pass programming is
> not attempted on the flash.
>
>
Hi Pratyush,
On 12/1/20 3:57 PM, Pratyush Yadav wrote:
> Some flashes like the Cypress S28 family use ECC. Under this ECC scheme,
> multi-pass writes to an ECC block is not allowed. In other words, once
> data is programmed to an ECC block, it can't be programmed again without
> erasing it first.
On Mon, 30 Nov 2020 16:24:15 +0100, Jonathan Neuschäfer wrote:
> There are a few typos in comments in the SPI NOR framework; fix them.
Addressed Tudor's comments locally.
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git
spi-nor/next, thanks!
[1/1] mtd: spi-nor: Fix multip
Hi Xiaoming,
On 12/7/20 4:23 PM, Miquel Raynal wrote:
> Hi Xiaoming,
>
> Xiaoming Ni wrote on Mon, 7 Dec 2020 18:48:33
> +0800:
>
>> ping
>>
>> On 2020/11/27 21:07, Xiaoming Ni wrote:
>>> When CONFIG_MTD_XIP=y, local_irq_disable() is called in xip_disable().
>>> To avoid sleep in interrupt cont
On 11/30/20 10:50 PM, Andrew Lunn wrote:
>> +static int am65_cpsw_port_stp_state_set(struct am65_cpsw_port *port,
>> +struct switchdev_trans *trans, u8 state)
>> +{
>> +struct am65_cpsw_common *cpsw = port->common;
>> +u8 cpsw_state;
>> +int ret =
Hi Andrew,
On 11/30/20 9:20 PM, Andrew Lunn wrote:
> On Mon, Nov 30, 2020 at 01:50:43PM +0530, Vignesh Raghavendra wrote:
>> AM65 NUSS ethernet switch on K3 devices can be configured to work either
>> in independent mac mode where each port acts as independent network
>> int
below, for pm_runtime of 'pdev->dev' should
> be disabled when pm_runtime_resume_and_get fails.
>
> Fixes: 3b0fb97c8dc4 ("I2C: OMAP: Handle error check for pm runtime")
> Reported-by: Hulk Robot
> Signed-off-by: Qinglang Miao
> ---
Reviewed-by: Vignesh Ra
FLOOD
- SWITCHDEV_ATTR_ID_PORT_STP_STATE
- SWITCHDEV_OBJ_ID_PORT_VLAN
- SWITCHDEV_OBJ_ID_PORT_MDB
- SWITCHDEV_OBJ_ID_HOST_MDB
Hence AM65 CPSW switchdev driver supports:
- FDB offloading
- MDB offloading
- VLAN filtering and offloading
- STP
Signed-off-by: Vi
J721e, J7200 and AM64 have multi port switches which can work in multi
mac mode and in switch mode. Add documentation explaining how to use
different modes.
Borrowed from:
Documentation/networking/device_drivers/ethernet/ti/cpsw_switchdev.rst
Signed-off-by: Vignesh Raghavendra
Register netdevice notifiers in order to receive notification when
individual MAC ports are added to the HW bridge.
Signed-off-by: Vignesh Raghavendra
---
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 130 ++-
drivers/net/ethernet/ti/am65-cpsw-nuss.h | 4 +
2 files changed
This series adds switchdev support for AM65 CPSW NUSS driver to support
multi port CPSW present on J721e and AM64 SoCs.
It adds devlink hook to switch b/w switch mode and multi mac mode.
Vignesh Raghavendra (4):
net: ti: am65-cpsw-nuss: Add devlink support
net: ti: am65-cpsw-nuss: Add
AM65 NUSS ethernet switch on K3 devices can be configured to work either
in independent mac mode where each port acts as independent network
interface (multi mac) or switch mode.
Add devlink hooks to provide a way to switch b/w these modes.
Signed-off-by: Vignesh Raghavendra
---
.../devlink
p3 and at the same time add the
> line names as well.
>
> Signed-off-by: Peter Ujfalusi
> ---
Yes, the schematics call this expander as exp3. Thanks for the fix
Reviewed-by: Vignesh Raghavendra
> arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 5 -
> 1 file
xpander on SOM that's missing from DT
today. So this change looks good to me.
Reviewed-by: Vignesh Raghavendra
Regards
Vignesh
> .../dts/ti/k3-j7200-common-proc-board.dts | 11
> arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 26 +++
> 2 files chan
On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
> Add QSPI controller support for Intel LGM SoC.
>
> Note from Vignesh(mtd subsystem maintainer):
> This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
> support for the Cadence QSPI controller" by Ramuthevar,Vadivel Mur
On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan
>
> Add multiple chipselect support for Intel LGM SoCs,
> currently QSPI-NOR and QSPI-NAND supported.
>
> Signed-off-by: Ramuthevar Vadivel Murugan
>
> ---
> drivers/spi/spi-cadence-quadspi.c | 15 +
On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
> Add QSPI controller support for Intel LGM SoC.
>
> Note from Vignesh(mtd subsystem maintainer):
> This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
> support for the Cadence QSPI controller" by Ramuthevar,Vadivel Mur
On 11/9/20 10:34 PM, Kishon Vijay Abraham I wrote:
> Add PCIe device tree node (both RC and EP) for the single PCIe
> instance present in j7200.
>
nit: s/j7200/J7200
> Signed-off-by: Kishon Vijay Abraham I
> ---
Reviewed-by: Vignesh Raghavendra
[...]
On 11/9/20 10:34 PM, Kishon Vijay Abraham I wrote:
> Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
> to PCIe and QSGMII (multi-link SERDES).
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> .../dts/ti/k3-j7200-common-proc-board.dts | 23 +++
> 1 file
On 11/12/20 7:19 AM, Nishanth Menon wrote:
> Follow the device tree standards that states to set the
> status="reserved" if an device is operational, but used by a non-linux
> firmware in the system.
>
> Signed-off-by: Nishanth Menon
> ---
Acked-by: Vignesh Raghavendra
On 11/9/20 10:34 PM, Kishon Vijay Abraham I wrote:
> x2 lane PCIe slot in the common processor board is enabled and connected to
> j7200 SOM. Add PCIe DT node in common processor board to reflect the
> same.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
Reviewed-by: V
On 11/12/20 1:57 PM, Miquel Raynal wrote:
> Hi Sergey,
>
> Serge Semin wrote on Wed, 11 Nov
> 2020 22:22:59 +0300:
>
>> On Tue, Nov 10, 2020 at 04:35:56PM +0100, Miquel Raynal wrote:
>>> Hi Serge,
>>>
>>> Serge Semin wrote on Tue, 10 Nov
>>> 2020 14:38:27 +0300:
>>>
Hello Miquel,
>>>
riable]
Fix this by moving the code using k3_soc_devices array to
omap_serial_fill_features_erratas() that handles other errata flags as
well.
Fixes: 439c7183e5b9 ("serial: 8250: 8250_omap: Disable RX interrupt after DMA
enable")
Reported-by: kernel test robot
Signed-off-by: Vignesh
k3_soc_devices array is missing a sentinel entry which may result in out
of bounds access as reported by kernel KASAN.
Fix this by adding a sentinel entry.
Fixes: 439c7183e5b9 ("serial: 8250: 8250_omap: Disable RX interrupt after DMA
enable")
Reported-by: Naresh Kamboju
Signed-off-b
Hi Naresh,
On 11/11/20 12:08 PM, Stephen Rothwell wrote:
> Hi Naresh,
>
> On Wed, 11 Nov 2020 11:55:46 +0530 Naresh Kamboju
> wrote:
>>
>> The following kernel warning noticed on arm KASAN enabled config while
>> booting on
>> TI beagleboard x15 device.
>>
>> [ 32.127451] BUG: KASAN: global-o
Hi Chin-Ting,
On 11/6/20 11:57 PM, Chin-Ting Kuo wrote:
> Hi Boris,
>
>> -Original Message-
>> From: Boris Brezillon
>> Sent: Friday, November 6, 2020 7:30 PM
>> To: Chin-Ting Kuo
>> Subject: Re: [v3 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller
>> driver
>>
>> +Tudor and Vigne
Hi,
On 11/7/20 7:11 PM, Jonathan Neuschäfer wrote:
> Signed-off-by: Jonathan Neuschäfer
Thanks for the patch, but a commit msg is expected however trivial the
patch maybe. scripts/checkpatch.pl --strict complains about the same:
WARNING: Missing commit description - Add an appropriate one
Rega
On 10/28/20 3:56 AM, Michael Walle wrote:
> Am 2020-10-03 17:32, schrieb Michael Walle:
>> I bundled this as a series, because otherwise there will be conflicts
>> because the "remove global protection flag" patches modify the same lines
>> as the main patch.
>>
>> See invdividual patches for th
On 10/16/20 5:25 PM, Lad Prabhakar wrote:
> This chip is (nearly) identical to the Winbond w25m512jv which is
> already supported by Linux. Compared to the w25m512jv, the 'jw'
> has a different JEDEC ID.
>
> Signed-off-by: Lad Prabhakar
> Reviewed-by: Biju Das
I believe this was tested on a
On Mon, 5 Oct 2020 21:01:23 +0530, Pratyush Yadav wrote:
> This series adds support for Octal DTR flashes in the SPI NOR framework,
> and then adds hooks for the Cypress Semper and Micron Xcella flashes to
> allow running them in Octal DTR mode. This series assumes that the flash
> is handed to the
Hi,
[...]
On 10/5/20 9:01 PM, Pratyush Yadav wrote:
> +static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
> +{
> + struct spi_mem_op op;
> + u8 *buf = nor->bouncebuf;
> + int ret;
> +
> + if (enable) {
> + /* Use 24 dummy cycles for memory ar
controllers/hisi-sfc.c:328: warning: Function parameter
> or member 'host' not described in 'hisi_spi_nor_register'
>
> Cc: Tudor Ambarus
> Cc: Miquel Raynal
> Cc: Richard Weinberger
> Cc: Vignesh Raghavendra
> Cc: Sumit Semwal
> Cc: "Christian König&
On 11/3/20 6:15 PM, Pratyush Yadav wrote:
> On 03/11/20 05:05PM, Vignesh Raghavendra wrote:
>>
>>
>> On 11/1/20 3:14 AM, Richard Weinberger wrote:
>>> On Tue, Oct 27, 2020 at 12:24 PM Pratyush Yadav wrote:
>>>>> [0]
>>>>> https://lo
On 10/12/20 11:34 PM, Pratyush Yadav wrote:
> For NOR flashes EC and VID are zeroed out before an erase is issued to
> make sure UBI does not mistakenly treat the PEB as used and associate it
> with an LEB.
>
> But on some flashes, like the Cypress Semper S28 SPI NOR flash family,
> multi-pass
On 11/1/20 3:14 AM, Richard Weinberger wrote:
> On Tue, Oct 27, 2020 at 12:24 PM Pratyush Yadav wrote:
>>> [0] https://lore.kernel.org/linux-mtd/20201005153138.6437-1-p.ya...@ti.com/
>>
>> Ping. Any comments on the series?
>
> From the UBIFS point of view I'd like to avoid as many device speci
d-off-by: Grygorii Strashko
> ---
Reviewed-by: Vignesh Raghavendra
> drivers/pwm/pwm-tiehrpwm.c | 12
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
> index 0846917ff2d2..14c8fdcfd607 10064
On Mon, 5 Oct 2020 10:48:03 +0200, Alexander A Sverdlin wrote:
> spi_nor_parse_sfdp() modifies the passed structure so that it points to
> itself (params.erase_map.regions to params.erase_map.uniform_region). This
> makes it impossible to copy the local struct anywhere else.
>
> Therefore only use
On Tue, 6 Oct 2020 15:23:46 +0200, Bert Vermeulen wrote:
> If a flash chip has more than 16MB capacity but its BFPT reports
> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
>
> The check in spi_nor_set_addr_width() doesn't catch it because addr_width
> did get set. This fix
arted so as to avoid spurious interrupt being raised
when data is in the RX FIFO but is yet to be drained by DMA (a known
errata in older SoCs).
Signed-off-by: Vignesh Raghavendra
---
drivers/tty/serial/8250/8250_omap.c | 42 -
1 file changed, 41 insertions(+), 1 del
J7200 has a single instance of 8 channel ADC in MCU domain. Add DT node
for the same.
Signed-off-by: Vignesh Raghavendra
---
Resending, after rebasing and testing on top of 5.10-rc1. No code
change.
v1: https://lore.kernel.org/r/20201013081650.26090-1-vigne...@ti.com
.../dts/ti/k3-j7200
On 10/28/20 8:51 PM, tudor.amba...@microchip.com wrote:
> On 10/28/20 2:49 PM, Pratyush Yadav wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> Hi Tudor,
>>
>> On 28/10/20 07:53AM, tudor.amba...@microchip.com wrote:
>>> Hi, Pratyush,
>
AM64 uses a UART controller that is compatible with AM654 UART.
Introduce a specific compatible to help handle the differences if
necessary.
Signed-off-by: Vignesh Raghavendra
---
Documentation/devicetree/bindings/serial/omap_serial.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a
J7200 has a single instance of 8 channel ADC in MCU domain. Add DT node
for the same.
Signed-off-by: Vignesh Raghavendra
---
.../dts/ti/k3-j7200-common-proc-board.dts | 6 ++
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 19 +++
2 files changed, 25 insertions(+)
diff
o `rpcif_prepare' ld:
drivers/mtd/hyperbus/rpc-if.o: in function `rpcif_hb_read16':
[...]
Fixes: 5de15b610f78 ("mtd: hyperbus: add Renesas RPC-IF driver") leads
Reported-by: Richard Weinberger
Signed-off-by: Vignesh Raghavendra
---
Based on mtd/next
Richard,
Could you pleas
On 10/6/20 8:48 PM, Pratyush Yadav wrote:
> On 06/10/20 03:23PM, Bert Vermeulen wrote:
>> If a flash chip has more than 16MB capacity but its BFPT reports
>> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
>>
>> The check in spi_nor_set_addr_width() doesn't catch it becaus
On Mon, 5 Oct 2020 14:33:21 +0530, Vignesh Raghavendra wrote:
> This reverts commit 03edda0e1edaa3c2e99239c66e3c14d749318fd6.
>
> This leads to warn dump like [1] on some platforms and reorders MTD
> devices thus may break user space expectations. So revert the cha
Hi Michael,
On 10/3/20 10:24 PM, Michael Walle wrote:
> Hi Douglas,
>
> Am 2020-10-03 18:27, schrieb Doug Anderson:
>> Hi,
>>
>> On Sat, Oct 3, 2020 at 8:22 AM Michael Walle wrote:
>>>
>>> Hi Douglas,
>>>
>>> > On my system the spi_nor_probe() took ~6 ms at bootup. That's not a
>>> > lot, but e
: device is disabled, skipping
[1.858753] WARNING: CPU: 1 PID: 7 at kernel/kmod.c:136
__request_module+0x3a4/0x568
[...]
Reported-by: Michael Walle
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/core.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mtd/spi-nor
Hi Pratyush,
On 10/2/20 1:50 AM, Pratyush Yadav wrote:
> +
> +/**
> + * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
> + * @nor: pointer to a 'struct spi_nor'
> + * @enable: whether to enable or disable Octal DTR
> + *
> + * This also sets the
Hi,
On 10/1/20 1:20 PM, Miquel Raynal wrote:
> Hello,
>
> Pratyush Yadav wrote on Thu, 1 Oct 2020 13:04:27 +0530:
>
>> On 01/10/20 07:19AM, tudor.amba...@microchip.com wrote:
>>> On 9/30/20 9:57 PM, Pratyush Yadav wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you k
1 - 100 of 409 matches
Mail list logo
