is added to separate from memory specific apis.
- MSR update api names are changed from having cbm to ctrl.
- info file API names are set to reflect generic default_ctrl or control
values rather than cbm.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/intel
is added to separate from memory specific apis.
- MSR update api names are changed from having cbm to ctrl.
- info file API names are set to reflect generic default_ctrl or control
values rather than cbm.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 22
Update the intel_rdt_ui documentation to have Memory bandwidth(b/w)
allocation interface usage.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
Documentation/x86/intel_rdt_ui.txt | 74 ++
1 file changed, 67 insertions(+), 7 del
Update the intel_rdt_ui documentation to have Memory bandwidth(b/w)
allocation interface usage.
Signed-off-by: Vikas Shivappa
---
Documentation/x86/intel_rdt_ui.txt | 74 ++
1 file changed, 67 insertions(+), 7 deletions(-)
diff --git a/Documentation/x86
Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1.
Add supporting data structures to detect feature details which is done
in later patch using CPUID with EAX=10H, ECX= 3.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/cpufeatures
Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1.
Add supporting data structures to detect feature details which is done
in later patch using CPUID with EAX=10H, ECX= 3.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/include/asm/intel_rdt.h
are 10,20,30...
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/intel_rdt.h | 2 +
arch/x86/kernel/cpu/intel_rdt.c | 1 +
arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 64
3 files changed, 67 insertions(+)
are 10,20,30...
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 2 +
arch/x86/kernel/cpu/intel_rdt.c | 1 +
arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 64
3 files changed, 67 insertions(+)
diff --git a/arch/x86/include/asm
-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/intel_rdt.h | 17 +++
arch/x86/kernel/cpu/intel_rdt.c | 95 ++--
2 files changed, 99 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/i
-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 17 +++
arch/x86/kernel/cpu/intel_rdt.c | 95 ++--
2 files changed, 99 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
index d2eee45
Memory b/w allocation(MBA) is part of the Intel Resource Director
Technology (RDT). RDT helps monitor and share processor shared
resources. MBA helps enforce a limit on the memory bandwidth(b/w)
threads can use when they are scheduled. OS does the enforcement using
MSR(model specific register)
Memory b/w allocation(MBA) is part of the Intel Resource Director
Technology (RDT). RDT helps monitor and share processor shared
resources. MBA helps enforce a limit on the memory bandwidth(b/w)
threads can use when they are scheduled. OS does the enforcement using
MSR(model specific register)
resource and cache resource info files.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/intel_rdt.h | 5 +
arch/x86/kernel/cpu/intel_rdt.c | 1 +
arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 18 ++
3 files chang
resource and cache resource info files.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 5 +
arch/x86/kernel/cpu/intel_rdt.c | 1 +
arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 18 ++
3 files changed, 20 insertions(+), 4 deletions
for the resources depending on whether its displayed in
hex/decimal.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/intel_rdt.h | 8 +++
arch/x86/kernel/cpu/intel_rdt.c | 33 +-
arch/x86/kernel/cpu/intel_rdt_sche
the corresponding domain PQOS_MSRs which are indexed from 0xD50
for MBA.
For linear scale the granularity is just the 100-max_delay. For
non-linear values, it is obtained by the mapping between the delay
values and percentage b/w values.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.
for the resources depending on whether its displayed in
hex/decimal.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 8 +++
arch/x86/kernel/cpu/intel_rdt.c | 33 +-
arch/x86/kernel/cpu/intel_rdt_schemata.c | 40
the corresponding domain PQOS_MSRs which are indexed from 0xD50
for MBA.
For linear scale the granularity is just the 100-max_delay. For
non-linear values, it is obtained by the mapping between the delay
values and percentage b/w values.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm
resources
because the entire change is atomic. Also this avoids looping all
enabled resources again.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/kernel/cpu/intel_rdt_schemata.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/ar
resources
because the entire change is atomic. Also this avoids looping all
enabled resources again.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt_schemata.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_rdt_schemata.c
-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/kernel/cpu/intel_rdt_schemata.c | 40
1 file changed, 30 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_rdt_schemata.c
b/arch/x86/kernel/cpu/intel_rdt_schemata.c
index 1
-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt_schemata.c | 40
1 file changed, 30 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_rdt_schemata.c
b/arch/x86/kernel/cpu/intel_rdt_schemata.c
index 14ba504..64b43b1 100644
--- a/arch/x86
are per package. Change the update to QOS_MSRs to
happen only when the control value on the particular domain is updated.
Hence not sending IPIs on all domains when user updates the control
vals.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/kern
are per package. Change the update to QOS_MSRs to
happen only when the control value on the particular domain is updated.
Hence not sending IPIs on all domains when user updates the control
vals.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt_schemata.c | 11 +--
1 file
Add some improvements to the existing RDT(Resource director technology)
framework and fix some hotcpu RDT code. Sending them as a seperate
series as per Thomas suggestion during the V1 of MBA review (Memory
bandwidth allocation) -
https://marc.info/?l=linux-kernel=148407699309286
Patches are
During rmdir reset the ctrl values to all 1s in the QOS_MSR for the
directory's closid. This is done so that that next time when the closid
is reused they dont reflect old values.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/kernel/cpu/intel_rdt_rdtgroup.
Add some improvements to the existing RDT(Resource director technology)
framework and fix some hotcpu RDT code. Sending them as a seperate
series as per Thomas suggestion during the V1 of MBA review (Memory
bandwidth allocation) -
https://marc.info/?l=linux-kernel=148407699309286
Patches are
During rmdir reset the ctrl values to all 1s in the QOS_MSR for the
directory's closid. This is done so that that next time when the closid
is reused they dont reflect old values.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 18 +-
1 file changed
down, rather than waiting to clear it during online cpu.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/events/intel/cqm.c | 10 +-
arch/x86/kernel/cpu/intel_rdt.c | 1 -
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/x86/events
down, rather than waiting to clear it during online cpu.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 10 +-
arch/x86/kernel/cpu/intel_rdt.c | 1 -
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/x86/events/intel/cqm.c b/arch/x86/events/intel/cqm.c
Resending including Thomas , also with some changes. Sorry for the spam
Based on Thomas and Peterz feedback Can think of two design
variants which target:
-Support monitoring and allocating using the same resctrl group.
user can use a resctrl group to allocate resources and also monitor
them
Resending including Thomas , also with some changes. Sorry for the spam
Based on Thomas and Peterz feedback Can think of two design
variants which target:
-Support monitoring and allocating using the same resctrl group.
user can use a resctrl group to allocate resources and also monitor
them
Based on Thomas and Peterz feedback Can think of two variants which target:
-Support monitoring and allocating using the same resctrl group.
user can use a resctrl group to allocate resources and also monitor
them (with respect to tasks or cpu)
-allows 'task only' monitoring outside of resctrl.
Based on Thomas and Peterz feedback Can think of two variants which target:
-Support monitoring and allocating using the same resctrl group.
user can use a resctrl group to allocate resources and also monitor
them (with respect to tasks or cpu)
-allows 'task only' monitoring outside of resctrl.
Memory b/w allocation(MBA) is part of the Intel Resource Director
Technology (RDT). RDT helps monitor and share processor shared
resources. MBA helps enforce a limit on the memory b/w, threads can use
when they are scheduled. OS does the enforcement using MSR(model
specific register) interface
Memory b/w allocation(MBA) is part of the Intel Resource Director
Technology (RDT). RDT helps monitor and share processor shared
resources. MBA helps enforce a limit on the memory b/w, threads can use
when they are scheduled. OS does the enforcement using MSR(model
specific register) interface
^n if non-linear scale. OS then updates the corresponding domain
PQOS_MSRs which are indexed from 0xD50 for MBA. The schemata APIs for
parsing and validating the schemata input are changed to accommodate
handling of both cbm and throttle values.
Signed-off-by: Vikas Shivappa <vikas.sh
to be zero when cpu is online, remove the PQR MSR write to zero during
cpuonline because the MSRs are at zero after cpu reset and also during
the first sched in they are updated.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/events/intel/cqm.c | 1 -
ar
to separate from memory specific apis.
- MSR update api names are changed from having cbm to ctrl.
- info file API names are set to reflect generic no_ctrl or control values
rather than cbm.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/intel_rdt.h
^n if non-linear scale. OS then updates the corresponding domain
PQOS_MSRs which are indexed from 0xD50 for MBA. The schemata APIs for
parsing and validating the schemata input are changed to accommodate
handling of both cbm and throttle values.
Signed-off-by: Vikas Shivappa
---
arch/x86
to be zero when cpu is online, remove the PQR MSR write to zero during
cpuonline because the MSRs are at zero after cpu reset and also during
the first sched in they are updated.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 1 -
arch/x86/kernel/cpu/intel_rdt.c
to separate from memory specific apis.
- MSR update api names are changed from having cbm to ctrl.
- info file API names are set to reflect generic no_ctrl or control values
rather than cbm.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 20 ++--
arch/x86
. Parameters specific to delay values and delay
granularity are added to the RDT resource and domain structure.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/intel_rdt.h | 10 +
arch/x86/kernel/cpu/intel_rdt.c
. Parameters specific to delay values and delay
granularity are added to the RDT resource and domain structure.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 10 +
arch/x86/kernel/cpu/intel_rdt.c | 70 ++--
arch/x86/kernel/cpu
the configured values. But if a throttle_by value of x > y, then x is
guaranteed to throttle more b/w than y.
- throttle granularity: Shows the throttle granularity of the throttle
values that can be configured.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/in
resources.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/intel_rdt.h | 16 +
arch/x86/kernel/cpu/intel_rdt_schemata.c | 40 +---
2 files changed, 37 insertions(+), 19 deletions(-)
diff --git a/ar
the configured values. But if a throttle_by value of x > y, then x is
guaranteed to throttle more b/w than y.
- throttle granularity: Shows the throttle granularity of the throttle
values that can be configured.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 8 ++-
arch/
resources.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 16 +
arch/x86/kernel/cpu/intel_rdt_schemata.c | 40 +---
2 files changed, 37 insertions(+), 19 deletions(-)
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86
allocation interface usage.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
Documentation/x86/intel_rdt_ui.txt | 31 +++
1 file changed, 31 insertions(+)
diff --git a/Documentation/x86/intel_rdt_ui.txt
b/Documentation/x86/intel_rdt_ui.txt
index d
allocation interface usage.
Signed-off-by: Vikas Shivappa
---
Documentation/x86/intel_rdt_ui.txt | 31 +++
1 file changed, 31 insertions(+)
diff --git a/Documentation/x86/intel_rdt_ui.txt
b/Documentation/x86/intel_rdt_ui.txt
index d918d26..23959ba 100644
Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1.
Add supporting data structures to detect feature details which is done
in later patch using CPUID with EAX=10H, ECX= 3.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/include/asm/cpufeatures.
Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1.
Add supporting data structures to detect feature details which is done
in later patch using CPUID with EAX=10H, ECX= 3.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/include/asm/intel_rdt.h
Another attempt for cqm2 series-
Cqm(cache quality monitoring) is part of Intel RDT(resource director
technology) which enables monitoring and controlling of processor shared
resources via MSR interface.
The current upstream cqm(Cache monitoring) has major issues which make
the feature almost
Add documentation of usage of cqm and mbm events using perf interface
and examples.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
Documentation/x86/intel_rdt_mon_ui.txt | 62 ++
1 file changed, 62 insertions(+)
create mode
fixes this problem by modifying read_counters()
to mark the event as not scaled (scaled = -1) to force
the printout routine to show .
Signed-off-by: Stephane Eranian <eran...@google.com>
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
tools/perf/builtin-stat.c | 12 ++
read_counters()
to mark the event as not scaled (scaled = -1) to force
the printout routine to show .
Signed-off-by: Stephane Eranian
Signed-off-by: Vikas Shivappa
---
tools/perf/builtin-stat.c | 12 +---
tools/perf/util/evsel.c | 4 ++--
2 files changed, 11 insertions(+), 5 deletions
Add documentation of usage of cqm and mbm events using perf interface
and examples.
Signed-off-by: Vikas Shivappa
---
Documentation/x86/intel_rdt_mon_ui.txt | 62 ++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/x86/intel_rdt_mon_ui.txt
diff
Another attempt for cqm2 series-
Cqm(cache quality monitoring) is part of Intel RDT(resource director
technology) which enables monitoring and controlling of processor shared
resources via MSR interface.
The current upstream cqm(Cache monitoring) has major issues which make
the feature almost
ephane Eranian <eran...@google.com>
Signed-off-by: David Carrillo-Cisneros <davi...@google.com>
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
tools/perf/builtin-stat.c | 36 +++---
tools/perf/util/counts.h | 19 ++
tools/
-by: David Carrillo-Cisneros
Signed-off-by: Vikas Shivappa
---
tools/perf/builtin-stat.c | 36 +++---
tools/perf/util/counts.h | 19 ++
tools/perf/util/evsel.c | 49 ---
tools/perf/util/evsel.h | 8
Vikas<vikas.shiva...@linux.intel.com>
to only remove recycling parts from code and edit commit message.
Tests: The cqm should either gives correct numbers for task events
or just throw error that its run out of RMIDs.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arc
use the RMIDs that are freed.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/events/intel/cqm.c | 107
1 file changed, 107 insertions(+)
diff --git a/arch/x86/events/intel/cqm.c b/arch/x86/events/intel/cqm.c
index e1765e3
s
in cqm2 series.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/events/intel/cqm.c | 31 ---
arch/x86/include/asm/intel_rdt_common.h | 2 +-
include/linux/perf_event.h | 19 ---
kerne
use the RMIDs that are freed.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 107
1 file changed, 107 insertions(+)
diff --git a/arch/x86/events/intel/cqm.c b/arch/x86/events/intel/cqm.c
index e1765e3..92efe12 100644
--- a/arch/x86/events/in
off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 31 ---
arch/x86/include/asm/intel_rdt_common.h | 2 +-
include/linux/perf_event.h | 19 ---
kernel/events/core.c| 16
4 files changed,
parts from code and edit commit message.
Tests: The cqm should either gives correct numbers for task events
or just throw error that its run out of RMIDs.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 647 ++--
1 file changed, 30 insertions
com> patches
in cqm2 series.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/events/intel/cqm.c | 45 ++-
arch/x86/include/asm/intel_pqr_common.h | 38 +
arch/x86/include/asm/intel_rdt.h | 39 -
arch/x86
From: Vikas Shivappa<vikas.shiva...@intel.com>
This patch adds support to monitor a cgroup x and a task p1
when p1 is part of cgroup x. Since we cannot write two RMIDs during
sched in the driver handles this.
This patch introduces a u32 *rmid in the task_struck which keeps track
of the
,put_rmid, perf start, terminate
Tests: RMIDs available increase by x times where x is number of sockets
and the usage is dynamic so we save more.
Patch is based on David Carrillo-Cisneros <davi...@google.com> patches
in cqm2 series.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.
Add a compile option INTEL_RDT which enables common code for all
RDT(Resource director technology) and a specific INTEL_RDT_M which
enables code for RDT monitoring. CQM(cache quality monitoring) and
mbm(memory b/w monitoring) are part of Intel RDT monitoring.
Signed-off-by: Vikas Shivappa
cgroup->arch_info: css_alloc,
css_free, event terminate, init hold mutex.
Tests: Cgroup monitoring should work. Monitoring multiple cgroups in the
same hierarchy works. monitoring cgroup and a task within same cgroup
doesnt work yet.
Patch modified/refactored by Vikas Shivappa
<vikas.shiva...@lin
.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 45 ++-
arch/x86/include/asm/intel_pqr_common.h | 38 +
arch/x86/include/asm/intel_rdt.h | 39 -
arch/x86/include/asm/intel_rdt_common.h | 11
arch/x86/include/asm
From: Vikas Shivappa
This patch adds support to monitor a cgroup x and a task p1
when p1 is part of cgroup x. Since we cannot write two RMIDs during
sched in the driver handles this.
This patch introduces a u32 *rmid in the task_struck which keeps track
of the RMIDs associated with the task
,put_rmid, perf start, terminate
Tests: RMIDs available increase by x times where x is number of sockets
and the usage is dynamic so we save more.
Patch is based on David Carrillo-Cisneros patches
in cqm2 series.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 340
Add a compile option INTEL_RDT which enables common code for all
RDT(Resource director technology) and a specific INTEL_RDT_M which
enables code for RDT monitoring. CQM(cache quality monitoring) and
mbm(memory b/w monitoring) are part of Intel RDT monitoring.
Signed-off-by: Vikas Shivappa
loc,
css_free, event terminate, init hold mutex.
Tests: Cgroup monitoring should work. Monitoring multiple cgroups in the
same hierarchy works. monitoring cgroup and a task within same cgroup
doesnt work yet.
Patch modified/refactored by Vikas Shivappa
to support recycling removal.
Signed-
before. Cgroup still doesnt work but we did the prep to
get it to work
Patch modified/refactored by Vikas Shivappa
<vikas.shiva...@linux.intel.com> to support recycling removal.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/events/intel/cqm.c | 19 +++
but we did the prep to
get it to work
Patch modified/refactored by Vikas Shivappa
to support recycling removal.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 19 ++-
arch/x86/include/asm/perf_event.h | 27 +++
include/linux
,put_rmid, perf start, terminate
Tests: RMIDs available increase by x times where x is number of sockets
and the usage is dynamic so we save more.
Patch is based on David Carrillo-Cisneros <davi...@google.com> patches
in cqm2 series.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.
,put_rmid, perf start, terminate
Tests: RMIDs available increase by x times where x is number of sockets
and the usage is dynamic so we save more.
Patch is based on David Carrillo-Cisneros patches
in cqm2 series.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 340
Resending version 5 with updated send list. Sorry for the spam.
Cqm(cache quality monitoring) is part of Intel RDT(resource director
technology) which enables monitoring and controlling of processor shared
resources via MSR interface.
The current upstream cqm(Cache monitoring) has major issues
before. Cgroup still doesnt work but we did the prep to
get it to work
Patch modified/refactored by Vikas Shivappa
<vikas.shiva...@linux.intel.com> to support recycling removal.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/events/intel/cqm.c | 19 +++
cgroup->arch_info: css_alloc,
css_free, event terminate, init hold mutex.
Tests: Cgroup monitoring should work. Monitoring multiple cgroups in the
same hierarchy works. monitoring cgroup and a task within same cgroup
doesnt work yet.
Patch modified/refactored by Vikas Shivappa
<vikas.shiva...@lin
Resending version 5 with updated send list. Sorry for the spam.
Cqm(cache quality monitoring) is part of Intel RDT(resource director
technology) which enables monitoring and controlling of processor shared
resources via MSR interface.
The current upstream cqm(Cache monitoring) has major issues
but we did the prep to
get it to work
Patch modified/refactored by Vikas Shivappa
to support recycling removal.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 19 ++-
arch/x86/include/asm/perf_event.h | 27 +++
include/linux
loc,
css_free, event terminate, init hold mutex.
Tests: Cgroup monitoring should work. Monitoring multiple cgroups in the
same hierarchy works. monitoring cgroup and a task within same cgroup
doesnt work yet.
Patch modified/refactored by Vikas Shivappa
to support recycling removal.
Signed-
Add a compile option INTEL_RDT which enables common code for all
RDT(Resource director technology) and a specific INTEL_RDT_M which
enables code for RDT monitoring. CQM(cache quality monitoring) and
mbm(memory b/w monitoring) are part of Intel RDT monitoring.
Signed-off-by: Vikas Shivappa
Add documentation of usage of cqm and mbm events using perf interface
and examples.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
Documentation/x86/intel_rdt_mon_ui.txt | 62 ++
1 file changed, 62 insertions(+)
create mode
Add a compile option INTEL_RDT which enables common code for all
RDT(Resource director technology) and a specific INTEL_RDT_M which
enables code for RDT monitoring. CQM(cache quality monitoring) and
mbm(memory b/w monitoring) are part of Intel RDT monitoring.
Signed-off-by: Vikas Shivappa
Add documentation of usage of cqm and mbm events using perf interface
and examples.
Signed-off-by: Vikas Shivappa
---
Documentation/x86/intel_rdt_mon_ui.txt | 62 ++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/x86/intel_rdt_mon_ui.txt
diff
com> patches
in cqm2 series.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/events/intel/cqm.c | 45 ++-
arch/x86/include/asm/intel_pqr_common.h | 38 +
arch/x86/include/asm/intel_rdt.h | 39 -
arch/x86
ephane Eranian <eran...@google.com>
Signed-off-by: David Carrillo-Cisneros <davi...@google.com>
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
tools/perf/builtin-stat.c | 36 +++---
tools/perf/util/counts.h | 19 ++
tools/
s
in cqm2 series.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arch/x86/events/intel/cqm.c | 31 ---
arch/x86/include/asm/intel_rdt_common.h | 2 +-
include/linux/perf_event.h | 19 ---
kerne
.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 45 ++-
arch/x86/include/asm/intel_pqr_common.h | 38 +
arch/x86/include/asm/intel_rdt.h | 39 -
arch/x86/include/asm/intel_rdt_common.h | 11
arch/x86/include/asm
-by: David Carrillo-Cisneros
Signed-off-by: Vikas Shivappa
---
tools/perf/builtin-stat.c | 36 +++---
tools/perf/util/counts.h | 19 ++
tools/perf/util/evsel.c | 49 ---
tools/perf/util/evsel.h | 8
off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 31 ---
arch/x86/include/asm/intel_rdt_common.h | 2 +-
include/linux/perf_event.h | 19 ---
kernel/events/core.c| 16
4 files changed,
fixes this problem by modifying read_counters()
to mark the event as not scaled (scaled = -1) to force
the printout routine to show .
Signed-off-by: Stephane Eranian <eran...@google.com>
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
tools/perf/builtin-stat.c | 12 ++
read_counters()
to mark the event as not scaled (scaled = -1) to force
the printout routine to show .
Signed-off-by: Stephane Eranian
Signed-off-by: Vikas Shivappa
---
tools/perf/builtin-stat.c | 12 +---
tools/perf/util/evsel.c | 4 ++--
2 files changed, 11 insertions(+), 5 deletions
Vikas<vikas.shiva...@linux.intel.com>
to only remove recycling parts from code and edit commit message.
Tests: The cqm should either gives correct numbers for task events
or just throw error that its run out of RMIDs.
Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
---
arc
parts from code and edit commit message.
Tests: The cqm should either gives correct numbers for task events
or just throw error that its run out of RMIDs.
Signed-off-by: Vikas Shivappa
---
arch/x86/events/intel/cqm.c | 647 ++--
1 file changed, 30 insertions
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