On Tue, 28 Jul 2015, Marcelo Tosatti wrote:
On Wed, Jul 01, 2015 at 03:21:04PM -0700, Vikas Shivappa wrote:
Adds a description of Cache allocation technology, overview
of kernel implementation and usage of Cache Allocation cgroup interface.
Cache allocation is a sub-feature of Resource
On Tue, 28 Jul 2015, Peter Zijlstra wrote:
On Wed, Jul 01, 2015 at 03:21:07PM -0700, Vikas Shivappa wrote:
+static inline bool cbm_is_contiguous(unsigned long var)
+{
+ unsigned long maxcbm = MAX_CBM_LENGTH;
+ unsigned long first_bit, zero_bit;
+
+ if (!var
On Tue, 28 Jul 2015, Peter Zijlstra wrote:
On Wed, Jul 01, 2015 at 03:21:05PM -0700, Vikas Shivappa wrote:
+static int __init intel_rdt_late_init(void)
+{
+ struct cpuinfo_x86 *c = _cpu_data;
+
+ if (!cpu_has(c, X86_FEATURE_CAT_L3))
+ return -ENODEV
On Tue, 28 Jul 2015, Marcelo Tosatti wrote:
On Wed, Jul 01, 2015 at 03:21:04PM -0700, Vikas Shivappa wrote:
Adds a description of Cache allocation technology, overview
of kernel implementation and usage of Cache Allocation cgroup interface.
Cache allocation is a sub-feature of Resource
On Tue, 28 Jul 2015, Peter Zijlstra wrote:
On Wed, Jul 01, 2015 at 03:21:05PM -0700, Vikas Shivappa wrote:
+static int __init intel_rdt_late_init(void)
+{
+ struct cpuinfo_x86 *c = boot_cpu_data;
+
+ if (!cpu_has(c, X86_FEATURE_CAT_L3))
+ return -ENODEV
On Tue, 28 Jul 2015, Peter Zijlstra wrote:
On Wed, Jul 01, 2015 at 03:21:07PM -0700, Vikas Shivappa wrote:
+static inline bool cbm_is_contiguous(unsigned long var)
+{
+ unsigned long maxcbm = MAX_CBM_LENGTH;
+ unsigned long first_bit, zero_bit;
+
+ if (!var
On Fri, 24 Jul 2015, Thomas Gleixner wrote:
On Fri, 24 Jul 2015, Vikas Shivappa wrote:
On Fri, 24 Jul 2015, Thomas Gleixner wrote:
On Wed, 1 Jul 2015, Vikas Shivappa wrote:
Cache allocation patches(dependent on prep patches) adds a cgroup
subsystem to support the new Cache Allocation
Hello PeterZ,
On Fri, 24 Jul 2015, Thomas Gleixner wrote:
On Wed, 1 Jul 2015, Vikas Shivappa wrote:
Cache allocation patches(dependent on prep patches) adds a cgroup
subsystem to support the new Cache Allocation feature found in future
Intel Xeon Intel processors. Cache Allocation is a sub
On Fri, 24 Jul 2015, Thomas Gleixner wrote:
On Wed, 1 Jul 2015, Vikas Shivappa wrote:
Cache allocation patches(dependent on prep patches) adds a cgroup
subsystem to support the new Cache Allocation feature found in future
Intel Xeon Intel processors. Cache Allocation is a sub-feature
On Fri, 24 Jul 2015, Thomas Gleixner wrote:
On Wed, 1 Jul 2015, Vikas Shivappa wrote:
Cache allocation patches(dependent on prep patches) adds a cgroup
subsystem to support the new Cache Allocation feature found in future
Intel Xeon Intel processors. Cache Allocation is a sub-feature
Hello PeterZ,
On Fri, 24 Jul 2015, Thomas Gleixner wrote:
On Wed, 1 Jul 2015, Vikas Shivappa wrote:
Cache allocation patches(dependent on prep patches) adds a cgroup
subsystem to support the new Cache Allocation feature found in future
Intel Xeon Intel processors. Cache Allocation is a sub
On Fri, 24 Jul 2015, Thomas Gleixner wrote:
On Fri, 24 Jul 2015, Vikas Shivappa wrote:
On Fri, 24 Jul 2015, Thomas Gleixner wrote:
On Wed, 1 Jul 2015, Vikas Shivappa wrote:
Cache allocation patches(dependent on prep patches) adds a cgroup
subsystem to support the new Cache Allocation
Hello Thomas,
Just a ping for any feedback if any. Have tried to fix some issues you pointed
out in V11 and V12.
Thanks,
Vikas
On Wed, 1 Jul 2015, Vikas Shivappa wrote:
This patch has some changes to hot cpu handling code in existing cache
monitoring and RAPL kernel code. This improves
Hello Thomas,
Just a ping for any feedback if any. Have tried to fix some issues you pointed
out in V11 and V12.
Thanks,
Vikas
On Wed, 1 Jul 2015, Vikas Shivappa wrote:
This patch has some changes to hot cpu handling code in existing cache
monitoring and RAPL kernel code. This improves
of existing MSRs. Also the software cache for
IA32_PQR_ASSOC MSRs are updated during hot cpu notifications.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt.c | 95 ++---
1 file changed, 90 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/cpu
frequency.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 45 ++
arch/x86/include/asm/rdt_common.h | 25 +
arch/x86/include/asm/switch_to.h | 3 ++
arch/x86/kernel/cpu/intel_rdt.c| 17
cant CLOSids optimally.
- This also implies that during context switch, write to PQR-MSR is
done only when a task with a different bitmask is scheduled in.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 3 +
arch/x86/kernel/cpu/intel_rdt.c | 205 ++
data into the cache. The programming of the
hardware is done via programming MSRs(model specific registers).
More information about Cache allocation be found in the Intel (R) x86
Architecture Software Developer Manual,Volume 3, section 17.15.
Signed-off-by: Vikas Shivappa
---
arch/x86/include
search for the next online sibling during hot cpu exit, it uses
the same mapping instead of looping all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa
---
arch/x86/kern
.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt.c | 62 +++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 1f9716c..790cdba 100644
--- a/arch/x86/kernel
which may
be overlapping with other 'subsets'. This feature is used when
allocating a line in cache ie when pulling new data into the cache.
Signed-off-by: Vikas Shivappa
---
Documentation/cgroups/rdt.txt | 215 ++
1 file changed, 215 insertions(+)
create
an associated CLOSid. However if multiple cgroups
have the same cache mask they would also have the same CLOSid. The
reference count parameter in CLOSid-CBM map keeps track of how many
cgroups are using each CLOSid<->CBM mapping.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel
This patch has some changes to hot cpu handling code in existing cache
monitoring and RAPL kernel code. This improves hot cpu notification
handling by not looping through all online cpus which could be expensive
in large systems.
Cache allocation patches(dependent on prep patches) adds a cgroup
online sibling during cpu exit, it uses the
same map instead of looping through all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/perf_event_intel_cqm.
for the next online sibling during hot cpu exit, it uses
the same mapping instead of looping all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch
.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/kernel/cpu/intel_rdt.c | 62 +++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 1f9716c..790cdba
which may
be overlapping with other 'subsets'. This feature is used when
allocating a line in cache ie when pulling new data into the cache.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
Documentation/cgroups/rdt.txt | 215 ++
1 file
an associated CLOSid. However if multiple cgroups
have the same cache mask they would also have the same CLOSid. The
reference count parameter in CLOSid-CBM map keeps track of how many
cgroups are using each CLOSid-CBM mapping.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch
.
- This also implies that during context switch, write to PQR-MSR is
done only when a task with a different bitmask is scheduled in.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/include/asm/intel_rdt.h | 3 +
arch/x86/kernel/cpu/intel_rdt.c | 205
data into the cache. The programming of the
hardware is done via programming MSRs(model specific registers).
More information about Cache allocation be found in the Intel (R) x86
Architecture Software Developer Manual,Volume 3, section 17.15.
Signed-off-by: Vikas Shivappa vikas.shiva
This patch has some changes to hot cpu handling code in existing cache
monitoring and RAPL kernel code. This improves hot cpu notification
handling by not looping through all online cpus which could be expensive
in large systems.
Cache allocation patches(dependent on prep patches) adds a cgroup
sibling during cpu exit, it uses the
same map instead of looping through all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/kernel/cpu
of existing MSRs. Also the software cache for
IA32_PQR_ASSOC MSRs are updated during hot cpu notifications.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/kernel/cpu/intel_rdt.c | 95 ++---
1 file changed, 90 insertions(+), 5 deletions
frequency.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/include/asm/intel_rdt.h | 45 ++
arch/x86/include/asm/rdt_common.h | 25 +
arch/x86/include/asm/switch_to.h | 3 ++
arch/x86/kernel/cpu
search for the next online sibling during hot cpu exit, it uses
the same mapping instead of looping all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa
---
arch/x86/kern
data into the cache. The programming of the
hardware is done via programming MSRs(model specific registers).
More information about Cache allocation be found in the Intel (R) x86
Architecture Software Developer Manual,Volume 3, section 17.15.
Signed-off-by: Vikas Shivappa
---
arch/x86/include
which may
be overlapping with other 'subsets'. This feature is used when
allocating a line in cache ie when pulling new data into the cache.
Signed-off-by: Vikas Shivappa
---
Documentation/cgroups/rdt.txt | 215 ++
1 file changed, 215 insertions(+)
create
an associated CLOSid. However if multiple cgroups
have the same cache mask they would also have the same CLOSid. The
reference count parameter in CLOSid-CBM map keeps track of how many
cgroups are using each CLOSid<->CBM mapping.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel
cant CLOSids optimally.
- This also implies that during context switch, write to PQR-MSR is
done only when a task with a different bitmask is scheduled in.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 3 +
arch/x86/kernel/cpu/intel_rdt.c | 205 ++
frequency.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 45 ++
arch/x86/include/asm/rdt_common.h | 25 +
arch/x86/include/asm/switch_to.h | 3 ++
arch/x86/kernel/cpu/intel_rdt.c| 17
of existing MSRs. Also the software cache for
IA32_PQR_ASSOC MSRs are updated during hot cpu notifications.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt.c | 89 -
1 file changed, 87 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu
.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt.c | 62 +++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 28886be..10e1a5b 100644
--- a/arch/x86/kernel
online sibling during cpu exit, it uses the
same map instead of looping through all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/perf_event_intel_cqm.
This patch has some changes to hot cpu handling code in existing cache
monitoring and RAPL kernel code. This improves hot cpu notification
handling by not looping through all online cpus which could be expensive
in large systems.
Cache allocation patches(dependent on prep patches) adds a cgroup
frequency.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/include/asm/intel_rdt.h | 45 ++
arch/x86/include/asm/rdt_common.h | 25 +
arch/x86/include/asm/switch_to.h | 3 ++
arch/x86/kernel/cpu
for the next online sibling during hot cpu exit, it uses
the same mapping instead of looping all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch
data into the cache. The programming of the
hardware is done via programming MSRs(model specific registers).
More information about Cache allocation be found in the Intel (R) x86
Architecture Software Developer Manual,Volume 3, section 17.15.
Signed-off-by: Vikas Shivappa vikas.shiva
This patch has some changes to hot cpu handling code in existing cache
monitoring and RAPL kernel code. This improves hot cpu notification
handling by not looping through all online cpus which could be expensive
in large systems.
Cache allocation patches(dependent on prep patches) adds a cgroup
sibling during cpu exit, it uses the
same map instead of looping through all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/kernel/cpu
of existing MSRs. Also the software cache for
IA32_PQR_ASSOC MSRs are updated during hot cpu notifications.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/kernel/cpu/intel_rdt.c | 89 -
1 file changed, 87 insertions(+), 2 deletions
.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/kernel/cpu/intel_rdt.c | 62 +++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 28886be..10e1a5b
.
- This also implies that during context switch, write to PQR-MSR is
done only when a task with a different bitmask is scheduled in.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/include/asm/intel_rdt.h | 3 +
arch/x86/kernel/cpu/intel_rdt.c | 205
an associated CLOSid. However if multiple cgroups
have the same cache mask they would also have the same CLOSid. The
reference count parameter in CLOSid-CBM map keeps track of how many
cgroups are using each CLOSid-CBM mapping.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch
which may
be overlapping with other 'subsets'. This feature is used when
allocating a line in cache ie when pulling new data into the cache.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
Documentation/cgroups/rdt.txt | 215 ++
1 file
On Wed, 24 Jun 2015, Thomas Gleixner wrote:
On Tue, 23 Jun 2015, Vikas Shivappa wrote:
+/*
+ * cbm_update_msrs() - Updates all the existing IA32_L3_MASK_n MSRs
+ * which are one per CLOSid except IA32_L3_MASK_0 on the current package.
+ */
+static inline void cbm_update_msrs(void
On Wed, 24 Jun 2015, Thomas Gleixner wrote:
On Tue, 23 Jun 2015, Vikas Shivappa wrote:
This patch modifies hot cpu notification handling in Intel cache
monitoring:
- to add a new cpu to the cqm_cpumask(which has one cpu per package)
during cpu start, it uses the existing package<-&g
On Wed, 24 Jun 2015, Thomas Gleixner wrote:
On Tue, 23 Jun 2015, Vikas Shivappa wrote:
There is currently no cpumask helper function to pick a "random" cpu
from a mask which is also online.
cpumask_any_online_but() does that which is similar to cpumask_any_but()
but also ret
On Wed, 24 Jun 2015, Thomas Gleixner wrote:
On Tue, 23 Jun 2015, Vikas Shivappa wrote:
This patch modifies hot cpu notification handling in Intel cache
monitoring:
- to add a new cpu to the cqm_cpumask(which has one cpu per package)
during cpu start, it uses the existing package-core
On Wed, 24 Jun 2015, Thomas Gleixner wrote:
On Tue, 23 Jun 2015, Vikas Shivappa wrote:
There is currently no cpumask helper function to pick a random cpu
from a mask which is also online.
cpumask_any_online_but() does that which is similar to cpumask_any_but()
but also returns a cpu
On Wed, 24 Jun 2015, Thomas Gleixner wrote:
On Tue, 23 Jun 2015, Vikas Shivappa wrote:
+/*
+ * cbm_update_msrs() - Updates all the existing IA32_L3_MASK_n MSRs
+ * which are one per CLOSid except IA32_L3_MASK_0 on the current package.
+ */
+static inline void cbm_update_msrs(void
an associated CLOSid. However if multiple cgroups
have the same cache mask they would also have the same CLOSid. The
reference count parameter in CLOSid-CBM map keeps track of how many
cgroups are using each CLOSid<->CBM mapping.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel
which may
be overlapping with other 'subsets'. This feature is used when
allocating a line in cache ie when pulling new data into the cache.
Signed-off-by: Vikas Shivappa
---
Documentation/cgroups/rdt.txt | 215 ++
1 file changed, 215 insertions(+)
create
online sibling during cpu exit, it uses the
cpumask_any_online_but instead of looping through all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa
---
arch/x86/kern
data into the cache. The programming of the
hardware is done via programming MSRs(model specific registers).
More information about Cache allocation be found in the Intel (R) x86
Architecture Software Developer Manual,Volume 3, section 17.15.
Signed-off-by: Vikas Shivappa
---
arch/x86/include
of existing MSRs. Also the software cache for
IA32_PQR_ASSOC MSRs are updated during hot cpu notifications.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt.c | 84 -
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu
cant CLOSids optimally.
- This also implies that during context switch, write to PQR-MSR is
done only when a task with a different bitmask is scheduled in.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 3 +
arch/x86/kernel/cpu/intel_rdt.c | 205 ++
frequency.
Signed-off-by: Vikas Shivappa
---
arch/x86/include/asm/intel_rdt.h | 45 ++
arch/x86/include/asm/rdt_common.h | 25 +
arch/x86/include/asm/switch_to.h | 3 ++
arch/x86/kernel/cpu/intel_rdt.c| 17
.
Signed-off-by: Vikas Shivappa
---
arch/x86/kernel/cpu/intel_rdt.c | 62 +++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 24db9a0..e15dd96 100644
--- a/arch/x86/kernel
search for the next online sibling during hot cpu exit, it uses
the cpumask_any_online_but instead of looping all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa
---
arch/x86/kern
This patch has some preparatory patches which add a new API
cpumask_any_online_but and change hot cpu handling code in existing
cache monitoring and RAPL kernel code. This improves hot cpu
notification handling by not looping through all online cpus which could
be expensive in large systems.
There is currently no cpumask helper function to pick a "random" cpu
from a mask which is also online.
cpumask_any_online_but() does that which is similar to cpumask_any_but()
but also returns a cpu that is online.
Signed-off-by: Vikas Shivappa
---
include/linux/cpum
On Thu, 18 Jun 2015, Thomas Gleixner wrote:
On Thu, 18 Jun 2015, Kanaka Juvva wrote:
Added lock in event reader function. The cqm_pick_event_reader() function
accesses cqm_cpumask and it is critical section between this and
cqm_stable().
This situation is true when a CPU is hotplugged.
On Thu, 18 Jun 2015, Thomas Gleixner wrote:
On Thu, 18 Jun 2015, Kanaka Juvva wrote:
Added lock in event reader function. The cqm_pick_event_reader() function
accesses cqm_cpumask and it is critical section between this and
cqm_stable().
This situation is true when a CPU is hotplugged.
of existing MSRs. Also the software cache for
IA32_PQR_ASSOC MSRs are updated during hot cpu notifications.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/kernel/cpu/intel_rdt.c | 84 -
1 file changed, 82 insertions(+), 2 deletions
sibling during cpu exit, it uses the
cpumask_any_online_but instead of looping through all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86
data into the cache. The programming of the
hardware is done via programming MSRs(model specific registers).
More information about Cache allocation be found in the Intel (R) x86
Architecture Software Developer Manual,Volume 3, section 17.15.
Signed-off-by: Vikas Shivappa vikas.shiva
.
- This also implies that during context switch, write to PQR-MSR is
done only when a task with a different bitmask is scheduled in.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/include/asm/intel_rdt.h | 3 +
arch/x86/kernel/cpu/intel_rdt.c | 205
.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/kernel/cpu/intel_rdt.c | 62 +++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 24db9a0..e15dd96
frequency.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch/x86/include/asm/intel_rdt.h | 45 ++
arch/x86/include/asm/rdt_common.h | 25 +
arch/x86/include/asm/switch_to.h | 3 ++
arch/x86/kernel/cpu
which may
be overlapping with other 'subsets'. This feature is used when
allocating a line in cache ie when pulling new data into the cache.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
Documentation/cgroups/rdt.txt | 215 ++
1 file
an associated CLOSid. However if multiple cgroups
have the same cache mask they would also have the same CLOSid. The
reference count parameter in CLOSid-CBM map keeps track of how many
cgroups are using each CLOSid-CBM mapping.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
arch
There is currently no cpumask helper function to pick a random cpu
from a mask which is also online.
cpumask_any_online_but() does that which is similar to cpumask_any_but()
but also returns a cpu that is online.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
---
include/linux
This patch has some preparatory patches which add a new API
cpumask_any_online_but and change hot cpu handling code in existing
cache monitoring and RAPL kernel code. This improves hot cpu
notification handling by not looping through all online cpus which could
be expensive in large systems.
for the next online sibling during hot cpu exit, it uses
the cpumask_any_online_but instead of looping all online cpus. In
large systems with large number of cpus the time taken to loop may be
expensive and also the time increase linearly.
Signed-off-by: Vikas Shivappa vikas.shiva...@linux.intel.com
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Tue, 16 Jun 2015, Vikas Shivappa wrote:
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Fri, 12 Jun 2015, Vikas Shivappa wrote:
+static inline void intel_rdt_cpu_start(int cpu)
+{
+ struct intel_pqr_state *state = _cpu(pqr_state, cpu
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Tue, 16 Jun 2015, Vikas Shivappa wrote:
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Fri, 12 Jun 2015, Vikas Shivappa wrote:
+static inline void intel_rdt_cpu_start(int cpu)
+{
+ struct intel_pqr_state *state = per_cpu(pqr_state, cpu
On Tue, 16 Jun 2015, Peter Zijlstra wrote:
On Mon, Jun 15, 2015 at 02:44:32PM -0700, Vikas Shivappa wrote:
Secondly, there's more HSW models:
case 60: /* 22nm Haswell Core */
case 63: /* 22nm Haswell Server */
case 69: /* 22nm Haswell ULT */
case 70: /* 22nm Haswell
On Tue, 16 Jun 2015, Peter Zijlstra wrote:
On Mon, Jun 15, 2015 at 02:44:32PM -0700, Vikas Shivappa wrote:
Secondly, there's more HSW models:
case 60: /* 22nm Haswell Core */
case 63: /* 22nm Haswell Server */
case 69: /* 22nm Haswell ULT */
case 70: /* 22nm Haswell
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Fri, 12 Jun 2015, Vikas Shivappa wrote:
+static inline void intel_rdt_cpu_start(int cpu)
+{
+ struct intel_pqr_state *state = _cpu(pqr_state, cpu);
+
+ state->closid = 0;
+ mutex_lock(_group_mutex);
This is called f
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Mon, 15 Jun 2015, Vikas Shivappa wrote:
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:08AM -0700, Vikas Shivappa wrote:
+ cpumask_and(, cpu_online_mask, mask);
+ cpumask_clear_cpu(cpu, );
+ return
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Mon, 15 Jun 2015, Vikas Shivappa wrote:
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:08AM -0700, Vikas Shivappa wrote:
+ cpumask_and(tmp, cpu_online_mask, mask);
+ cpumask_clear_cpu(cpu, tmp
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Fri, 12 Jun 2015, Vikas Shivappa wrote:
+static inline void intel_rdt_cpu_start(int cpu)
+{
+ struct intel_pqr_state *state = per_cpu(pqr_state, cpu);
+
+ state-closid = 0;
+ mutex_lock(rdt_group_mutex);
This is called from
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:17AM -0700, Vikas Shivappa wrote:
+ /*
+* Probe test for Haswell CPUs.
+*/
+ if (c->x86 == 0x6 && c->x86_model == 0x3f)
+ return hsw_probetest();
Firstly,
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:12AM -0700, Vikas Shivappa wrote:
+ /* Additional Intel-defined flags: level 0x0010 */
+ if (c->cpuid_level >= 0x0010) {
+ u32 eax, ebx, ecx, edx;
+
+ cpuid
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:09AM -0700, Vikas Shivappa wrote:
static inline void cqm_pick_event_reader(int cpu)
{
- int phys_id = topology_physical_package_id(cpu);
- int i;
+ struct cpumask tmp;
No cpumasks on stacks.
ok
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:08AM -0700, Vikas Shivappa wrote:
There is currently no cpumask helper function to pick a "random" cpu
from a mask which is also online.
cpumask_any_online_but() does that which is similar to cpumask_any_but(
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:12AM -0700, Vikas Shivappa wrote:
+ /* Additional Intel-defined flags: level 0x0010 */
+ if (c-cpuid_level = 0x0010) {
+ u32 eax, ebx, ecx, edx;
+
+ cpuid_count(0x0010
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:08AM -0700, Vikas Shivappa wrote:
There is currently no cpumask helper function to pick a random cpu
from a mask which is also online.
cpumask_any_online_but() does that which is similar to cpumask_any_but()
but also
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:09AM -0700, Vikas Shivappa wrote:
static inline void cqm_pick_event_reader(int cpu)
{
- int phys_id = topology_physical_package_id(cpu);
- int i;
+ struct cpumask tmp;
No cpumasks on stacks.
ok
On Mon, 15 Jun 2015, Peter Zijlstra wrote:
On Fri, Jun 12, 2015 at 11:17:17AM -0700, Vikas Shivappa wrote:
+ /*
+* Probe test for Haswell CPUs.
+*/
+ if (c-x86 == 0x6 c-x86_model == 0x3f)
+ return hsw_probetest();
Firstly, isn't a probe already
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