Detecting platform supports i8042 or not, AMD resorted to
BIOS's FADT i8042 flag.
Signed-off-by: Vincent Wan
---
drivers/input/serio/i8042-x86ia64io.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/input/serio/i8042-x86ia64io.h
b/drivers/input/serio/i8042-x86ia64io.h
index
Detecting platform supports i8042 or not, AMD resorted to
BIOS's FADT i8042 flag.
Signed-off-by: Vincent Wan <vincent@amd.com>
---
drivers/input/serio/i8042-x86ia64io.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/input/serio/i8042-x86ia64io.h
b/drivers/input
This patch is to enable the quirk for AMD sdhci requiring transfer
mode register need to be cleared for commands without data
Signed-off-by: Vincent Wan
Signed-off-by: Wan Zongshun
---
drivers/mmc/host/sdhci-pci.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion
AMD SD controller supports the SDR104 mode, but caps2 can not
be promoted to support hs200 for eMMC.
Signed-off-by: Vincent Wan
Signed-off-by: Wan Zongshun
---
drivers/mmc/host/sdhci-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pci.c b
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms
Signed-off-by: Vincent Wan
Signed-off-by: Wan Zongshun
Signed-off-by: Arindam Nath
Tested-by: Vikram B
Tested
AMD SD controller support the SDR104 mode, but caps2 can not
be promoted to support hs200 for eMMC.
Signed-off-by: Vincent Wan
---
drivers/mmc/host/sdhci-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
On 2014年11月04日 15:51, Ulf Hansson wrote:
On 30 October 2014 05:06, Vincent Wan wrote:
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms.
Signed-off-by: Vincent
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms.
Signed-off-by: Vincent Wan
Signed-off-by: Arindam Nath
Cc: Huang Rui
Tested-by: Vikram B
Tested
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms.
Signed-off-by: Vincent Wan vincent@amd.com
Signed-off-by: Arindam Nath arindam.n...@amd.com
Cc: Huang Rui
On 2014年11月04日 15:51, Ulf Hansson wrote:
On 30 October 2014 05:06, Vincent Wan vincent@amd.com wrote:
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms
AMD SD controller support the SDR104 mode, but caps2 can not
be promoted to support hs200 for eMMC.
Signed-off-by: Vincent Wan vincent@amd.com
---
drivers/mmc/host/sdhci-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms
Signed-off-by: Vincent Wan vincent@amd.com
Signed-off-by: Wan Zongshun mcuos@gmail.com
Signed-off
AMD SD controller supports the SDR104 mode, but caps2 can not
be promoted to support hs200 for eMMC.
Signed-off-by: Vincent Wan vincent@amd.com
Signed-off-by: Wan Zongshun mcuos@gmail.com
---
drivers/mmc/host/sdhci-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
This patch is to enable the quirk for AMD sdhci requiring transfer
mode register need to be cleared for commands without data
Signed-off-by: Vincent Wan vincent@amd.com
Signed-off-by: Wan Zongshun mcuos@gmail.com
---
drivers/mmc/host/sdhci-pci.c | 27 ++-
1 file
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms.
Signed-off-by: Vincent Wan
Signed-off-by: Arindam Nath
Tested-by: Vikram B
Tested-by: Raghavendra Swamy
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms.
Signed-off-by: Vincent Wan vincent@amd.com
Signed-off-by: Arindam Nath arindam.n...@amd.com
Tested
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