On 04-02-21, 22:28, Vinod Koul wrote:
> This series adds support for UFS found in SM8350 SoC.
>
> We add binding for UFS phy and new regsiters for QMPv5 followed by UFS phy
> tables.
Applied, thanks
--
~Vinod
the phandle for binding
Changes in v5:
- rebase and revise binding based on Bjorn's qcom common TLMM binding
Changes in v4:
- rename to qcom,sm8350-tlmm along with binding and driver structs
- fix some nits in binding pointer by Rob
Vinod Koul (2):
dt-bindings: pinctrl: qcom: Add SM8350
Add device tree binding Documentation details for Qualcomm SM8350
pinctrl driver.
Reviewed-by: Bjorn Andersson
Reviewed-by: Rob Herring
Signed-off-by: Vinod Koul
---
.../bindings/pinctrl/qcom,sm8350-pinctrl.yaml | 145 ++
1 file changed, 145 insertions(+)
create mode 100644
This adds pincontrol driver for tlmm block found in SM8350 SoC
This patch is based on initial code downstream by Raghavendra.
Reviewed-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom/Makefile |1 +
drivers
Hello Greg,
Please pull to receive few phy driver fixes for v5.11.
Apologies for sending them bit late.
The following changes since commit d092bd9110494de3372722b317510b3692f1b2fe:
phy: mediatek: allow compile-testing the dsi phy (2021-01-04 13:00:54 +0530)
are available in the Git
Hello Jack,
On 04-02-21, 10:05, Jack Pham wrote:
> On Thu, Feb 04, 2021 at 10:39:03PM +0530, Vinod Koul wrote:
> > From: Jack Pham
> > +
> > + resets = < 20>;
>
> Shouldn't this (and all the other gcc phandles below) use the
> d
Add the registers for UFS found in SM8350. The UFS phy used in SM8350
seems to have same offsets as V5 phy, although Documentation for that is
lacking.
Signed-off-by: Vinod Koul
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 47 +
1 file changed, 47 insertions(+)
diff
Add the tables for init sequences for UFS QMP phy found in SM8350 SoC.
Reviewed-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 127
1 file changed, 127 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b
This series adds more support for smmu, usb and ufs to SM8350 and MTP. This
also adds regulator names which is very handy to have while looking at
regulators.
Jack Pham (2):
arm64: dts: qcom: sm8350: add USB and PHY device nodes
arm64: dts: qcom: sm8350-mtp: enable USB nodes
Vinod Koul (4
This adds UFS HC and UFS phy nodes to the SM8350 DTS
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 76
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index
This adds apss_smmu node to SM8350 DTS
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 105 +++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 29af0b931690
-3-ja...@codeaurora.org>
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 42 +
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts
b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts
index 8923657579fb..a2baa1ad3752 100644
From: Jack Pham
Add device nodes for the two instances each of USB3 controllers,
QMP SS PHYs and SNPS HS PHYs.
Signed-off-by: Jack Pham
Message-Id: <20210116013802.1609-2-ja...@codeaurora.org>
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi
Add the property "regulator-names" to the regulators as given in
schematics so that it is easier to understand the regulators being used
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 27 +
1 file changed, 27 insertions(+)
diff --
Enabled the UFS node found in SM8350-MTP platform, also add the
regulators associated with UFS HC and UFS phy to these nodes.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
This series adds support for UFS found in SM8350 SoC.
We add binding for UFS phy and new regsiters for QMPv5 followed by UFS phy
tables.
Vinod Koul (3):
dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
phy: qcom-qmp: Add UFS V5 registers found in SM8350
phy: qcom-qmp: Add support
Add the compatible strings for the UFS PHY found on SM8350 SoC.
Reviewed-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
b
Document "qcom,sm8250-ufshc" and "qcom,sm8350-ufshc" compatible string.
Use of "qcom,sm8250-ufshc" is already present upstream, so add misiing
documentation. "qcom,sm8350-ufshc" is for UFS HC found in SM8350 SoC.
Reviewed-by: Bjorn Andersson
Signed-of
On 03-02-21, 12:06, Enric Balletbo i Serra wrote:
> From: Boris Brezillon
>
> This patch adds the missing MODULE_DEVICE_TABLE definitions on different
> Mediatek phy drivers which generates correct modalias for automatic loading
> when these drivers are compiled as an external module.
Applied,
On 03-02-21, 10:58, Yang Li wrote:
> Eliminate the following coccicheck warning:
> ./drivers/phy/broadcom/phy-brcm-sata.c:654:2-3: Unneeded semicolon
Applied, thanks
--
~Vinod
On 31-01-21, 02:31, Konrad Dybcio wrote:
> This is required to bring up the PHY on MDM9607-based boards.
Applied, thanks
--
~Vinod
On 29-01-21, 16:03, Mauro Carvalho Chehab wrote:
> The phy USB3 driver for Hisilicon 970 (hi3670) is ready
> for mainstream. Mode it from staging into the main driver's
> phy/ directory.
Acked-By: Vinod Koul
--
~Vinod
On 29-01-21, 14:17, Geert Uytterhoeven wrote:
> The Intel Lightning Mountain (LGM) USB3 USB is only present on Intel
> Lightning Mountain SoCs. Hence add a dependency on X86, to prevent
> asking the user about this driver when configuring a kernel without
> Intel Lightning Mountain platform
On 29-01-21, 14:07, Steen Hegelund wrote:
> Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G
> interfaces available in the Sparx5 SoC.
>
> Signed-off-by: Bjarni Jonasson
> Signed-off-by: Steen Hegelund
> Reviewed-by: Andrew Lunn
> Reviewed-by: Alexandre Belloni
>
On 29-01-21, 14:07, Steen Hegelund wrote:
> Provide a new ethernet phy configuration structure, that
> allow PHYs used for ethernet to be configured with
> speed, media type and clock information.
This lgtm, Kishon ?
>
> Signed-off-by: Lars Povlsen
> Signed-off-by: Steen Hegelund
>
On 27-01-21, 20:08, Mauro Carvalho Chehab wrote:
> The phy USB3 driver for Hisilicon 970 (hi3670) is ready
> for mainstream. Mode it from staging into the main driver's
> phy/ directory.
I guess Greg will pick this, so:
Acked-By: Vinod Koul
--
~Vinod
On 26-01-21, 18:49, Greg Kroah-Hartman wrote:
> On Tue, Jan 19, 2021 at 11:44:38AM +0100, Mauro Carvalho Chehab wrote:
> > Hi Vinod/Rob,
> >
> > This series moves the Hikey 970 USB PHY driver out of staging.
> >
> > Patches 1 to 4 contain the fixes from staging. Patch 5 moves the
> > driver
On 19-01-21, 11:44, Mauro Carvalho Chehab wrote:
> The phy USB3 driver for Hisilicon 970 (hi3670) is ready
> for mainstream. Mode it from staging into the main driver's
> phy/ directory.
Acked-By: Vinod Koul
I think it makes sense if Greg applies this as well
--
~Vinod
On 20-01-21, 17:43, Bjorn Andersson wrote:
> Add compatibles for the Qualcomm QMP PHY binding for the SuperSpeed USB
> phys found in the SC8180x platform.
Applied, thanks
--
~Vinod
On 20-01-21, 14:45, Bjorn Andersson wrote:
> Add compatible for the SC8180x UFS PHY to the QMP binding.
Applied, thanks
--
~Vinod
On 02-02-21, 14:46, Yang Li wrote:
> Eliminate the following coccicheck warning:
> ./drivers/dma/qcom/gpi.c:1703:2-3: Unneeded semicolon
This was already fixed with commit 9ee8f3d968ae3dd838c379da7c9bfd335dbdcd95
--
~Vinod
; Cc: Scott Branden
> Cc: Pavel Machek
> Cc: Ulf Hansson
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Cc: Geert Uytterhoeven
> Cc: Linus Walleij
> Cc: Daniel Lezcano
> Cc: linux-cry...@vger.kernel.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-l...@vger.
On 02-02-21, 10:43, Pierre-Louis Bossart wrote:
>
>
> On 2/1/21 10:18 PM, Vinod Koul wrote:
> > On 01-02-21, 10:10, Pierre-Louis Bossart wrote:
> > > On 2/1/21 4:14 AM, Vinod Koul wrote:
> > > > On 21-01-21, 17:23, Srinivas Kandagatla wrote:
> > >
On 02-02-21, 10:52, Pierre-Louis Bossart wrote:
>
>
> On 2/1/21 10:39 PM, Vinod Koul wrote:
> > On 01-02-21, 10:18, Pierre-Louis Bossart wrote:
> > > On 2/1/21 4:38 AM, Vinod Koul wrote:
> > > > On 01-02-21, 15:58, Vinod Koul wrote:
> >
On 01-02-21, 15:50, Srinivas Kandagatla wrote:
>
>
> On 01/02/2021 14:21, Vinod Koul wrote:
> > On 29-01-21, 17:32, Srinivas Kandagatla wrote:
> > > Start the clock during initialization.
> >
> > A detailed log please, which clock..? Also how do old
On 01-02-21, 15:50, Srinivas Kandagatla wrote:
>
>
> On 01/02/2021 14:16, Vinod Koul wrote:
> > > /* Configure number of retries of a read/write cmd */
> > > - ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, SWRM_RD_WR_CMD_RETRIES);
> > >
On 01-02-21, 10:29, Pierre-Louis Bossart wrote:
>
> > >* Set SCP_INT1_MASK register, typically bus clash and
> > > diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
> > > index f7ba1a77a1df..c1fdc85d0a74 100644
> > > --- a/drivers/soundwire/intel.c
> > > +++
On 01-02-21, 10:20, Pierre-Louis Bossart wrote:
>
>
> On 2/1/21 4:42 AM, Vinod Koul wrote:
> > On 26-01-21, 16:37, Bard Liao wrote:
> > > There is nothing we can do to handle the bus clash interrupt before
> > > interrupt mask is enabled.
> > >
>
On 01-02-21, 10:18, Pierre-Louis Bossart wrote:
> On 2/1/21 4:38 AM, Vinod Koul wrote:
> > On 01-02-21, 15:58, Vinod Koul wrote:
> > > On 26-01-21, 16:37, Bard Liao wrote:
> >
> > > > struct sdw_master_prop {
> > > > u32 revision;
>
On 01-02-21, 10:10, Pierre-Louis Bossart wrote:
> On 2/1/21 4:14 AM, Vinod Koul wrote:
> > On 21-01-21, 17:23, Srinivas Kandagatla wrote:
> > > On 21/01/2021 15:12, Pierre-Louis Bossart wrote:
> > > > On 1/21/21 6:03 AM, Srinivas Kandagatla wrote:
> >
On 29-01-21, 17:32, Srinivas Kandagatla wrote:
> Add support to new interrupts and update irq routine in a way
> to deal with multiple pending interrupts with in a single interrupt!
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/soundwire/qcom.c | 191
On 29-01-21, 17:32, Srinivas Kandagatla wrote:
> In the existing code every soundwire register read and register write
> are kinda blocked. Each of these are using a special command id that
> generates interrupt after it successfully finishes. This is really
> overhead, limiting and not really
On 29-01-21, 17:32, Srinivas Kandagatla wrote:
> Start the clock during initialization.
A detailed log please, which clock..? Also how do older controllers work
w/o this clk
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/soundwire/qcom.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>
On 29-01-21, 17:32, Srinivas Kandagatla wrote:
> version 1.5.1 and higher IPs of this controller required to set
> continue execution on ingored command flag. This patch sets this flag.
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/soundwire/qcom.c | 12 +++-
> 1 file changed,
On 29-01-21, 17:32, Srinivas Kandagatla wrote:
> Some of the transport parameters derived from device tree
> are not fully parsed by the driver.
>
> This patch adds support to parse those missing parameters.
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/soundwire/qcom.c | 107
On 26-01-21, 16:37, Bard Liao wrote:
> From: Pierre-Louis Bossart
>
> We recently added the ability to discard bus clash interrupts reported
> on startup. These bus clash interrupts can happen randomly on some
> platforms and don't seem to be valid. A master-level quirk helped
> squelch those
On 26-01-21, 16:54, Bard Liao wrote:
> From: Chao Song
>
> If there is no slave attached to soundwire bus, we
> can return earlier from sdw_bus_prep_clk_stop() and
> sdw_bus_exit_clk_stop(), this saves a redundant value
> check.
Applied, thanks
--
~Vinod
On 26-01-21, 16:54, Bard Liao wrote:
> From: Pierre-Louis Bossart
>
> Add a dev_dbg() log for both enumeration and initialization completion
> to better track suspend-resume issues.
Applied, thanks
--
~Vinod
On 26-01-21, 16:37, Bard Liao wrote:
> There is nothing we can do to handle the bus clash interrupt before
> interrupt mask is enabled.
>
> Signed-off-by: Bard Liao
> Reviewed-by: Rander Wang
> Reviewed-by: Pierre-Louis Bossart
> ---
> drivers/soundwire/intel.c | 2 ++
> 1 file changed, 2
On 01-02-21, 15:58, Vinod Koul wrote:
> On 26-01-21, 16:37, Bard Liao wrote:
> > struct sdw_master_prop {
> > u32 revision;
> > @@ -421,8 +422,11 @@ struct sdw_master_prop {
> > u32 err_threshold;
> > u32 mclk_freq;
> > bool hw_disabled;
On 26-01-21, 16:37, Bard Liao wrote:
> The SoundWire specification allows a Slave device to report a bus clash
> with the in-band interrupt mechanism when it detects a conflict while
> driving a bitSlot it owns. This can be a symptom of an electrical conflict
> or a programming error, and it's
On 25-01-21, 16:23, Srinivas Kandagatla wrote:
>
>
> On 22/01/2021 16:42, Pierre-Louis Bossart wrote:
> > > >
> > > > if you completely remove the stream and re-add it with updated
> > > > configuration things should work.
> > >
> > > That's exactly what we do currently!
> > >
> > > The
On 21-01-21, 17:23, Srinivas Kandagatla wrote:
>
>
> On 21/01/2021 15:12, Pierre-Louis Bossart wrote:
> >
> >
> > On 1/21/21 6:03 AM, Srinivas Kandagatla wrote:
> > >
> > >
> > > On 19/01/2021 19:09, Pierre-Louis Bossart wrote:
> > > >
> > > > > currently we have
> > > > >
On 17-12-20, 17:23, Guanhua Gao wrote:
> This patch dupdates the DPDMAI interfaces to support MC firmware to
> 10.1x.x.
Threading is broken in this series, they do not appear together for me..
Can you explain what it means to support 10.1x.x...?
>
> Signed-off-by: Guanhua Gao
> ---
>
On 17-12-20, 17:23, Guanhua Gao wrote:
> In case of long format of qDMA command descriptor, there are one frame
> descriptor, three entries in the frame list and two data entries. So the
> size of dma_pool_create for these three fields should be the same with
> the total size of entries
On 29-01-21, 17:08, Richard Fitzgerald wrote:
> Use GFP_NOWAIT allocation in xilinx_dma_alloc_tx_descriptor().
>
> This is necessary for compatibility with ALSA, which calls
> dmaengine_prep_dma_cyclic() from an atomic context.
Applied, thanks
--
~Vinod
On 25-01-21, 09:32, Sia Jee Heng wrote:
> The below patch series are to support AxiDMA running on Intel KeemBay SoC.
> The base driver is dw-axi-dmac. This driver only support DMA memory copy
> transfers.
> Code refactoring is needed so that additional features can be supported.
> The features
loading/unloading driver
> - memory space definition for the data area and for the linked list space
> - scatter-gather address calculation on 32 bits platforms
> - minor comment and variable reordering
>
> Cc: Vinod Koul
> Cc: Dan Williams
> Cc: Bjorn Helgaas
> C
On 01-02-21, 11:52, mda...@codeaurora.org wrote:
> On 2021-02-01 11:35, Vinod Koul wrote:
> > On 27-01-21, 23:56, mda...@codeaurora.org wrote:
> > > The actual LOCK/UNLOCK flag should be set on hardware command
> > > descriptor.
> > > so this flag setting
On 27-01-21, 23:56, mda...@codeaurora.org wrote:
> On 2021-01-19 22:15, Vinod Koul wrote:
> > On 18-01-21, 09:21, mda...@codeaurora.org wrote:
> > > On 2021-01-15 11:28, Vinod Koul wrote:
> > > > On 14-01-21, 01:20, mda...@codeaurora.org wrote:
> > > &g
On 29-01-21, 14:17, Geert Uytterhoeven wrote:
> The Intel Lightning Mountain (LGM) DMA controller is only present on
> Intel Lightning Mountain SoCs. Hence add a dependency on X86, to
> prevent asking the user about this driver when configuring a kernel
> without Intel Lightning Mountain platform
On 29-01-21, 21:31, Grygorii Strashko wrote:
> Optimize struct psil_endpoint_config for size by
> - reordering fields
> - grouping bitfields
> - change mapped_channel_id type to s16 (32K channel is enough)
> - default_flow_id type to s16 as it's assigned to -1
>
> before:
> textdata
On 28-01-21, 09:44, Geert Uytterhoeven wrote:
> Hi Vinod,
>
> This patch series adds support for the Direct Memory Access Controller
> variant in the Renesas R-Car V3U (R8A779A0) SoC, to both DT bindings and
> driver.
Applied all, thanks
--
~Vinod
Hi Sai,
On 27-01-21, 18:37, Sai Prakash Ranjan wrote:
> Hi Vinod,
>
> On 2021-01-27 18:00, Vinod Koul wrote:
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = > IRQ_TYPE_LEVEL_LOW)>,
> &g
On 26-01-21, 16:18, Thara Gopinath wrote:
> When bam dma is "controlled remotely", thus far clocks were not controlled
> from the Linux. In this scenario, Linux was disabling runtime pm in bam dma
> driver and not doing any clock management in suspend/resume hooks.
>
> With introduction of crypto
Kryo685 is found in SM8350, so add it to the list of cpu compatibles
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml
b/Documentation/devicetree/bindings/arm
Add compatible for SM8150 and SM8350 SoCs.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
b/Documentation/devicetree/bindings/firmware/qcom
Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC
MTP board. This enabled uart node and adds rpmh-regulators present for
this board.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 250
Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC.
This adds gcc, pinctrl, reserved memory, uart, cpu nodes for this SoC.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 499 +++
1 file changed, 499 insertions(+)
create mode
Document the SM8350 SoC binding and also the boards using it.
Acked-by: Rob Herring
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
b/Documentation
by Rob recieved for v1
- Document cpu and scm compatible and use soc specific scm compatible
- Fix errors pointed by Rob and make dtbs_check as well as W=1 compilation
Vinod Koul (6):
dt-bindings: arm: qcom: Document SM8350 SoC and boards
soc: qcom: aoss: Add SM8350 compatible
dt-bindings
Add SM8350 compatible to the qcom_aoss binding and driver.
Acked-by: Rob Herring
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 +
drivers/soc/qcom/qcom_aoss.c | 1 +
2 files changed, 2 insertions(+)
diff --git
From: Vivek Aknurwar
This adds Global Clock controller (GCC) driver for SM8350 SoC
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Andersson
---
drivers/clk/qcom/Kconfig |8 +
drivers
Add device tree bindings for global clock controller on SM8350 SoCs.
Reviewed-by: Rob Herring
Reviewed-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
.../bindings/clock/qcom,gcc-sm8350.yaml | 96 +++
include/dt-bindings/clock/qcom,gcc-sm8350.h | 254 ++
2 files
From: Vivek Aknurwar
Lucid 5LPE is a slightly different Lucid PLL with different offsets and
porgramming sequence so add support for these
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
Reviewed
Driver uses regval variable for holding register values, replace with a
shorter one val
Suggested-by: Stephen Boyd
Reviewed-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/clk-alpha-pll.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff
and BRANCH_HALT_DELAY
Changes in v2:
- Add r-b from Bjorn
- Add the gcc_qupv3_wrap_1_{m|s}_ahb_clk and gcc_qupv3_wrap1_s5_clk
Vinod Koul (3):
clk: qcom: clk-alpha-pll: replace regval with val
clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate()
dt-bindings: clock: Add SM8350 GCC
Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but
with different registers. Modularize these by moving out latch and latch
ack bits so that we can reuse the function.
Suggested-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
Signed-off-by: Vinod Koul
On 21-01-21, 12:03, Lubomir Rintel wrote:
> Hi,
>
> please consider attaching the patches chained to this message.
>
> The last two are straighforward Kconfig changes that allow building mmp_tdma
> and mmp_pdma as modules so that distros that will choose to enable the
> drivers
> will not add
On 21-01-21, 12:12, Amireddy Mallikarjuna reddy wrote:
> There have been some fixes for JSON pointers and tools check now got this is
> missing a '/'.
> Add missing a '/' in '/schemas/types.yaml#definitions/uint32'
Already applied patch from Bjorn which came before this
--
~Vinod
On 20-01-21, 10:53, Paul Cercueil wrote:
> Add support for the JZ4760 and JZ4760B SoCs.
>
> Both SoCs have only 5 DMA channels per chip. The JZ4760B introduced the
> DCKES/DCKEC registers.
Applied after fixing subsystem name, thanks
--
~Vinod
On 20-01-21, 10:09, Bjorn Andersson wrote:
> The $ref for "intel,dma-poll-cnt" is missing an '/', causing
> dt_binding_check to fail. Fix this.
Applied, thanks
--
~Vinod
On 20-01-21, 10:53, Paul Cercueil wrote:
> Add ingenic,jz4760-dma and ingenic,jz4760b-dma compatible strings to
> support the DMA engines present in the JZ4760 and JZ4760B SoCs.
Applied, thanks
>
> Signed-off-by: Paul Cercueil
> ---
> Documentation/devicetree/bindings/dma/ingenic,dma.yaml | 2
On 24-01-21, 08:09, Christophe JAILLET wrote:
> In 'dma_pool_create()', we return -ENOMEM, but don't release the resources
> already allocated, as in all the other error handling paths.
>
> Go to 'err_res_free' instead of returning directly.
Applied, thanks
--
~Vinod
--
> drivers/dma/pl330.c | 3 +--
For dmaengine:
Acked-By: Vinod Koul
--
~Vinod
On 20-01-21, 14:18, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> A few Arm platforms are getting removed in v5.12, this removes
> the corresponding dmaengine drivers.
Thanks for the cleanup... Applied, thanks
--
~Vinod
On 25-01-21, 11:18, Bjorn Andersson wrote:
> On Sun 17 Jan 22:43 CST 2021, Vinod Koul wrote:
>
> > From: Vivek Aknurwar
> >
> > Lucid 5LPE is a slightly different Lucid PLL with different offsets and
> > porgramming sequence so add support for these
> >
On 25-01-21, 11:25, Bjorn Andersson wrote:
> On Sun 17 Jan 22:43 CST 2021, Vinod Koul wrote:
>
> > Add device tree bindings for global clock controller on SM8350 SoCs.
> >
> > Reviewed-by: Rob Herring
> > Signed-off-by: Vinod Koul
> > ---
> >
Add the tables for init sequences for UFS QMP phy found in SM8350 SoC.
Signed-off-by: Vinod Koul
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 127
1 file changed, 127 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom
Document "qcom,sm8250-ufshc" and "qcom,sm8350-ufshc" compatible string.
Use of "qcom,sm8250-ufshc" is already present upstream, so add misiing
documentation. "qcom,sm8350-ufshc" is for UFS HC found in SM8350 SoC.
Signed-off-by: Vinod Koul
---
Docu
subsystem.
Vinod Koul (4):
scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings
dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
phy: qcom-qmp: Add UFS v4 registers found in SM8350
phy: qcom-qmp: Add support for SM8350 UFS phy
.../devicetree/bindings/phy/qcom,qmp-phy.yaml
Add the compatible strings for the UFS PHY found on SM8350 SoC.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
b/Documentation/devicetree/bindings
Add the registers for few new registers found in SM8350. Also the UFS
phy used in SM8350 seems to have different offsets than V4 phy, although
it claims it is v4 phy, so add the new offsets with SM8350 tag instead
of V4 tag.
Signed-off-by: Vinod Koul
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 27
This adds pincontrol driver for tlmm block found in SM8350 SoC
This patch is based on initial code downstream by Raghavendra.
Signed-off-by: Raghavendra Rao Ananta
Signed-off-by: Jeevan Shriram
Signed-off-by: Vinod Koul
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom
This adds binding and driver for TLMM block found in SM8350 SoC
Changes in v5:
- rebase and revise binding based on Bjorn's qcom common TLMM binding
Changes in v4:
- rename to qcom,sm8350-tlmm along with binding and driver structs
- fix some nits in binding pointer by Rob
Vinod Koul (2
Add device tree binding Documentation details for Qualcomm SM8350
pinctrl driver.
Signed-off-by: Vinod Koul
---
.../bindings/pinctrl/qcom,sm8350-pinctrl.yaml | 146 ++
1 file changed, 146 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,sm8350
duced to just listing which of these properties should be checked for
> > - or further specified.
> >
> > Signed-off-by: Bjorn Andersson
Reviewed-by: Vinod Koul
> Overall it looks good, just cutting some slack for reviewers (especially
> DT people) before applying.
Yeah it d
On 19-01-21, 09:37, Jack Pham wrote:
> Add compatible strings for the USB DWC3 controller on QCOM SM8150,
> SM8250 and SM8350 SoCs.
>
> Note the SM8150 & SM8250 compatibles are already being used in the
> dts but was missing from the documentation.
Reviewed-by: Vinod Koul
--
~Vinod
On 18-01-21, 09:21, mda...@codeaurora.org wrote:
> On 2021-01-15 11:28, Vinod Koul wrote:
> > On 14-01-21, 01:20, mda...@codeaurora.org wrote:
> > > On 2021-01-12 15:40, Vinod Koul wrote:
> > > > On 12-01-21, 15:01, mda...@codeaurora.org wrote:
> > > > &g
On 15-01-21, 09:47, Jack Pham wrote:
> Add compatible strings for the USB DWC3 controller on QCOM SM8150,
> SM8250 and SM8350 SoCs.
>
> Note the SM8150 & SM8250 compatibles are already being used in the
> dts but was missing from the documentation.
Reviewed-by: Vinod Koul
--
~Vinod
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