er to your previous nuc900 series patches for SPARSE
IRQ, now I am waiting for rc1 release, and will send v3 patches.
>
> Arnd
--
---
Vincent Wan(Zongshun)
www.mcuos.com
2016-07-15 15:00 GMT+08:00 Arnd Bergmann :
> On Friday, July 15, 2016 1:15:58 PM CEST Wan Zongshun wrote:
>>
>> Actually, I have two choice to implement this function:
>>
>> option1:
>>
>> void __exception_irq_entry aic_handle_irq(struct p
On 2016年07月14日 21:54, Jason Cooper wrote:
Hi Wan Zongshun,
On Thu, Jul 14, 2016 at 11:36:53AM +0800, Wan Zongshun wrote:
On 2016年07月14日 04:09, Jason Cooper wrote:
On Sun, Jul 10, 2016 at 03:27:22PM +0800, Wan Zongshun wrote:
This patch is to add irqchip driver support for nuc900 plat
On 2016年07月12日 16:26, Arnd Bergmann wrote:
On Tuesday, July 12, 2016 3:04:42 PM CEST Wan Zongshun wrote:
Ideally, this should just go away once we use SPARSE_IRQ.
This platform also can use SPARSE_IRQ? this just a simple irq map and no
more irq number in this Soc.
SPARSE_IRQ is implied
On 2016年07月14日 04:09, Jason Cooper wrote:
Hi Wan Zongshun,
On Sun, Jul 10, 2016 at 03:27:22PM +0800, Wan Zongshun wrote:
This patch is to add irqchip driver support for nuc900 plat,
current this driver only supports nuc970 SoC.
Signed-off-by: Wan Zongshun
---
arch/arm/mach-w90x900
On 2016年07月12日 18:55, Joerg Roedel wrote:
Hey Vincent,
On Tue, Jul 12, 2016 at 05:03:08PM +0800, Wan Zongshun wrote:
Currently, those patches can not work at my eCarrizo board.
When I merged your patches, boot failed, and no any info print to me.
I set iommu=pt, it also does not work; set
On 2016年07月12日 23:39, Afzal Mohammed wrote:
Hi,
On Sun, Jul 10, 2016 at 03:42:20PM +0800, Wan Zongshun wrote:
This patch is to add dts support for nuc970 platform.
cpu ! in soc ? lost in fab ? ;)
Do you mean I should add cpus into soc like?
cpus {
#address-cells
On 2016年07月11日 16:03, Arnd Bergmann wrote:
On Sunday, July 10, 2016 3:27:26 PM CEST Wan Zongshun wrote:
+ ret = of_property_read_string(np, "compatible", &soc_dev_attr->soc_id);
+ if (ret)
return -EINVAL;
+
+ soc_dev_attr->
On 2016年07月08日 19:44, Joerg Roedel wrote:
Hi,
here is a patch-set to make the AMD IOMMU driver use the
generic IOVA allocator, which is already used in the Intel
VT-d driver and a few other places.
The main reason for the conversion is to make the driver
benefit from the recent scalability im
On 2016年07月11日 23:36, Arnd Bergmann wrote:
On Sunday, July 10, 2016 3:27:23 PM CEST Wan Zongshun wrote:
+config NUC900_TIMER
+bool "Clocksource timer for nuc900 platform" if COMPILE_TEST
+depends on ARM
+select CLKSRC_OF if OF
+select CLKSRC_MMIO
+
On 2016年07月12日 12:30, Wan Zongshun wrote:
On 2016年07月12日 00:04, Arnd Bergmann wrote:
On Sunday, July 10, 2016 3:27:21 PM CEST Wan Zongshun wrote:
+ifeq ($(CONFIG_SOC_NUC970),)
obj-y := irq.o time.o mfp.o gpio.o clock.o
obj-y += clksel.o
On 2016年07月11日 23:46, Arnd Bergmann wrote:
On Sunday, July 10, 2016 3:27:22 PM CEST Wan Zongshun wrote:
+
+#if !defined(CONFIG_SOC_NUC900)
#define NR_IRQS(IRQ_ADC+1)
+#else
+#define NR_IRQS62
+#endif
The Kconfig symbols are a bit confusing here
On 2016年07月12日 00:04, Arnd Bergmann wrote:
On Sunday, July 10, 2016 3:27:21 PM CEST Wan Zongshun wrote:
+ifeq ($(CONFIG_SOC_NUC970),)
obj-y := irq.o time.o mfp.o gpio.o clock.o
obj-y += clksel.o dev.o cpu.o
+endif
# W90X900 CPU support
2016-07-11 18:24 GMT+08:00 Arnd Bergmann :
> On Monday, July 11, 2016 5:07:01 PM CEST Wan Zongshun wrote:
>>
>> On 2016年07月11日 16:03, Arnd Bergmann wrote:
>> > On Sunday, July 10, 2016 3:27:26 PM CEST Wan Zongshun wrote:
>> >> + ret = of_
...@lists.linux-foundation.org
> https://lists.linuxfoundation.org/mailman/listinfo/iommu
--
---
Vincent Wan(Zongshun)
www.mcuos.com
On 2016年07月11日 15:19, Joerg Roedel wrote:
On Sun, Jul 10, 2016 at 07:40:53PM +0800, Wan Zongshun wrote:
Do you mean we need enable the V and TV bits to DTE entry after all
DTEs tables were initialized completely?
Yes, this is what my patch does and what fixes the bug that was
reported on
On 2016年07月11日 16:03, Arnd Bergmann wrote:
On Sunday, July 10, 2016 3:27:26 PM CEST Wan Zongshun wrote:
+ ret = of_property_read_string(np, "compatible", &soc_dev_attr->soc_id);
+ if (ret)
return -EINVAL;
+
+ soc_dev_attr->
On 2016年07月11日 05:56, Paul Gortmaker wrote:
On Sun, Jul 10, 2016 at 3:27 AM, Wan Zongshun wrote
This driver is to add reset support for nuc900 series,
currently, it only supports nuc970 SoC reset.
Signed-off-by: Wan Zongshun
---
drivers/power/reset/Kconfig| 7 +++
drivers/power
On 2016年07月11日 05:51, Paul Gortmaker wrote:
On Sun, Jul 10, 2016 at 3:27 AM, Wan Zongshun wrote:
This patch is to add irqchip driver support for nuc900 plat,
current this driver only supports nuc970 SoC.
Signed-off-by: Wan Zongshun
---
arch/arm/mach-w90x900/include/mach/irqs.h | 5
On 2016年07月11日 06:17, Arnd Bergmann wrote:
On Sunday, July 10, 2016 3:42:21 PM CEST Wan Zongshun wrote:
+
+Required properties:
+- compatible : Should be "nuvoton,nuc970-tmr"
+- reg : Address and length of the register set
+- clocks : Reference on the timer input clock
+-
On 2016年07月07日 00:00, Joerg Roedel wrote:
From: Joerg Roedel
There is a race condition in the AMD IOMMU init code that
causes requested unity mappings to be blocked by the IOMMU
for a short period of time. This results on boot failures
and IO_PAGE_FAULTs on some machines.
Fix this by making
Add nuc970_defconfig file support.
Signed-off-by: Wan Zongshun
---
arch/arm/configs/nuc970_defconfig | 76 +++
1 file changed, 76 insertions(+)
create mode 100644 arch/arm/configs/nuc970_defconfig
diff --git a/arch/arm/configs/nuc970_defconfig
b/arch/arm
This patch is to add dts description for nuc900 platform.
Signed-off-by: Wan Zongshun
---
.../devicetree/bindings/arm/nuvoton/nuc970.txt | 12
.../bindings/clock/nuvoton,nuc970-clk.txt | 13 +
.../interrupt-controller/nuvoton,nuc900-aic.txt| 15
This patch is to add dts support for nuc970 platform.
Signed-off-by: Wan Zongshun
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/nuc970-evb.dts | 34
arch/arm/boot/dts/nuc970.dtsi| 88
3 files changed, 123 insertions
This patch is to add clock framework driver for nuc970.
The clock controller generates all clocks for Video, Audio,
CPU, system bus and all functionalities, nuc970 includes
two PLL modules.
Signed-off-by: Wan Zongshun
---
drivers/clk/Makefile| 1 +
drivers/clk/nuc900/Makefile
and soc drivers, split some dts patches according to maillist's comments.
Wan Zongshun (10):
ARM: NUC900: Add nuc970 machine support
irqchip: add irqchip driver for nuc900
Clocksource: add nuc970 clocksource driver
clk: add Clock driver for nuc970
power/reset: Add reset driver suppor
This patch is to add SoC specific driver for nuc970 SoC,
it is for getting nuc970 version id and chip id.
Signed-off-by: Wan Zongshun
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/nuvoton/Kconfig | 10
drivers/soc/nuvoton/Makefile
resolution, and programmable counting period.
The timer can generate an interrupt signal upon timeout, or provide the
current value of count during operation.
Currently, we are using TIMER0 and TIMER1 for clocksource and clockevent
device driver support.
Signed-off-by: Wan Zongshun
---
drivers
NUC970 is a new SoC of Nuvoton nuc900 series, this patch is
to add machine file support for it.
Signed-off-by: Wan Zongshun
---
arch/arm/mach-w90x900/Kconfig | 20
arch/arm/mach-w90x900/Makefile | 3 +++
arch/arm/mach-w90x900/nuc900.c | 41
This driver is to add reset support for nuc900 series,
currently, it only supports nuc970 SoC reset.
Signed-off-by: Wan Zongshun
---
drivers/power/reset/Kconfig| 7 +++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/nuc900-reset.c | 93
This patch is to add nuc970 clock Macros header file
into include/dt-bindings/clock.
Signed-off-by: Wan Zongshun
---
include/dt-bindings/clock/nuc970-clock.h | 233 +++
1 file changed, 233 insertions(+)
create mode 100644 include/dt-bindings/clock/nuc970-clock.h
This patch is to add irqchip driver support for nuc900 plat,
current this driver only supports nuc970 SoC.
Signed-off-by: Wan Zongshun
---
arch/arm/mach-w90x900/include/mach/irqs.h | 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-nuc900.c | 150
On 2016年06月29日 23:27, Arnd Bergmann wrote:
On Saturday, June 25, 2016 6:37:20 PM CEST Wan Zongshun wrote:
+#define IRQ_WDTW90X900_IRQ(1)
+#define IRQ_WWDT W90X900_IRQ(2)
+#define IRQ_LVDW90X900_IRQ(3)
+#define IRQ_EXT0 W90X900_IRQ(4)
+#define
On 2016年06月28日 03:46, Daniel Lezcano wrote:
On 06/25/2016 12:37 PM, Wan Zongshun wrote:
This patch is to add nuc970 clocksource driver support.
Hi Wan,
add a detailed description of how works this timer and its general
design. If there is a pointer or a reference to a manual that would be
On 2016年06月29日 23:27, Arnd Bergmann wrote:
On Saturday, June 25, 2016 6:37:20 PM CEST Wan Zongshun wrote:
+#define IRQ_WDTW90X900_IRQ(1)
+#define IRQ_WWDT W90X900_IRQ(2)
+#define IRQ_LVDW90X900_IRQ(3)
+#define IRQ_EXT0 W90X900_IRQ(4)
+#define
On 2016年06月29日 23:25, Arnd Bergmann wrote:
On Saturday, June 25, 2016 6:37:19 PM CEST Wan Zongshun wrote:
This patch is to add nuc970 clocksource driver support.
Signed-off-by: Wan Zongshun
---
.../mach-w90x900/include/mach/nuc970-regs-timer.h | 44 +
drivers/clocksource/Kconfig
On 2016年06月29日 23:19, Arnd Bergmann wrote:
On Saturday, June 25, 2016 6:37:17 PM CEST Wan Zongshun wrote:
NUC970 is a new SoC of Nuvoton nuc900 series, this patch is
to add machine file support for it.
Signed-off-by: Wan Zongshun
Nice to see some activity on the port!
---
arch/arm
devid));
>
> - devid = e->devid;
> flags = e->flags;
>
Sure, thanks for your patch.
This is my fault.
> ret = add_acpi_hid_device(hid, uid, &devid, false);
> --
> 2.9.0
>
--
---
Vincent Wan(Zongshun)
www.mcuos.com
as dts, driver/clk, driver/clocksource
, driver/irqchip drivers.
The old w90x900 plat such as nuc910,nuc960 codes will also be changed
to new style according to nuc970 codes after those patches was accepted.
Wan Zongshun (6):
ARM: NUC900: Add nuc970 machine support
ARM: dts: nuc900: Add
This patch is to add nuc970 clocksource driver support.
Signed-off-by: Wan Zongshun
---
.../mach-w90x900/include/mach/nuc970-regs-timer.h | 44 +
drivers/clocksource/Kconfig| 8 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource
NUC970 is a new SoC of Nuvoton nuc900 series, this patch is
to add machine file support for it.
Signed-off-by: Wan Zongshun
---
arch/arm/mach-w90x900/Kconfig | 25
arch/arm/mach-w90x900/Makefile | 3 +
.../mach-w90x900/include/mach/nuc970-regs
Signed-off-by: Wan Zongshun
---
drivers/clk/Makefile| 1 +
drivers/clk/nuc900/Makefile | 6 +
drivers/clk/nuc900/clk-apll.c | 168
drivers/clk/nuc900/clk-ccf.h| 53 +++
drivers/clk/nuc900/clk-nuc970.c | 920
drivers/clk
This patch is to add irqchip driver support for nuc900 plat,
current this driver only supports nuc970 SoC.
Signed-off-by: Wan Zongshun
---
arch/arm/mach-w90x900/include/mach/irqs.h | 69 ++
.../mach-w90x900/include/mach/nuc970-regs-aic.h| 53 +++
drivers
This patch is to add dts support for nuc970 platform.
Signed-off-by: Wan Zongshun
---
.../devicetree/bindings/arm/nuvoton/nuc970.txt | 30 +++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/nuc970-evb.dts | 20 ++
arch/arm/boot/dts/nuc970
Add nuc970_defconfig file support.
Signed-off-by: Wan Zongshun
---
arch/arm/configs/nuc970_defconfig | 1278 +
1 file changed, 1278 insertions(+)
create mode 100644 arch/arm/configs/nuc970_defconfig
diff --git a/arch/arm/configs/nuc970_defconfig
b/arch/arm
as dts, driver/clk, driver/clocksource
, driver/irqchip drivers.
The old w90x900 plat such as nuc910,nuc960 codes will also be changed
to new style according to nuc970 codes after those patches was accepted.
Wan Zongshun (6):
ARM: NUC900: Add nuc970 machine support
ARM: dts: nuc900: Add
as dts, driver/clk, driver/clocksource
, driver/irqchip drivers.
The old w90x900 plat such as nuc910,nuc960 codes will also be changed
to new style according to nuc970 codes after those patches was accepted.
Wan Zongshun (6):
ARM: NUC900: Add nuc970 machine support
ARM: dts: nuc900: Add
as dts, driver/clk, driver/clocksource
, driver/irqchip drivers.
The old w90x900 plat such as nuc910,nuc960 codes will also be changed
to new style according to nuc970 codes after those patches was accepted.
Wan Zongshun (6):
ARM: NUC900: Add nuc970 machine support
ARM: dts: nuc900: Add
From: Wan Zongshun
This patch is to do the following:
1. Add error check for caller of iommu_device_create.
2. Add error check for caller of iommu_device_link and
move 'iommu = amd_iommu_rlookup_table[dev_data->devid]' out of
iommuv2 capability condition that make iommu_device_
2016-05-10 21:21 GMT+08:00 Wan Zongshun :
> From: Wan Zongshun
>
> AMD has more drivers will use ACPI to platform bus driver later,
> all those devices need iommu support, for example: eMMC driver.
>
> For latest AMD eMMC controller, it will utilize sdhci-acpi.c driver,
&g
Original Message
From: Baoquan HE
If not valid just skip reserving the old domain id.
Signed-off-by: Baoquan He
---
drivers/iommu/amd_iommu.c | 4
drivers/iommu/amd_iommu_init.c | 5 +++--
drivers/iommu/amd_iommu_types.h | 5 +
3 files changed, 8 insertion
Original Message
From: Baoquan HE
Here several things need be done:
1) Initialize amd_iommu_dev_table because it was set several times
since kdump kernel reboot. We don't need the set because we will
copy the content from old kernel.
2) Re-enable event/cmd buffer
3) In
Original Message
Add function copy_dev_tables to copy old DTE of the 1st kernel to
the new DTE table. Since all iommu share the same DTE table the
copy only need be done once as long as the physical address of
old DTE table is retrieved from iommu reg. Besides the old domain
i
Original Message
Add functions to check whether translation is already enabled in IOMMU.
Signed-off-by: Baoquan He
---
drivers/iommu/amd_iommu_init.c | 25 +
drivers/iommu/amd_iommu_types.h | 4
2 files changed, 29 insertions(+)
diff --git a/
From: Wan Zongshun
This patch is to do the following:
1. Add error check for caller of iommu_device_create.
2. Add error check for caller of iommu_device_link and
move 'iommu = amd_iommu_rlookup_table[dev_data->devid]' out of
iommuv2 capability condition that make iommu_device_
From: Wan Zongshun
AMD has more drivers will use ACPI to platform bus driver later,
all those devices need iommu support, for example: eMMC driver.
For latest AMD eMMC controller, it will utilize sdhci-acpi.c driver,
which will rely on platform bus to match device and driver, where we
will set
Original Message
On Thu, Apr 14, 2016 at 09:28:53AM -0400, Wan Zongshun wrote:
From: Wan Zongshun
AMD has more drivers will use ACPI to platform bus driver later,
all those devices need iommu support, such as eMMC acpi driver.
Signed-off-by: Wan Zongshun
---
drivers
e the following sequence : v1 ->v2->kfd,
drm.
iommuv1 -- rootfs_initcall(fn)
IOMMUV2 -- device_initcall(fn)
kfd module -- late_initcall(fn)
drm -- late_initcall(fn)
Thanks!
Wan Zongshun.
Luis
___
iommu mailing list
io...@lists.linux-found
From: Wan Zongshun
AMD has more drivers will use ACPI to platform bus driver later,
all those devices need iommu support, such as eMMC acpi driver.
Signed-off-by: Wan Zongshun
---
drivers/iommu/amd_iommu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/iommu/amd_iommu.c b
From: Wan Zongshun
AMD Uart DMA belongs to ACPI HID type device, and its driver
is basing on AMBA Bus, need also IOMMU support.
This patch is just to set the AMD iommu callbacks for amba bus.
Signed-off-by: Wan Zongshun
---
drivers/iommu/amd_iommu.c | 13 -
1 file changed, 12
From: Suravee Suthikulpanit
This patch modifies the existing struct ivhd_header,
which currently only support IVHD type 0x10, to add
new fields from IVHD type 11h and 40h.
It also modifies the pointer calculation to allow
support for IVHD type 11h and 40h
Signed-off-by: Suravee Suthikulpanit
-
From: Wan Zongshun
This patch introduces acpihid_map, which is used to store
the new IVHD device entry extracted from BIOS IVRS table.
It also provides a utility function add_acpi_hid_device(),
to add this types of devices to the map.
Signed-off-by: Wan Zongshun
Signed-off-by: Suravee
From: Wan Zongshun
There are some devices indentified using ACPI HID format in AMD chip.
This patch series enable iommu support for those ACPI HID device,
since the existing AMD iommu only supports PCI bus based device.
The latest public version of AMD IOMMU specification that describes
the
From: Suravee Suthikulpanit
This patch introduces a new kernel parameter, ivrs_acpihid.
This is used to override existing ACPI-HID IVHD device entry,
or add an entry in case it is missing in the IVHD.
Signed-off-by: Wan Zongshun
Signed-off-by: Suravee Suthikulpanit
---
Documentation/kernel
From: Wan Zongshun
Current IOMMU driver make assumption that the downstream devices are PCI.
With the newly added ACPI-HID IVHD device entry support, this is no
longer true. This patch is to add dev type check and to distinguish the
pci and acpihid device code path.
Signed-off-by: Wan Zongshun
From: Wan Zongshun
This patch is to make the call-sites of get_device_id aware of its
return value.
Signed-off-by: Wan Zongshun
---
drivers/iommu/amd_iommu.c | 51 +--
1 file changed, 41 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu
From: Wan Zongshun
This patch creates a new function for finding or creating an IOMMU
group for acpihid(ACPI Hardware ID) device.
The acpihid devices with the same devid will be put into same group and
there will have the same domain id and share the same page table.
Signed-off-by: Wan
.
[Vincent: fix the build error of IVHD_DEV_ACPI_HID flag not found]
Signed-off-by: Wan Zongshun
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 107 ++---
1 file changed, 78 insertions(+), 29 deletions(-)
diff --git a/drivers/iommu
From: Suravee Suthikulpanit
The IVHD header type 11h and 40h introduce the PCSup bit in
the EFR Register Image bit fileds. This should be used to
determine the IOMMU performance support instead of relying
on the PNCounters and PNBanks.
Note also that the PNCouters and PNBanks bits in the IOMMU
a
Original Message
Hi,
Since about 4.4, we've been seeing reports of this warning on every boot
from some users:
WARNING: CPU: 2 PID: 1 at drivers/iommu/amd_iommu_init.c:2301
amd_iommu_pc_get_set_reg_val+0xa8/0xe0()
Modules linked in:
CPU: 2 PID: 1 Comm: swapper/0 Not tainted
.
[Vincent: fix the build error of IVHD_DEV_ACPI_HID flag not found]
Signed-off-by: Wan Zongshun
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 107 ++---
1 file changed, 78 insertions(+), 29 deletions(-)
diff --git a/drivers/iommu
From: Wan Zongshun
AMD Uart DMA belongs to ACPI HID type device, and its driver
is basing on AMBA Bus, need also IOMMU support.
This patch is just to set the AMD iommu callbacks for amba bus.
Signed-off-by: Wan Zongshun
---
drivers/iommu/amd_iommu.c | 13 -
1 file changed, 12
From: Wan Zongshun
This patch introduces acpihid_map, which is used to store
the new IVHD device entry extracted from BIOS IVRS table.
It also provides a utility function add_acpi_hid_device(),
to add this types of devices to the map.
Signed-off-by: Wan Zongshun
Signed-off-by: Suravee
From: Wan Zongshun
This patch creates a new function for finding or creating an IOMMU
group for acpihid(ACPI Hardware ID) device.
The acpihid devices with the same devid will be put into same group and
there will have the same domain id and share the same page table.
Signed-off-by: Wan
From: Suravee Suthikulpanit
This patch introduces a new kernel parameter, ivrs_acpihid.
This is used to override existing ACPI-HID IVHD device entry,
or add an entry in case it is missing in the IVHD.
Signed-off-by: Wan Zongshun
Signed-off-by: Suravee Suthikulpanit
---
Documentation/kernel
From: Wan Zongshun
Current IOMMU driver make assumption that the downstream devices are PCI.
With the newly added ACPI-HID IVHD device entry support, this is no
longer true. This patch is to add dev type check and to distinguish the
pci and acpihid device code path.
Signed-off-by: Wan Zongshun
From: Wan Zongshun
This patch is to make the call-sites of get_device_id aware of its
return value.
Signed-off-by: Wan Zongshun
---
drivers/iommu/amd_iommu.c | 51 +--
1 file changed, 41 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu
From: Suravee Suthikulpanit
This patch modifies the existing struct ivhd_header, which currently
only support IVHD type 0x10, to add new fields from IVHD type 11h and 40h.
It also modifies the pointer calculation to allow support for IVHD type
11h and 40h
Signed-off-by: Suravee Suthikulpanit
--
From: Wan Zongshun
There are some devices indentified using ACPI HID format in AMD chip.
This patch series enable iommu support for those ACPI HID device,
since the existing AMD iommu only supports PCI bus based device.
The latest public version of AMD IOMMU specification that describes
the
From: Suravee Suthikulpanit
This patch modifies the existing struct ivhd_header, which currently
only support IVHD type 0x10, to add new fields from IVHD type 11h and 40h.
It also modifies the pointer calculation to allow support for IVHD type
11h and 40h
Signed-off-by: Suravee Suthikulpanit
--
From: Wan Zongshun
This patch series enable ACPI hardware ID device support,
There are some devices indentified using ACPI HID format in AMD chip.
This patch series enable iommu support for those ACPI HID device,
since the existing AMD iommu only supports PCI bus based device.
Suravee
From: Wan Zongshun
This patch creates a new function for finding or creating an IOMMU
group for acpihid(ACPI Hardware ID) device.
The acpihid devices with the same devid will be put into same group and
there will have the same domain id and share the same page table.
Signed-off-by: Wan
.
[Vincent: fix the build error of IVHD_DEV_ACPI_HID flag not found]
Signed-off-by: Wan Zongshun
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 107 ++---
1 file changed, 78 insertions(+), 29 deletions(-)
diff --git a/drivers/iommu
From: Wan Zongshun
Current IOMMU driver make assumption that the downstream devices are PCI.
With the newly added ACPI-HID IVHD device entry support, this is no
longer true. This patch is to add dev type check and to distinguish the
pci and acpihid device code path.
Signed-off-by: Wan Zongshun
From: Wan Zongshun
This patch introduces acpihid_map, which is used to store
the new IVHD device entry extracted from BIOS IVRS table.
It also provides a utility function add_acpi_hid_device(),
to add this types of devices to the map.
Signed-off-by: Wan Zongshun
Signed-off-by: Suravee
From: Suravee Suthikulpanit
This patch introduces a new kernel parameter, ivrs_acpihid.
This is used to override existing ACPI-HID IVHD device entry,
or add an entry in case it is missing in the IVHD.
Signed-off-by: Wan Zongshun
Signed-off-by: Suravee Suthikulpanit
---
Documentation/kernel
From: Wan Zongshun
Since uart dma is using AMD iommu, and it bases on amba bus.
So we need set callbacks for amba bus type firstly.
Signed-off-by: Wan Zongshun
---
drivers/iommu/amd_iommu.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu
ecessary.
>
> return 0;
> -
> err_unmap:
> unmap_iommu(iommu);
> error_free_seq_id:
> --
> 2.5.0
>
> ___
> iommu mailing list
> io...@lists.linux-foundation.org
> https://lists.linuxfoundation.org/mailman
2015-12-22 17:52 GMT+08:00 Andy Shevchenko :
> On Tue, Dec 22, 2015 at 6:40 PM, Wan Zongshun wrote:
>> From: Wan Zongshun
>>
>> This patch is to add software tuning functions for AMD hs200
>> mode.
>>
>> Signed-off-by: Wan Zongshun
>> --
idea, thanks.
>
>
>> + return err;
>> }
>>
>> ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>>
From: Wan Zongshun
This patch is to remove the SDHCI_QUIRK2_BROKEN_HS200 quirk and
enable the emmc hs200 mode for AMD current platforms.
Signed-off-by: Wan Zongshun
---
drivers/mmc/host/sdhci-pci-core.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/mmc/host
From: Wan Zongshun
This patch is to add software tuning functions for AMD hs200
mode.
Signed-off-by: Wan Zongshun
---
drivers/mmc/host/sdhci-pci-core.c | 146 ++
1 file changed, 146 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pci-core.c
b/drivers
From: Wan Zongshun
AMD hs200 mode tuning mode is not compatible with standard tuning process,
so we need .platform_execute_tuning callback support in sdhci-pci-core.c,
this patch is to do:
1. Add platform_execute_tuning callback in sdhci_pci_slot.
2. Implement
clk->ops->disable(clk);
> + spin_unlock_irqrestore(&clocks_lock, flags);
> }
> EXPORT_SYMBOL(clk_disable);
>
> diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c
> index 2c371ff..90ec250 100644
> --- a/arch/arm/mach-w90x900/clock.c
>
Detecting x86 platform supporting i8042 or not, we should resort
to BIOS's FADT i8042 flag per ACPI spec.
Currently, Windows is conforming to this spec, and request this
flag to detect i8042 supporting.
Signed-off-by: Wan Zongshun
---
drivers/input/serio/i8042-x86ia64io.h | 4
1
Commit-ID: 2167ceabf34163727ca4e283c0f030e3960932e5
Gitweb: http://git.kernel.org/tip/2167ceabf34163727ca4e283c0f030e3960932e5
Author: Wan Zongshun
AuthorDate: Fri, 30 Oct 2015 13:11:39 +0100
Committer: Ingo Molnar
CommitDate: Sun, 1 Nov 2015 11:26:23 +0100
x86/cpu: Add CLZERO
on, I doubt if
their BIOS is providing this i8024 flag.
So I have to implement my codes carefully.
>
>> + if (!(acpi_gbl_FADT.boot_flags & ACPI_FADT_8042))
>> + return -ENODEV;
>> + }
>
> --
> Regards/Gruss,
> Boris.
>
> ECO tip #101: Trim y
f clockevent
> devices, for example: ONESHOT_STOPPED.
>
> Cc: Wan ZongShun
> Signed-off-by: Viresh Kumar
> ---
> arch/arm/mach-w90x900/time.c | 51
>
> 1 file changed, 28 insertions(+), 23 deletions(-)
>
> diff --git a/ar
set_irq_flags calls. Some
> users also set IRQ_NOPROBE and this has been maintained although it is not
> clear that is really needed. There appears to be a great deal of blind
> Cc: Robert Jarzmik
> Cc: Simtec Linux Team
> Cc: Kukjin Kim
> Cc: Krzysztof Kozlowski
> Cc: Wan ZongShun
Change this quirk to apply to AMD Carrizo platform.
Signed-off-by: Wan ZongShun
Tested-by: Nath, Arindam
Tested-by: Ramesh, Ramya
---
drivers/mmc/host/sdhci-pci.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pci.c b
1 - 100 of 114 matches
Mail list logo
